Lines Matching refs:sarea_priv
746 x += dev_priv->sarea_priv->boxes[0].x1;
747 y += dev_priv->sarea_priv->boxes[0].y1;
775 if (dev_priv->sarea_priv->pfCurrentPage == 1) {
851 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
853 int nbox = sarea_priv->nbox;
854 drm_clip_rect_t *pbox = sarea_priv->boxes;
863 if (dev_priv->sarea_priv->pfCurrentPage == 1) {
889 dev_priv->sarea_priv->ctx_owner = 0;
966 dev_priv->sarea_priv->ctx_owner = 0;
1199 dev_priv->sarea_priv->ctx_owner = 0;
1206 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1270 dev_priv->sarea_priv->ctx_owner = 0;
1277 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1313 dev_priv->sarea_priv->last_clear++;
1317 RADEON_CLEAR_AGE(dev_priv->sarea_priv->last_clear);
1326 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1327 int nbox = sarea_priv->nbox;
1328 drm_clip_rect_t *pbox = sarea_priv->boxes;
1370 if (dev_priv->sarea_priv->pfCurrentPage == 0) {
1390 dev_priv->sarea_priv->last_frame++;
1394 RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame);
1404 int offset = (dev_priv->sarea_priv->pfCurrentPage == 1)
1409 dev_priv->sarea_priv->pfCurrentPage);
1427 OUT_RING_REG(RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base
1436 dev_priv->sarea_priv->last_frame++;
1437 dev_priv->sarea_priv->pfCurrentPage =
1438 1 - dev_priv->sarea_priv->pfCurrentPage;
1442 RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame);
1484 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1487 int nbox = sarea_priv->nbox;
1504 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1531 buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;
1581 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1588 int nbox = sarea_priv->nbox;
1622 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
2095 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2107 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2108 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
2111 sarea_priv->nbox * sizeof(depth_boxes[0])))
2141 if (dev_priv->sarea_priv->pfCurrentPage != 1)
2142 dev_priv->sarea_priv->pfCurrentPage = 0;
2173 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2180 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2181 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
2184 dev_priv->sarea_priv->ctx_owner = 0;
2195 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2241 if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
2243 &sarea_priv->context_state,
2244 sarea_priv->tex_state,
2245 sarea_priv->dirty)) {
2250 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
2260 prim.vc_format = dev_priv->sarea_priv->vc_format;
2278 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2334 if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
2336 &sarea_priv->context_state,
2337 sarea_priv->tex_state,
2338 sarea_priv->dirty)) {
2343 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
2356 prim.vc_format = dev_priv->sarea_priv->vc_format;
2496 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2535 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2578 if (sarea_priv->nbox == 1)
2579 sarea_priv->nbox = 0;
3097 dev_priv->sarea_priv->tiling_enabled = 0;
3102 dev_priv->sarea_priv->tiling_enabled = 1;
3148 if (dev_priv->sarea_priv &&
3149 dev_priv->sarea_priv->pfCurrentPage != 0)