Searched refs:BIT8 (Results 1 - 7 of 7) sorted by relevance

/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-arm/arch-integrator/
H A Dbits.h34 #define BIT8 0x00000100 macro
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/drivers/scsi/
H A Dtmscsim.h185 #define BIT8 0x00000100 macro
216 #define SRB_DATA_XFER BIT8
H A Ddc395x.h64 #define BIT8 0x00000100 macro
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/linux/
H A Dsynclink.h28 #define BIT8 0x0100 macro
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/drivers/char/
H A Dsynclink.c523 #define RXSTATUS_SHORT_FRAME BIT8
524 #define RXSTATUS_CODE_VIOLATION BIT8
585 #define MISCSTATUS_DSR BIT8
608 #define SICR_DSR_INACTIVE BIT8
609 #define SICR_DSR (BIT9+BIT8)
1668 usc_OutDmaReg(info, CDIR, BIT8+BIT0 );
4605 /* Note: must preserve state of BIT8 in DCAR */
4634 /* Note: must preserve state of BIT8 in DCAR */
4894 RegValue |= BIT9 + BIT8;
4896 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
[all...]
H A Dsynclink_gt.c431 #define IRQ_RXOVER BIT8
2346 if (gsr & (BIT8 << i))
4002 val |= BIT8;
4042 val |= BIT8;
4146 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4210 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4781 if (!(*(src+1) & (BIT9 + BIT8))) {
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/drivers/char/pcmcia/
H A Dsynclink_cs.c309 #define IRQ_TXFIFO BIT8 // transmit pool ready

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