Lines Matching refs:BIT8
523 #define RXSTATUS_SHORT_FRAME BIT8
524 #define RXSTATUS_CODE_VIOLATION BIT8
585 #define MISCSTATUS_DSR BIT8
608 #define SICR_DSR_INACTIVE BIT8
609 #define SICR_DSR (BIT9+BIT8)
1668 usc_OutDmaReg(info, CDIR, BIT8+BIT0 );
4605 /* Note: must preserve state of BIT8 in DCAR */
4634 /* Note: must preserve state of BIT8 in DCAR */
4894 RegValue |= BIT9 + BIT8;
4896 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
5051 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
5055 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break;
5102 info->mbre_bit = BIT8;
5103 outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */
5215 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break;
5216 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
5218 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 + BIT8; break;
6165 if (usc_InReg( info, RCSR ) & (BIT8 + BIT4 + BIT3 + BIT1))
7373 if ( status & (BIT8 + BIT3 + BIT1) ) {