1/*********************************************************************** 2;* File Name : TMSCSIM.H * 3;* TEKRAM DC-390(T) PCI SCSI Bus Master Host Adapter * 4;* Device Driver * 5;***********************************************************************/ 6/* $Id: tmscsim.h,v 1.1.1.1 2007/08/03 18:52:57 Exp $ */ 7 8#ifndef _TMSCSIM_H 9#define _TMSCSIM_H 10 11#include <linux/types.h> 12 13#define SCSI_IRQ_NONE 255 14 15#define MAX_ADAPTER_NUM 4 16#define MAX_SG_LIST_BUF 16 /* Not used */ 17#define MAX_SCSI_ID 8 18#define MAX_SRB_CNT 50 /* Max number of started commands */ 19 20#define SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40 MHz) */ 21 22/* 23;----------------------------------------------------------------------- 24; SCSI Request Block 25;----------------------------------------------------------------------- 26*/ 27struct dc390_srb 28{ 29//u8 CmdBlock[12]; 30 31struct dc390_srb *pNextSRB; 32struct dc390_dcb *pSRBDCB; 33struct scsi_cmnd *pcmd; 34struct scatterlist *pSegmentList; 35 36struct scatterlist Segmentx; /* make a one entry of S/G list table */ 37 38unsigned long SGBusAddr; /*;a segment starting address as seen by AM53C974A 39 in CPU endianness. We're only getting 32-bit bus 40 addresses by default */ 41unsigned long SGToBeXferLen; /*; to be xfer length */ 42unsigned long TotalXferredLen; 43unsigned long SavedTotXLen; 44unsigned long Saved_Ptr; 45u32 SRBState; 46 47u8 SRBStatus; 48u8 SRBFlag; /*; b0-AutoReqSense,b6-Read,b7-write */ 49 /*; b4-settimeout,b5-Residual valid */ 50u8 AdaptStatus; 51u8 TargetStatus; 52 53u8 ScsiPhase; 54s8 TagNumber; 55u8 SGIndex; 56u8 SGcount; 57 58u8 MsgCnt; 59u8 EndMessage; 60u8 SavedSGCount; 61 62u8 MsgInBuf[6]; 63u8 MsgOutBuf[6]; 64 65//u8 IORBFlag; /*;81h-Reset, 2-retry */ 66}; 67 68 69/* 70;----------------------------------------------------------------------- 71; Device Control Block 72;----------------------------------------------------------------------- 73*/ 74struct dc390_dcb 75{ 76struct dc390_dcb *pNextDCB; 77struct dc390_acb *pDCBACB; 78 79/* Queued SRBs */ 80struct dc390_srb *pGoingSRB; 81struct dc390_srb *pGoingLast; 82struct dc390_srb *pActiveSRB; 83u8 GoingSRBCnt; 84 85u32 TagMask; 86 87u8 TargetID; /*; SCSI Target ID (SCSI Only) */ 88u8 TargetLUN; /*; SCSI Log. Unit (SCSI Only) */ 89u8 DevMode; 90u8 DCBFlag; 91 92u8 CtrlR1; 93u8 CtrlR3; 94u8 CtrlR4; 95 96u8 SyncMode; /*; 0:async mode */ 97u8 NegoPeriod; /*;for nego. */ 98u8 SyncPeriod; /*;for reg. */ 99u8 SyncOffset; /*;for reg. and nego.(low nibble) */ 100}; 101 102 103/* 104;----------------------------------------------------------------------- 105; Adapter Control Block 106;----------------------------------------------------------------------- 107*/ 108struct dc390_acb 109{ 110struct Scsi_Host *pScsiHost; 111u16 IOPortBase; 112u8 IRQLevel; 113u8 status; 114 115u8 SRBCount; 116u8 AdapterIndex; /*; nth Adapter this driver */ 117u8 DCBCnt; 118 119u8 TagMaxNum; 120u8 ACBFlag; 121u8 Gmode2; 122u8 scan_devices; 123 124struct dc390_dcb *pLinkDCB; 125struct dc390_dcb *pLastDCB; 126struct dc390_dcb *pDCBRunRobin; 127 128struct dc390_dcb *pActiveDCB; 129struct dc390_srb *pFreeSRB; 130struct dc390_srb *pTmpSRB; 131 132u8 msgin123[4]; 133u8 Connected; 134u8 pad; 135 136#if defined(USE_SPINLOCKS) && USE_SPINLOCKS > 1 && (defined(CONFIG_SMP) || \ 137 DEBUG_SPINLOCKS > 0) 138spinlock_t lock; 139#endif 140u8 sel_timeout; 141u8 glitch_cfg; 142 143u8 MsgLen; 144u8 Ignore_IRQ; /* Not used */ 145 146struct pci_dev *pdev; 147 148unsigned long Cmds; 149u32 SelLost; 150u32 SelConn; 151u32 CmdInQ; 152u32 CmdOutOfSRB; 153 154struct dc390_srb TmpSRB; 155struct dc390_srb SRB_array[MAX_SRB_CNT]; /* 50 SRBs */ 156}; 157 158 159/*;-----------------------------------------------------------------------*/ 160 161 162#define BIT31 0x80000000 163#define BIT30 0x40000000 164#define BIT29 0x20000000 165#define BIT28 0x10000000 166#define BIT27 0x08000000 167#define BIT26 0x04000000 168#define BIT25 0x02000000 169#define BIT24 0x01000000 170#define BIT23 0x00800000 171#define BIT22 0x00400000 172#define BIT21 0x00200000 173#define BIT20 0x00100000 174#define BIT19 0x00080000 175#define BIT18 0x00040000 176#define BIT17 0x00020000 177#define BIT16 0x00010000 178#define BIT15 0x00008000 179#define BIT14 0x00004000 180#define BIT13 0x00002000 181#define BIT12 0x00001000 182#define BIT11 0x00000800 183#define BIT10 0x00000400 184#define BIT9 0x00000200 185#define BIT8 0x00000100 186#define BIT7 0x00000080 187#define BIT6 0x00000040 188#define BIT5 0x00000020 189#define BIT4 0x00000010 190#define BIT3 0x00000008 191#define BIT2 0x00000004 192#define BIT1 0x00000002 193#define BIT0 0x00000001 194 195/*;---UnitCtrlFlag */ 196#define UNIT_ALLOCATED BIT0 197#define UNIT_INFO_CHANGED BIT1 198#define FORMATING_MEDIA BIT2 199#define UNIT_RETRY BIT3 200 201/*;---UnitFlags */ 202#define DASD_SUPPORT BIT0 203#define SCSI_SUPPORT BIT1 204#define ASPI_SUPPORT BIT2 205 206/*;----SRBState machine definition */ 207#define SRB_FREE 0 208#define SRB_WAIT BIT0 209#define SRB_READY BIT1 210#define SRB_MSGOUT BIT2 /*;arbitration+msg_out 1st byte*/ 211#define SRB_MSGIN BIT3 212#define SRB_MSGIN_MULTI BIT4 213#define SRB_COMMAND BIT5 214#define SRB_START_ BIT6 /*;arbitration+msg_out+command_out*/ 215#define SRB_DISCONNECT BIT7 216#define SRB_DATA_XFER BIT8 217#define SRB_XFERPAD BIT9 218#define SRB_STATUS BIT10 219#define SRB_COMPLETED BIT11 220#define SRB_ABORT_SENT BIT12 221#define DO_SYNC_NEGO BIT13 222#define SRB_UNEXPECT_RESEL BIT14 223 224/*;---SRBstatus */ 225#define SRB_OK BIT0 226#define ABORTION BIT1 227#define OVER_RUN BIT2 228#define UNDER_RUN BIT3 229#define PARITY_ERROR BIT4 230#define SRB_ERROR BIT5 231 232/*;---ACBFlag */ 233#define RESET_DEV BIT0 234#define RESET_DETECT BIT1 235#define RESET_DONE BIT2 236 237/*;---DCBFlag */ 238#define ABORT_DEV_ BIT0 239 240/*;---SRBFlag */ 241#define DATAOUT BIT7 242#define DATAIN BIT6 243#define RESIDUAL_VALID BIT5 244#define ENABLE_TIMER BIT4 245#define RESET_DEV0 BIT2 246#define ABORT_DEV BIT1 247#define AUTO_REQSENSE BIT0 248 249/*;---Adapter status */ 250#define H_STATUS_GOOD 0 251#define H_SEL_TIMEOUT 0x11 252#define H_OVER_UNDER_RUN 0x12 253#define H_UNEXP_BUS_FREE 0x13 254#define H_TARGET_PHASE_F 0x14 255#define H_INVALID_CCB_OP 0x16 256#define H_LINK_CCB_BAD 0x17 257#define H_BAD_TARGET_DIR 0x18 258#define H_DUPLICATE_CCB 0x19 259#define H_BAD_CCB_OR_SG 0x1A 260#define H_ABORT 0x0FF 261 262/*; SCSI Status byte codes*/ 263/* The values defined in include/scsi/scsi.h, to be shifted << 1 */ 264 265#define SCSI_STAT_UNEXP_BUS_F 0xFD /*; Unexpect Bus Free */ 266#define SCSI_STAT_BUS_RST_DETECT 0xFE /*; Scsi Bus Reset detected */ 267#define SCSI_STAT_SEL_TIMEOUT 0xFF /*; Selection Time out */ 268 269/* cmd->result */ 270#define RES_TARGET 0x000000FF /* Target State */ 271#define RES_TARGET_LNX STATUS_MASK /* Only official ... */ 272#define RES_ENDMSG 0x0000FF00 /* End Message */ 273#define RES_DID 0x00FF0000 /* DID_ codes */ 274#define RES_DRV 0xFF000000 /* DRIVER_ codes */ 275 276#define MK_RES(drv,did,msg,tgt) ((int)(drv)<<24 | (int)(did)<<16 | (int)(msg)<<8 | (int)(tgt)) 277#define MK_RES_LNX(drv,did,msg,tgt) ((int)(drv)<<24 | (int)(did)<<16 | (int)(msg)<<8 | (int)(tgt)<<1) 278 279#define SET_RES_TARGET(who, tgt) do { who &= ~RES_TARGET; who |= (int)(tgt); } while (0) 280#define SET_RES_TARGET_LNX(who, tgt) do { who &= ~RES_TARGET_LNX; who |= (int)(tgt) << 1; } while (0) 281#define SET_RES_MSG(who, msg) do { who &= ~RES_ENDMSG; who |= (int)(msg) << 8; } while (0) 282#define SET_RES_DID(who, did) do { who &= ~RES_DID; who |= (int)(did) << 16; } while (0) 283#define SET_RES_DRV(who, drv) do { who &= ~RES_DRV; who |= (int)(drv) << 24; } while (0) 284 285/*;---Sync_Mode */ 286#define SYNC_DISABLE 0 287#define SYNC_ENABLE BIT0 288#define SYNC_NEGO_DONE BIT1 289#define WIDE_ENABLE BIT2 /* Not used ;-) */ 290#define WIDE_NEGO_DONE BIT3 /* Not used ;-) */ 291#define EN_TAG_QUEUEING BIT4 292#define EN_ATN_STOP BIT5 293 294#define SYNC_NEGO_OFFSET 15 295 296/*;---SCSI bus phase*/ 297#define SCSI_DATA_OUT 0 298#define SCSI_DATA_IN 1 299#define SCSI_COMMAND 2 300#define SCSI_STATUS_ 3 301#define SCSI_NOP0 4 302#define SCSI_NOP1 5 303#define SCSI_MSG_OUT 6 304#define SCSI_MSG_IN 7 305 306/*;----SCSI MSG BYTE*/ /* see scsi/scsi.h */ /* One is missing ! */ 307#define ABORT_TAG 0x0d 308 309/* 310 * SISC query queue 311 */ 312typedef struct { 313 dma_addr_t saved_dma_handle; 314} dc390_cmd_scp_t; 315 316/* 317;========================================================== 318; EEPROM byte offset 319;========================================================== 320*/ 321typedef struct _EEprom 322{ 323u8 EE_MODE1; 324u8 EE_SPEED; 325u8 xx1; 326u8 xx2; 327} EEprom, *PEEprom; 328 329#define REAL_EE_ADAPT_SCSI_ID 64 330#define REAL_EE_MODE2 65 331#define REAL_EE_DELAY 66 332#define REAL_EE_TAG_CMD_NUM 67 333 334#define EE_ADAPT_SCSI_ID 32 335#define EE_MODE2 33 336#define EE_DELAY 34 337#define EE_TAG_CMD_NUM 35 338 339#define EE_LEN 40 340 341/*; EE_MODE1 bits definition*/ 342#define PARITY_CHK_ BIT0 343#define SYNC_NEGO_ BIT1 344#define EN_DISCONNECT_ BIT2 345#define SEND_START_ BIT3 346#define TAG_QUEUEING_ BIT4 347 348/*; EE_MODE2 bits definition*/ 349#define MORE2_DRV BIT0 350#define GREATER_1G BIT1 351#define RST_SCSI_BUS BIT2 352#define ACTIVE_NEGATION BIT3 353#define NO_SEEK BIT4 354#define LUN_CHECK BIT5 355 356#define ENABLE_CE 1 357#define DISABLE_CE 0 358#define EEPROM_READ 0x80 359 360/* 361;========================================================== 362; AMD 53C974 Registers bit Definition 363;========================================================== 364*/ 365/* 366;==================== 367; SCSI Register 368;==================== 369*/ 370 371/*; Command Reg.(+0CH) (rw) */ 372#define DMA_COMMAND BIT7 373#define NOP_CMD 0 374#define CLEAR_FIFO_CMD 1 375#define RST_DEVICE_CMD 2 376#define RST_SCSI_BUS_CMD 3 377 378#define INFO_XFER_CMD 0x10 379#define INITIATOR_CMD_CMPLTE 0x11 380#define MSG_ACCEPTED_CMD 0x12 381#define XFER_PAD_BYTE 0x18 382#define SET_ATN_CMD 0x1A 383#define RESET_ATN_CMD 0x1B 384 385#define SEL_WO_ATN 0x41 /* currently not used */ 386#define SEL_W_ATN 0x42 387#define SEL_W_ATN_STOP 0x43 388#define SEL_W_ATN3 0x46 389#define EN_SEL_RESEL 0x44 390#define DIS_SEL_RESEL 0x45 /* currently not used */ 391#define RESEL 0x40 /* " */ 392#define RESEL_ATN3 0x47 /* " */ 393 394#define DATA_XFER_CMD INFO_XFER_CMD 395 396 397/*; SCSI Status Reg.(+10H) (r) */ 398#define INTERRUPT BIT7 399#define ILLEGAL_OP_ERR BIT6 400#define PARITY_ERR BIT5 401#define COUNT_2_ZERO BIT4 402#define GROUP_CODE_VALID BIT3 403#define SCSI_PHASE_MASK (BIT2+BIT1+BIT0) 404/* BIT2: MSG phase; BIT1: C/D physe; BIT0: I/O phase */ 405 406/*; Interrupt Status Reg.(+14H) (r) */ 407#define SCSI_RESET BIT7 408#define INVALID_CMD BIT6 409#define DISCONNECTED BIT5 410#define SERVICE_REQUEST BIT4 411#define SUCCESSFUL_OP BIT3 412#define RESELECTED BIT2 413#define SEL_ATTENTION BIT1 414#define SELECTED BIT0 415 416/*; Internal State Reg.(+18H) (r) */ 417#define SYNC_OFFSET_FLAG BIT3 418#define INTRN_STATE_MASK (BIT2+BIT1+BIT0) 419/* 0x04: Sel. successful (w/o stop), 0x01: Sel. successful (w/ stop) */ 420 421/*; Clock Factor Reg.(+24H) (w) */ 422#define CLK_FREQ_40MHZ 0 423#define CLK_FREQ_35MHZ (BIT2+BIT1+BIT0) 424#define CLK_FREQ_30MHZ (BIT2+BIT1) 425#define CLK_FREQ_25MHZ (BIT2+BIT0) 426#define CLK_FREQ_20MHZ BIT2 427#define CLK_FREQ_15MHZ (BIT1+BIT0) 428#define CLK_FREQ_10MHZ BIT1 429 430/*; Control Reg. 1(+20H) (rw) */ 431#define EXTENDED_TIMING BIT7 432#define DIS_INT_ON_SCSI_RST BIT6 433#define PARITY_ERR_REPO BIT4 434#define SCSI_ID_ON_BUS (BIT2+BIT1+BIT0) /* host adapter ID */ 435 436/*; Control Reg. 2(+2CH) (rw) */ 437#define EN_FEATURE BIT6 438#define EN_SCSI2_CMD BIT3 439 440/*; Control Reg. 3(+30H) (rw) */ 441#define ID_MSG_CHECK BIT7 442#define EN_QTAG_MSG BIT6 443#define EN_GRP2_CMD BIT5 444#define FAST_SCSI BIT4 /* ;10MB/SEC */ 445#define FAST_CLK BIT3 /* ;25 - 40 MHZ */ 446 447/*; Control Reg. 4(+34H) (rw) */ 448#define EATER_12NS 0 449#define EATER_25NS BIT7 450#define EATER_35NS BIT6 451#define EATER_0NS (BIT7+BIT6) 452#define REDUCED_POWER BIT5 453#define CTRL4_RESERVED BIT4 /* must be 1 acc. to AM53C974.c */ 454#define NEGATE_REQACKDATA BIT2 455#define NEGATE_REQACK BIT3 456 457#define GLITCH_TO_NS(x) (((~x>>6 & 2) >> 1) | ((x>>6 & 1) << 1 ^ (x>>6 & 2))) 458#define NS_TO_GLITCH(y) (((~y<<7) | ~((y<<6) ^ ((y<<5 & 1<<6) | ~0x40))) & 0xc0) 459 460/* 461;==================== 462; DMA Register 463;==================== 464*/ 465/*; DMA Command Reg.(+40H) (rw) */ 466#define READ_DIRECTION BIT7 467#define WRITE_DIRECTION 0 468#define EN_DMA_INT BIT6 469#define EN_PAGE_INT BIT5 /* page transfer interrupt enable */ 470#define MAP_TO_MDL BIT4 471#define DIAGNOSTIC BIT2 472#define DMA_IDLE_CMD 0 473#define DMA_BLAST_CMD BIT0 474#define DMA_ABORT_CMD BIT1 475#define DMA_START_CMD (BIT1+BIT0) 476 477/*; DMA Status Reg.(+54H) (r) */ 478#define PCI_MS_ABORT BIT6 479#define BLAST_COMPLETE BIT5 480#define SCSI_INTERRUPT BIT4 481#define DMA_XFER_DONE BIT3 482#define DMA_XFER_ABORT BIT2 483#define DMA_XFER_ERROR BIT1 484#define POWER_DOWN BIT0 485 486/*; DMA SCSI Bus and Ctrl.(+70H) */ 487#define EN_INT_ON_PCI_ABORT BIT25 488#define WRT_ERASE_DMA_STAT BIT24 489#define PW_DOWN_CTRL BIT21 490#define SCSI_BUSY BIT20 491#define SCLK BIT19 492#define SCAM BIT18 493#define SCSI_LINES 0x0003ffff 494 495/* 496;========================================================== 497; SCSI Chip register address offset 498;========================================================== 499;Registers are rw unless declared otherwise 500*/ 501#define CtcReg_Low 0x00 /* r curr. transfer count */ 502#define CtcReg_Mid 0x04 /* r */ 503#define CtcReg_High 0x38 /* r */ 504#define ScsiFifo 0x08 505#define ScsiCmd 0x0C 506#define Scsi_Status 0x10 /* r */ 507#define INT_Status 0x14 /* r */ 508#define Sync_Period 0x18 /* w */ 509#define Sync_Offset 0x1C /* w */ 510#define Clk_Factor 0x24 /* w */ 511#define CtrlReg1 0x20 512#define CtrlReg2 0x2C 513#define CtrlReg3 0x30 514#define CtrlReg4 0x34 515#define DMA_Cmd 0x40 516#define DMA_XferCnt 0x44 /* rw starting transfer count (32 bit) */ 517#define DMA_XferAddr 0x48 /* rw starting physical address (32 bit) */ 518#define DMA_Wk_ByteCntr 0x4C /* r working byte counter */ 519#define DMA_Wk_AddrCntr 0x50 /* r working address counter */ 520#define DMA_Status 0x54 /* r */ 521#define DMA_MDL_Addr 0x58 /* rw starting MDL address */ 522#define DMA_Wk_MDL_Cntr 0x5C /* r working MDL counter */ 523#define DMA_ScsiBusCtrl 0x70 /* rw SCSI Bus, PCI/DMA Ctrl */ 524 525#define StcReg_Low CtcReg_Low /* w start transfer count */ 526#define StcReg_Mid CtcReg_Mid /* w */ 527#define StcReg_High CtcReg_High /* w */ 528#define Scsi_Dest_ID Scsi_Status /* w */ 529#define Scsi_TimeOut INT_Status /* w */ 530#define Intern_State Sync_Period /* r */ 531#define Current_Fifo Sync_Offset /* r Curr. FIFO / int. state */ 532 533 534#define DC390_read8(address) \ 535 (inb (pACB->IOPortBase + (address))) 536 537#define DC390_read8_(address, base) \ 538 (inb ((u16)(base) + (address))) 539 540#define DC390_read16(address) \ 541 (inw (pACB->IOPortBase + (address))) 542 543#define DC390_read32(address) \ 544 (inl (pACB->IOPortBase + (address))) 545 546#define DC390_write8(address,value) \ 547 outb ((value), pACB->IOPortBase + (address)) 548 549#define DC390_write8_(address,value,base) \ 550 outb ((value), (u16)(base) + (address)) 551 552#define DC390_write16(address,value) \ 553 outw ((value), pACB->IOPortBase + (address)) 554 555#define DC390_write32(address,value) \ 556 outl ((value), pACB->IOPortBase + (address)) 557 558 559#endif /* _TMSCSIM_H */ 560