/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mm/ |
H A D | tlb-fa.S | 42 mcr p15, 0, r3, c7, c10, 4 @ drain WB 45 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry 49 mcr p15, 0, r3, c7, c5, 6 @ invalidate BTB 50 mcr p15, 0, r3, c7, c10, 4 @ data write barrier 56 mcr p15, 0, r3, c7, c10, 4 @ drain WB 59 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry 63 mcr p15, 0, r3, c7, c5, 6 @ invalidate BTB 64 mcr p15, 0, r3, c7, c10, 4 @ data write barrier 65 mcr p15, 0, r3, c7, c5, 4 @ prefetch flush
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H A D | cache-v4.S | 33 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache 52 mcreq p15, 0, ip, c7, c7, 0 @ flush ID cache 107 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
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H A D | cache-fa.S | 56 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache 58 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 59 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 60 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer 61 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush 81 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line 82 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 87 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 88 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier 89 mcrne p15, 0, ip, c7, c [all...] |
H A D | proc-fa526.S | 63 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 64 mcr p15, 0, ip, c7, c10, 4 @ drain WB 66 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 82 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 87 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 91 mcr p15, 0, r0, c7, c10, 4 @ drain WB 108 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 110 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache 112 mcr p15, 0, ip, c7, c [all...] |
H A D | proc-mohawk.S | 74 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 75 mcr p15, 0, ip, c7, c10, 4 @ drain WB 76 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 91 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 92 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt 113 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache 115 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 116 mcrne p15, 0, ip, c7, c10, 0 @ drain write buffer 137 mcr p15, 0, r0, c7, c1 [all...] |
H A D | cache-v6.S | 29 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 30 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 31 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 32 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 50 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate 52 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 57 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate 120 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line 128 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 130 mcr p15, 0, r0, c7, c [all...] |
H A D | proc-arm920.S | 90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 91 mcr p15, 0, ip, c7, c10, 4 @ drain WB 93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 132 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 139 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 158 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 160 mcrne p15, 0, r0, c7, c [all...] |
H A D | proc-arm922.S | 92 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 93 mcr p15, 0, ip, c7, c10, 4 @ drain WB 95 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 134 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 140 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 141 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 160 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 162 mcrne p15, 0, r0, c7, c [all...] |
H A D | proc-arm1020.S | 100 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 101 mcr p15, 0, ip, c7, c10, 4 @ drain WB 103 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 116 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 140 mcr p15, 0, ip, c7, c10, 4 @ drain WB 143 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 144 mcr p15, 0, ip, c7, c10, 4 @ drain WB 152 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 154 mcrne p15, 0, ip, c7, c1 [all...] |
H A D | proc-arm1020e.S | 100 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 101 mcr p15, 0, ip, c7, c10, 4 @ drain WB 103 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 116 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 140 mcr p15, 0, ip, c7, c10, 4 @ drain WB 143 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 151 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 153 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 173 1: mcr p15, 0, r0, c7, c1 [all...] |
H A D | proc-arm1022.S | 89 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 90 mcr p15, 0, ip, c7, c10, 4 @ drain WB 92 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 105 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 131 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 139 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 141 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 161 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 168 mcrne p15, 0, ip, c7, c [all...] |
H A D | proc-arm1026.S | 89 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 90 mcr p15, 0, ip, c7, c10, 4 @ drain WB 92 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 105 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 129 1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate 134 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 136 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 156 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 163 mcrne p15, 0, ip, c7, c [all...] |
H A D | proc-arm925.S | 71 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 72 mcr p15, 0, ip, c7, c10, 4 @ drain WB 74 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 91 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 94 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 117 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 121 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 126 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 127 mcrne p15, 0, ip, c7, c1 [all...] |
H A D | proc-arm926.S | 82 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 83 mcr p15, 0, ip, c7, c10, 4 @ drain WB 85 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 102 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 132 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 134 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate 138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 139 mcrne p15, 0, ip, c7, c1 [all...] |
H A D | cache-v4wb.S | 68 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 85 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer 102 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 107 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 108 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 113 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer 154 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 155 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 160 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 161 mcr p15, 0, ip, c7, c1 [all...] |
H A D | cache-v4wt.S | 61 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 62 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 80 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 82 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 113 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 130 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache 147 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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H A D | proc-xsc3.S | 72 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line 116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB 121 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs 138 mcr p14, 0, r0, c7, c0, 0 @ go to idle 163 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB 164 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier 165 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush 186 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line 187 mcr p15, 0, r0, c7, c1 [all...] |
H A D | proc-arm946.S | 60 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 61 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 62 mcr p15, 0, ip, c7, c10, 4 @ drain WB 74 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 93 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 97 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index 104 mcrne p15, 0, ip, c7, c5, 0 @ flush I cache 105 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 127 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 128 mcrne p15, 0, r0, c7, c [all...] |
H A D | tlb-v6.S | 39 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer 52 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1) 57 mcr p15, 0, ip, c7, c5, 6 @ flush BTAC/BTB 58 mcr p15, 0, ip, c7, c10, 4 @ data synchronization barrier 71 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer 81 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA 86 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 87 mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier 88 mcr p15, 0, r2, c7, c5, 4 @ prefetch flush
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H A D | proc-arm940.S | 53 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 54 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 55 mcr p15, 0, ip, c7, c10, 4 @ drain WB 67 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 98 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 102 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index 109 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 110 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 152 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index 157 mcr p15, 0, ip, c7, c [all...] |
H A D | proc-arm720.S | 80 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache 82 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4) 106 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache 108 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4) 121 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches 123 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4) 149 mcr p15, 0, r0, c7, c [all...] |
H A D | proc-sa110.S | 67 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 68 mcr p15, 0, ip, c7, c10, 4 @ drain WB 70 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 117 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 138 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 154 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 155 mcr p15, 0, r0, c7, c10, 4 @ drain WB 164 mcr p15, 0, r10, c7, c7 [all...] |
H A D | tlb-v7.S | 47 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate U MVA 54 mcr p15, 0, ip, c7, c1, 6 @ flush BTAC/BTB Inner Shareable 56 mcr p15, 0, ip, c7, c5, 6 @ flush BTAC/BTB 80 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate U MVA 87 mcr p15, 0, r2, c7, c1, 6 @ flush BTAC/BTB Inner Shareable 89 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-msm/ |
H A D | idle.S | 14 mcr p15, 0, r0, c7, c10, 0 /* flush the cache */ 15 mcr p15, 0, r0, c7, c10, 4 /* memory barrier */ 16 mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-s3c2412/ |
H A D | sleep.S | 52 mcr p15, 0, r0, c7, c10, 4 53 mcrne p15, 0, r0, c7, c0, 4
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