Searched refs:SDRAM (Results 1 - 24 of 24) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-pnx4008/
H A Dsleep.S4 * PNX4008 support for STOP mode and SDRAM self-refresh
40 @ setup SDRAM controller base address in r2
48 @ clear SDRAM self-refresh bit latch
50 @ clear SDRAM self-refresh bit
57 @ set SDRAM self-refresh bit
61 @ set SDRAM self-refresh bit latch
65 @ clear SDRAM self-refresh bit latch
69 @ clear SDRAM self-refresh bit
73 @ wait for SDRAM to get into self-refresh mode
78 @ to prepare SDRAM t
[all...]
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-s3c2410/
H A Dsleep.S52 orr r7, r7, #S3C2410_REFRESH_SELF @ SDRAM sleep command
53 orr r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals
64 streq r7, [ r4 ] @ SDRAM sleep command
65 streq r8, [ r5 ] @ SDRAM power-down config
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/cris/arch-v10/lib/
H A Dhw_settings.S33 ; SDRAM or EDO DRAM?
H A Ddram_init.S2 * DRAM/SDRAM initialization - alter with care
42 ; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/frv/kernel/
H A Dcmode.S24 #define __addr_SDRAMC 0xfe000400 /* SDRAM controller regs */
25 #define SDRAMC_DSTS 0x28 /* SDRAM status */
26 #define SDRAMC_DSTS_SSI 0x00000001 /* indicates that the SDRAM is in self-refresh mode */
27 #define SDRAMC_DRCN 0x30 /* SDRAM refresh control */
28 #define SDRAMC_DRCN_SR 0x00000001 /* transition SDRAM into self-refresh mode */
76 # to access SDRAM and the internal resources.
106 # (6) Execute loading the dummy for SDRAM.
109 # (7) Set '1' to the DRCN.SR bit, and change SDRAM to the
144 # (14) Release the self-refresh of SDRAM.
H A Dhead-mmu-fr451.S40 # describe the position and layout of the SDRAM controller registers
44 # GR11 - displacement of 2nd SDRAM addr reg from GR14
45 # GR12 - displacement of 3rd SDRAM addr reg from GR14
46 # GR13 - displacement of 4th SDRAM addr reg from GR14
47 # GR14 - address of 1st SDRAM addr reg
48 # GR15 - amount to shift address by to match SDRAM addr reg
168 # determine the total SDRAM size
171 # GR25 - SDRAM size
183 sethi.p %hi(0xfe000000),gr17 ; unused SDRAM DBR value
225 # GR25 SDRAM siz
[all...]
H A Dhead-uc-fr401.S39 # describe the position and layout of the SDRAM controller registers
43 # GR11 - displacement of 2nd SDRAM addr reg from GR14
44 # GR12 - displacement of 3rd SDRAM addr reg from GR14
45 # GR13 - displacement of 4th SDRAM addr reg from GR14
46 # GR14 - address of 1st SDRAM addr reg
47 # GR15 - amount to shift address by to match SDRAM addr reg
173 # determine the total SDRAM size
176 # GR25 - SDRAM size
188 sethi.p %hi(0xfe000000),gr17 ; unused SDRAM DBR value
236 # GR25 SDRAM siz
[all...]
H A Dhead-uc-fr555.S38 # describe the position and layout of the SDRAM controller registers
42 # GR11 - displacement of 2nd SDRAM addr reg from GR14
43 # GR12 - displacement of 3rd SDRAM addr reg from GR14
44 # GR13 - displacement of 4th SDRAM addr reg from GR14
45 # GR14 - address of 1st SDRAM addr reg
46 # GR15 - amount to shift address by to match SDRAM addr reg
161 # determine the total SDRAM size
164 # GR25 - SDRAM size
176 sethi.p %hi(0xfff),gr17 ; unused SDRAM AMK value
220 # GR25 SDRAM siz
[all...]
H A Dsleep.S27 #define FR55X_SDRAMC_DSTS_SSI 0x00000002 /* indicates that the SDRAM is in self-refresh mode */
31 #define FR4XX_SDRAMC_DSTS_SSI 0x00000001 /* indicates that the SDRAM is in self-refresh mode */
33 #define SDRAMC_DRCN_SR 0x00000001 /* transition SDRAM into self-refresh mode */
135 # put SDRAM in self-refresh mode
143 # Execute dummy load from SDRAM
146 # put the SDRAM into self-refresh mode
152 # wait for SDRAM to reach self-refresh mode
183 # wake SDRAM from self-refresh mode
194 # wait for the SDRAM to stabilise
H A Dhead.S106 # we need to relocate the SDRAM to 0x00000000 (linux) or 0xC0000000 (uClinux)
108 # fiddling with the SDRAM controller registers
131 sethi.p %hi(0xfe000000),gr17 ; unused SDRAM DBR value
138 # consult the SDRAM controller CS address registers
151 # assume the lowest valid CS line to be the SDRAM base and get its address
160 cor gr23,gr0,gr24, cc7,#1 ; GR24 = SDRAM base
165 # calculate the displacement required to get the SDRAM into the right place in memory
231 # move the kernel image down to the bottom of the SDRAM
423 # save the SDRAM details
564 # GR25 SDRAM siz
[all...]
H A Dhead-uc-fr451.S42 # GR25 SDRAM size [saved]
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-at91/
H A Dpm.h6 * terminate self-refresh automatically on the next SDRAM access.
45 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
82 #warning Assuming EB1 SDRAM controller is *NOT* used
H A Dpm_slowclock.S31 #warning Assuming EB1 SDRAM controller is *NOT* used
113 * R2 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
126 /* Put SDRAM in self-refresh mode */
149 /* Enable SDRAM self-refresh mode */
274 /* Restore LPR on AT91 with SDRAM */
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-lpc32xx/
H A Dsuspend.S53 @ Wait for SDRAM busy status to go busy and then idle
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-pxa/
H A Dsleep.S187 @ prepare SDRAM refresh settings
191 @ enable SDRAM self-refresh mode
238 @ prepare SDRAM refresh settings
242 @ enable SDRAM self-refresh mode
249 @ We keep the change-down close to the actual suspend on SDRAM
302 @ external accesses after SDRAM is put in self-refresh mode
308 @ put SDRAM into self-refresh
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-omap1/
H A Dsleep.S76 @ prepare to put SDRAM into self-refresh manually
160 @ prepare to put SDRAM into self-refresh manually
229 @ Prepare to put SDRAM into self-refresh manually
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/video/aty/
H A Dmach64_ct.c351 else if (par->ram_type >= SDRAM)
468 case SDRAM:
542 if (M64_HAS(SDRAM_MAGIC_PLL) && (par->ram_type >= SDRAM))
H A Datyfb_base.c542 static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
544 static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
2388 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2389 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
3039 if ((aty_ld_le32(CNFG_STAT0, par) & 7) >= SDRAM)
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-omap2/
H A Dsram34xx.S83 * before use by the code in SRAM (SDRAM is not accessible during SDRC
100 * SDRAM when the registers are written. If the registers are changed while
101 * an initiator is accessing SDRAM, memory can be corrupted and/or the SDRC
104 * touching the SDRAM. Until that time, users who know that their use case
139 bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
148 beq return_to_sdram @ return to SDRAM code, otherwise,
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/h8300/platform/h8s/edosk2674/
H A Dcrt0_rom.S43 ;SDRAM setup
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/cris/arch-v32/mach-fs/
H A Ddram_init.S2 * DRAM/SDRAM initialization - alter with care
25 ; Refer to BIF MDS for a description of SDRAM initialization
/netgear-R7000-V1.0.7.12_1.2.5/src/shared/
H A Dsbsdram.S2 * BCM47XX Sonics SiliconBackplane SDRAM/MEMC core initialization
221 /* Get SDRAM parameters (t0, t1, t2) from NVRAM (a2) */
223 lw t0,8(a2) # SDRAM init
226 andi t1,t2,0xffff # SDRAM config
227 srl t2,16 # SDRAM refresh
228 lw t3,16(a2) # SDRAM ncdl
252 /* Initialize DDR SDRAM */
886 /* Wait for SDRAM controller to refresh.
918 /* Initialize for SDR SDRAM */
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/staging/xgifb/
H A Dvb_def.h418 #define SDRAM 000h macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/include/video/
H A Dmach64.h885 #define SDRAM 4 macro

Completed in 161 milliseconds