1 2/* 3 * ATI Mach64 CT/VT/GT/LT Support 4 */ 5 6#include <linux/fb.h> 7#include <linux/delay.h> 8#include <asm/io.h> 9#include <video/mach64.h> 10#include "atyfb.h" 11#ifdef CONFIG_PPC 12#include <asm/machdep.h> 13#endif 14 15#undef DEBUG 16 17static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll); 18static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll); 19static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll); 20static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll); 21 22u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par) 23{ 24 u8 res; 25 26 /* write addr byte */ 27 aty_st_8(CLOCK_CNTL_ADDR, (offset << 2) & PLL_ADDR, par); 28 /* read the register value */ 29 res = aty_ld_8(CLOCK_CNTL_DATA, par); 30 return res; 31} 32 33static void aty_st_pll_ct(int offset, u8 val, const struct atyfb_par *par) 34{ 35 /* write addr byte */ 36 aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) | PLL_WR_EN, par); 37 /* write the register value */ 38 aty_st_8(CLOCK_CNTL_DATA, val & PLL_DATA, par); 39 aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) & ~PLL_WR_EN, par); 40} 41 42/* 43 * by Daniel Mantione 44 * <daniel.mantione@freepascal.org> 45 * 46 * 47 * ATI Mach64 CT clock synthesis description. 48 * 49 * All clocks on the Mach64 can be calculated using the same principle: 50 * 51 * XTALIN * x * FB_DIV 52 * CLK = ---------------------- 53 * PLL_REF_DIV * POST_DIV 54 * 55 * XTALIN is a fixed speed clock. Common speeds are 14.31 MHz and 29.50 MHz. 56 * PLL_REF_DIV can be set by the user, but is the same for all clocks. 57 * FB_DIV can be set by the user for each clock individually, it should be set 58 * between 128 and 255, the chip will generate a bad clock signal for too low 59 * values. 60 * x depends on the type of clock; usually it is 2, but for the MCLK it can also 61 * be set to 4. 62 * POST_DIV can be set by the user for each clock individually, Possible values 63 * are 1,2,4,8 and for some clocks other values are available too. 64 * CLK is of course the clock speed that is generated. 65 * 66 * The Mach64 has these clocks: 67 * 68 * MCLK The clock rate of the chip 69 * XCLK The clock rate of the on-chip memory 70 * VCLK0 First pixel clock of first CRT controller 71 * VCLK1 Second pixel clock of first CRT controller 72 * VCLK2 Third pixel clock of first CRT controller 73 * VCLK3 Fourth pixel clock of first CRT controller 74 * VCLK Selected pixel clock, one of VCLK0, VCLK1, VCLK2, VCLK3 75 * V2CLK Pixel clock of the second CRT controller. 76 * SCLK Multi-purpose clock 77 * 78 * - MCLK and XCLK use the same FB_DIV 79 * - VCLK0 .. VCLK3 use the same FB_DIV 80 * - V2CLK is needed when the second CRTC is used (can be used for dualhead); 81 * i.e. CRT monitor connected to laptop has different resolution than built 82 * in LCD monitor. 83 * - SCLK is not available on all cards; it is know to exist on the Rage LT-PRO, 84 * Rage XL and Rage Mobility. It is know not to exist on the Mach64 VT. 85 * - V2CLK is not available on all cards, most likely only the Rage LT-PRO, 86 * the Rage XL and the Rage Mobility 87 * 88 * SCLK can be used to: 89 * - Clock the chip instead of MCLK 90 * - Replace XTALIN with a user defined frequency 91 * - Generate the pixel clock for the LCD monitor (instead of VCLK) 92 */ 93 94 /* 95 * It can be quite hard to calculate XCLK and MCLK if they don't run at the 96 * same frequency. Luckily, until now all cards that need asynchrone clock 97 * speeds seem to have SCLK. 98 * So this driver uses SCLK to clock the chip and XCLK to clock the memory. 99 */ 100 101/* ------------------------------------------------------------------------- */ 102 103/* 104 * PLL programming (Mach64 CT family) 105 * 106 * 107 * This procedure sets the display fifo. The display fifo is a buffer that 108 * contains data read from the video memory that waits to be processed by 109 * the CRT controller. 110 * 111 * On the more modern Mach64 variants, the chip doesn't calculate the 112 * interval after which the display fifo has to be reloaded from memory 113 * automatically, the driver has to do it instead. 114 */ 115 116#define Maximum_DSP_PRECISION 7 117static u8 postdividers[] = {1,2,4,8,3}; 118 119static int aty_dsp_gt(const struct fb_info *info, u32 bpp, struct pll_ct *pll) 120{ 121 u32 dsp_off, dsp_on, dsp_xclks; 122 u32 multiplier, divider, ras_multiplier, ras_divider, tmp; 123 u8 vshift, xshift; 124 s8 dsp_precision; 125 126 multiplier = ((u32)pll->mclk_fb_div) * pll->vclk_post_div_real; 127 divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div; 128 129 ras_multiplier = pll->xclkmaxrasdelay; 130 ras_divider = 1; 131 132 if (bpp>=8) 133 divider = divider * (bpp >> 2); 134 135 vshift = (6 - 2) - pll->xclk_post_div; /* FIFO is 64 bits wide in accelerator mode ... */ 136 137 if (bpp == 0) 138 vshift--; /* ... but only 32 bits in VGA mode. */ 139 140#ifdef CONFIG_FB_ATY_GENERIC_LCD 141 if (pll->xres != 0) { 142 struct atyfb_par *par = (struct atyfb_par *) info->par; 143 144 multiplier = multiplier * par->lcd_width; 145 divider = divider * pll->xres & ~7; 146 147 ras_multiplier = ras_multiplier * par->lcd_width; 148 ras_divider = ras_divider * pll->xres & ~7; 149 } 150#endif 151 /* If we don't do this, 32 bits for multiplier & divider won't be 152 enough in certain situations! */ 153 while (((multiplier | divider) & 1) == 0) { 154 multiplier = multiplier >> 1; 155 divider = divider >> 1; 156 } 157 158 /* Determine DSP precision first */ 159 tmp = ((multiplier * pll->fifo_size) << vshift) / divider; 160 161 for (dsp_precision = -5; tmp; dsp_precision++) 162 tmp >>= 1; 163 if (dsp_precision < 0) 164 dsp_precision = 0; 165 else if (dsp_precision > Maximum_DSP_PRECISION) 166 dsp_precision = Maximum_DSP_PRECISION; 167 168 xshift = 6 - dsp_precision; 169 vshift += xshift; 170 171 /* Move on to dsp_off */ 172 dsp_off = ((multiplier * (pll->fifo_size - 1)) << vshift) / divider - 173 (1 << (vshift - xshift)); 174 175/* if (bpp == 0) 176 dsp_on = ((multiplier * 20 << vshift) + divider) / divider; 177 else */ 178 { 179 dsp_on = ((multiplier << vshift) + divider) / divider; 180 tmp = ((ras_multiplier << xshift) + ras_divider) / ras_divider; 181 if (dsp_on < tmp) 182 dsp_on = tmp; 183 dsp_on = dsp_on + (tmp * 2) + (pll->xclkpagefaultdelay << xshift); 184 } 185 186 /* Calculate rounding factor and apply it to dsp_on */ 187 tmp = ((1 << (Maximum_DSP_PRECISION - dsp_precision)) - 1) >> 1; 188 dsp_on = ((dsp_on + tmp) / (tmp + 1)) * (tmp + 1); 189 190 if (dsp_on >= ((dsp_off / (tmp + 1)) * (tmp + 1))) { 191 dsp_on = dsp_off - (multiplier << vshift) / divider; 192 dsp_on = (dsp_on / (tmp + 1)) * (tmp + 1); 193 } 194 195 /* Last but not least: dsp_xclks */ 196 dsp_xclks = ((multiplier << (vshift + 5)) + divider) / divider; 197 198 /* Get register values. */ 199 pll->dsp_on_off = (dsp_on << 16) + dsp_off; 200 pll->dsp_config = (dsp_precision << 20) | (pll->dsp_loop_latency << 16) | dsp_xclks; 201#ifdef DEBUG 202 printk("atyfb(%s): dsp_config 0x%08x, dsp_on_off 0x%08x\n", 203 __func__, pll->dsp_config, pll->dsp_on_off); 204#endif 205 return 0; 206} 207 208static int aty_valid_pll_ct(const struct fb_info *info, u32 vclk_per, struct pll_ct *pll) 209{ 210 u32 q; 211 struct atyfb_par *par = (struct atyfb_par *) info->par; 212 int pllvclk; 213 214 q = par->ref_clk_per * pll->pll_ref_div * 4 / vclk_per; 215 if (q < 16*8 || q > 255*8) { 216 printk(KERN_CRIT "atyfb: vclk out of range\n"); 217 return -EINVAL; 218 } else { 219 pll->vclk_post_div = (q < 128*8); 220 pll->vclk_post_div += (q < 64*8); 221 pll->vclk_post_div += (q < 32*8); 222 } 223 pll->vclk_post_div_real = postdividers[pll->vclk_post_div]; 224 // pll->vclk_post_div <<= 6; 225 pll->vclk_fb_div = q * pll->vclk_post_div_real / 8; 226 pllvclk = (1000000 * 2 * pll->vclk_fb_div) / 227 (par->ref_clk_per * pll->pll_ref_div); 228#ifdef DEBUG 229 printk("atyfb(%s): pllvclk=%d MHz, vclk=%d MHz\n", 230 __func__, pllvclk, pllvclk / pll->vclk_post_div_real); 231#endif 232 pll->pll_vclk_cntl = 0x03; /* VCLK = PLL_VCLK/VCLKx_POST */ 233 234 /* Set ECP (scaler/overlay clock) divider */ 235 if (par->pll_limits.ecp_max) { 236 int ecp = pllvclk / pll->vclk_post_div_real; 237 int ecp_div = 0; 238 239 while (ecp > par->pll_limits.ecp_max && ecp_div < 2) { 240 ecp >>= 1; 241 ecp_div++; 242 } 243 pll->pll_vclk_cntl |= ecp_div << 4; 244 } 245 246 return 0; 247} 248 249static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll) 250{ 251 struct atyfb_par *par = (struct atyfb_par *) info->par; 252 int err; 253 254 if ((err = aty_valid_pll_ct(info, vclk_per, &pll->ct))) 255 return err; 256 if (M64_HAS(GTB_DSP) && (err = aty_dsp_gt(info, bpp, &pll->ct))) 257 return err; 258 /*aty_calc_pll_ct(info, &pll->ct);*/ 259 return 0; 260} 261 262static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll) 263{ 264 struct atyfb_par *par = (struct atyfb_par *) info->par; 265 u32 ret; 266 ret = par->ref_clk_per * pll->ct.pll_ref_div * pll->ct.vclk_post_div_real / pll->ct.vclk_fb_div / 2; 267#ifdef CONFIG_FB_ATY_GENERIC_LCD 268 if(pll->ct.xres > 0) { 269 ret *= par->lcd_width; 270 ret /= pll->ct.xres; 271 } 272#endif 273#ifdef DEBUG 274 printk("atyfb(%s): calculated 0x%08X(%i)\n", __func__, ret, ret); 275#endif 276 return ret; 277} 278 279void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll) 280{ 281 struct atyfb_par *par = (struct atyfb_par *) info->par; 282 u32 crtc_gen_cntl, lcd_gen_cntrl; 283 u8 tmp, tmp2; 284 285 lcd_gen_cntrl = 0; 286#ifdef DEBUG 287 printk("atyfb(%s): about to program:\n" 288 "pll_ext_cntl=0x%02x pll_gen_cntl=0x%02x pll_vclk_cntl=0x%02x\n", 289 __func__, 290 pll->ct.pll_ext_cntl, pll->ct.pll_gen_cntl, pll->ct.pll_vclk_cntl); 291 292 printk("atyfb(%s): setting clock %lu for FeedBackDivider %i, ReferenceDivider %i, PostDivider %i(%i)\n", 293 __func__, 294 par->clk_wr_offset, pll->ct.vclk_fb_div, 295 pll->ct.pll_ref_div, pll->ct.vclk_post_div, pll->ct.vclk_post_div_real); 296#endif 297#ifdef CONFIG_FB_ATY_GENERIC_LCD 298 if (par->lcd_table != 0) { 299 /* turn off LCD */ 300 lcd_gen_cntrl = aty_ld_lcd(LCD_GEN_CNTL, par); 301 aty_st_lcd(LCD_GEN_CNTL, lcd_gen_cntrl & ~LCD_ON, par); 302 } 303#endif 304 aty_st_8(CLOCK_CNTL, par->clk_wr_offset | CLOCK_STROBE, par); 305 306 /* Temporarily switch to accelerator mode */ 307 crtc_gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par); 308 if (!(crtc_gen_cntl & CRTC_EXT_DISP_EN)) 309 aty_st_le32(CRTC_GEN_CNTL, crtc_gen_cntl | CRTC_EXT_DISP_EN, par); 310 311 /* Reset VCLK generator */ 312 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par); 313 314 /* Set post-divider */ 315 tmp2 = par->clk_wr_offset << 1; 316 tmp = aty_ld_pll_ct(VCLK_POST_DIV, par); 317 tmp &= ~(0x03U << tmp2); 318 tmp |= ((pll->ct.vclk_post_div & 0x03U) << tmp2); 319 aty_st_pll_ct(VCLK_POST_DIV, tmp, par); 320 321 /* Set extended post-divider */ 322 tmp = aty_ld_pll_ct(PLL_EXT_CNTL, par); 323 tmp &= ~(0x10U << par->clk_wr_offset); 324 tmp &= 0xF0U; 325 tmp |= pll->ct.pll_ext_cntl; 326 aty_st_pll_ct(PLL_EXT_CNTL, tmp, par); 327 328 /* Set feedback divider */ 329 tmp = VCLK0_FB_DIV + par->clk_wr_offset; 330 aty_st_pll_ct(tmp, (pll->ct.vclk_fb_div & 0xFFU), par); 331 332 aty_st_pll_ct(PLL_GEN_CNTL, (pll->ct.pll_gen_cntl & (~(PLL_OVERRIDE | PLL_MCLK_RST))) | OSC_EN, par); 333 334 /* End VCLK generator reset */ 335 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl & ~(PLL_VCLK_RST), par); 336 mdelay(5); 337 338 aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par); 339 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par); 340 mdelay(1); 341 342 /* Restore mode register */ 343 if (!(crtc_gen_cntl & CRTC_EXT_DISP_EN)) 344 aty_st_le32(CRTC_GEN_CNTL, crtc_gen_cntl, par); 345 346 if (M64_HAS(GTB_DSP)) { 347 u8 dll_cntl; 348 349 if (M64_HAS(XL_DLL)) 350 dll_cntl = 0x80; 351 else if (par->ram_type >= SDRAM) 352 dll_cntl = 0xa6; 353 else 354 dll_cntl = 0xa0; 355 aty_st_pll_ct(DLL_CNTL, dll_cntl, par); 356 aty_st_pll_ct(VFC_CNTL, 0x1b, par); 357 aty_st_le32(DSP_CONFIG, pll->ct.dsp_config, par); 358 aty_st_le32(DSP_ON_OFF, pll->ct.dsp_on_off, par); 359 360 mdelay(10); 361 aty_st_pll_ct(DLL_CNTL, dll_cntl, par); 362 mdelay(10); 363 aty_st_pll_ct(DLL_CNTL, dll_cntl | 0x40, par); 364 mdelay(10); 365 aty_st_pll_ct(DLL_CNTL, dll_cntl & ~0x40, par); 366 } 367#ifdef CONFIG_FB_ATY_GENERIC_LCD 368 if (par->lcd_table != 0) { 369 /* restore LCD */ 370 aty_st_lcd(LCD_GEN_CNTL, lcd_gen_cntrl, par); 371 } 372#endif 373} 374 375static void __devinit aty_get_pll_ct(const struct fb_info *info, 376 union aty_pll *pll) 377{ 378 struct atyfb_par *par = (struct atyfb_par *) info->par; 379 u8 tmp, clock; 380 381 clock = aty_ld_8(CLOCK_CNTL, par) & 0x03U; 382 tmp = clock << 1; 383 pll->ct.vclk_post_div = (aty_ld_pll_ct(VCLK_POST_DIV, par) >> tmp) & 0x03U; 384 385 pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par) & 0x0FU; 386 pll->ct.vclk_fb_div = aty_ld_pll_ct(VCLK0_FB_DIV + clock, par) & 0xFFU; 387 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); 388 pll->ct.mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par); 389 390 pll->ct.pll_gen_cntl = aty_ld_pll_ct(PLL_GEN_CNTL, par); 391 pll->ct.pll_vclk_cntl = aty_ld_pll_ct(PLL_VCLK_CNTL, par); 392 393 if (M64_HAS(GTB_DSP)) { 394 pll->ct.dsp_config = aty_ld_le32(DSP_CONFIG, par); 395 pll->ct.dsp_on_off = aty_ld_le32(DSP_ON_OFF, par); 396 } 397} 398 399static int __devinit aty_init_pll_ct(const struct fb_info *info, 400 union aty_pll *pll) 401{ 402 struct atyfb_par *par = (struct atyfb_par *) info->par; 403 u8 mpost_div, xpost_div, sclk_post_div_real; 404 u32 q, memcntl, trp; 405 u32 dsp_config, dsp_on_off, vga_dsp_config, vga_dsp_on_off; 406#ifdef DEBUG 407 int pllmclk, pllsclk; 408#endif 409 pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par); 410 pll->ct.xclk_post_div = pll->ct.pll_ext_cntl & 0x07; 411 pll->ct.xclk_ref_div = 1; 412 switch (pll->ct.xclk_post_div) { 413 case 0: case 1: case 2: case 3: 414 break; 415 416 case 4: 417 pll->ct.xclk_ref_div = 3; 418 pll->ct.xclk_post_div = 0; 419 break; 420 421 default: 422 printk(KERN_CRIT "atyfb: Unsupported xclk source: %d.\n", pll->ct.xclk_post_div); 423 return -EINVAL; 424 } 425 pll->ct.mclk_fb_mult = 2; 426 if(pll->ct.pll_ext_cntl & PLL_MFB_TIMES_4_2B) { 427 pll->ct.mclk_fb_mult = 4; 428 pll->ct.xclk_post_div -= 1; 429 } 430 431#ifdef DEBUG 432 printk("atyfb(%s): mclk_fb_mult=%d, xclk_post_div=%d\n", 433 __func__, pll->ct.mclk_fb_mult, pll->ct.xclk_post_div); 434#endif 435 436 memcntl = aty_ld_le32(MEM_CNTL, par); 437 trp = (memcntl & 0x300) >> 8; 438 439 pll->ct.xclkpagefaultdelay = ((memcntl & 0xc00) >> 10) + ((memcntl & 0x1000) >> 12) + trp + 2; 440 pll->ct.xclkmaxrasdelay = ((memcntl & 0x70000) >> 16) + trp + 2; 441 442 if (M64_HAS(FIFO_32)) { 443 pll->ct.fifo_size = 32; 444 } else { 445 pll->ct.fifo_size = 24; 446 pll->ct.xclkpagefaultdelay += 2; 447 pll->ct.xclkmaxrasdelay += 3; 448 } 449 450 switch (par->ram_type) { 451 case DRAM: 452 if (info->fix.smem_len<=ONE_MB) { 453 pll->ct.dsp_loop_latency = 10; 454 } else { 455 pll->ct.dsp_loop_latency = 8; 456 pll->ct.xclkpagefaultdelay += 2; 457 } 458 break; 459 case EDO: 460 case PSEUDO_EDO: 461 if (info->fix.smem_len<=ONE_MB) { 462 pll->ct.dsp_loop_latency = 9; 463 } else { 464 pll->ct.dsp_loop_latency = 8; 465 pll->ct.xclkpagefaultdelay += 1; 466 } 467 break; 468 case SDRAM: 469 if (info->fix.smem_len<=ONE_MB) { 470 pll->ct.dsp_loop_latency = 11; 471 } else { 472 pll->ct.dsp_loop_latency = 10; 473 pll->ct.xclkpagefaultdelay += 1; 474 } 475 break; 476 case SGRAM: 477 pll->ct.dsp_loop_latency = 8; 478 pll->ct.xclkpagefaultdelay += 3; 479 break; 480 default: 481 pll->ct.dsp_loop_latency = 11; 482 pll->ct.xclkpagefaultdelay += 3; 483 break; 484 } 485 486 if (pll->ct.xclkmaxrasdelay <= pll->ct.xclkpagefaultdelay) 487 pll->ct.xclkmaxrasdelay = pll->ct.xclkpagefaultdelay + 1; 488 489 /* Allow BIOS to override */ 490 dsp_config = aty_ld_le32(DSP_CONFIG, par); 491 dsp_on_off = aty_ld_le32(DSP_ON_OFF, par); 492 vga_dsp_config = aty_ld_le32(VGA_DSP_CONFIG, par); 493 vga_dsp_on_off = aty_ld_le32(VGA_DSP_ON_OFF, par); 494 495 if (dsp_config) 496 pll->ct.dsp_loop_latency = (dsp_config & DSP_LOOP_LATENCY) >> 16; 497 /* Exit if the user does not want us to tamper with the clock 498 rates of her chip. */ 499 if (par->mclk_per == 0) { 500 u8 mclk_fb_div, pll_ext_cntl; 501 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); 502 pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par); 503 pll->ct.xclk_post_div_real = postdividers[pll_ext_cntl & 0x07]; 504 mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par); 505 if (pll_ext_cntl & PLL_MFB_TIMES_4_2B) 506 mclk_fb_div <<= 1; 507 pll->ct.mclk_fb_div = mclk_fb_div; 508 return 0; 509 } 510 511 pll->ct.pll_ref_div = par->pll_per * 2 * 255 / par->ref_clk_per; 512 513 q = par->ref_clk_per * pll->ct.pll_ref_div * 8 / 514 (pll->ct.mclk_fb_mult * par->xclk_per); 515 516 if (q < 16*8 || q > 255*8) { 517 printk(KERN_CRIT "atxfb: xclk out of range\n"); 518 return -EINVAL; 519 } else { 520 xpost_div = (q < 128*8); 521 xpost_div += (q < 64*8); 522 xpost_div += (q < 32*8); 523 } 524 pll->ct.xclk_post_div_real = postdividers[xpost_div]; 525 pll->ct.mclk_fb_div = q * pll->ct.xclk_post_div_real / 8; 526 527#ifdef CONFIG_PPC 528 if (machine_is(powermac)) { 529 /* Override PLL_EXT_CNTL & 0x07. */ 530 pll->ct.xclk_post_div = xpost_div; 531 pll->ct.xclk_ref_div = 1; 532 } 533#endif 534 535#ifdef DEBUG 536 pllmclk = (1000000 * pll->ct.mclk_fb_mult * pll->ct.mclk_fb_div) / 537 (par->ref_clk_per * pll->ct.pll_ref_div); 538 printk("atyfb(%s): pllmclk=%d MHz, xclk=%d MHz\n", 539 __func__, pllmclk, pllmclk / pll->ct.xclk_post_div_real); 540#endif 541 542 if (M64_HAS(SDRAM_MAGIC_PLL) && (par->ram_type >= SDRAM)) 543 pll->ct.pll_gen_cntl = OSC_EN; 544 else 545 pll->ct.pll_gen_cntl = OSC_EN | DLL_PWDN /* | FORCE_DCLK_TRI_STATE */; 546 547 if (M64_HAS(MAGIC_POSTDIV)) 548 pll->ct.pll_ext_cntl = 0; 549 else 550 pll->ct.pll_ext_cntl = xpost_div; 551 552 if (pll->ct.mclk_fb_mult == 4) 553 pll->ct.pll_ext_cntl |= PLL_MFB_TIMES_4_2B; 554 555 if (par->mclk_per == par->xclk_per) { 556 pll->ct.pll_gen_cntl |= (xpost_div << 4); /* mclk == xclk */ 557 } else { 558 /* 559 * The chip clock is not equal to the memory clock. 560 * Therefore we will use sclk to clock the chip. 561 */ 562 pll->ct.pll_gen_cntl |= (6 << 4); /* mclk == sclk */ 563 564 q = par->ref_clk_per * pll->ct.pll_ref_div * 4 / par->mclk_per; 565 if (q < 16*8 || q > 255*8) { 566 printk(KERN_CRIT "atyfb: mclk out of range\n"); 567 return -EINVAL; 568 } else { 569 mpost_div = (q < 128*8); 570 mpost_div += (q < 64*8); 571 mpost_div += (q < 32*8); 572 } 573 sclk_post_div_real = postdividers[mpost_div]; 574 pll->ct.sclk_fb_div = q * sclk_post_div_real / 8; 575 pll->ct.spll_cntl2 = mpost_div << 4; 576#ifdef DEBUG 577 pllsclk = (1000000 * 2 * pll->ct.sclk_fb_div) / 578 (par->ref_clk_per * pll->ct.pll_ref_div); 579 printk("atyfb(%s): use sclk, pllsclk=%d MHz, sclk=mclk=%d MHz\n", 580 __func__, pllsclk, pllsclk / sclk_post_div_real); 581#endif 582 } 583 584 /* Disable the extra precision pixel clock controls since we do not use them. */ 585 pll->ct.ext_vpll_cntl = aty_ld_pll_ct(EXT_VPLL_CNTL, par); 586 pll->ct.ext_vpll_cntl &= ~(EXT_VPLL_EN | EXT_VPLL_VGA_EN | EXT_VPLL_INSYNC); 587 588 return 0; 589} 590 591static void aty_resume_pll_ct(const struct fb_info *info, 592 union aty_pll *pll) 593{ 594 struct atyfb_par *par = info->par; 595 596 if (par->mclk_per != par->xclk_per) { 597 /* 598 * This disables the sclk, crashes the computer as reported: 599 * aty_st_pll_ct(SPLL_CNTL2, 3, info); 600 * 601 * So it seems the sclk must be enabled before it is used; 602 * so PLL_GEN_CNTL must be programmed *after* the sclk. 603 */ 604 aty_st_pll_ct(SCLK_FB_DIV, pll->ct.sclk_fb_div, par); 605 aty_st_pll_ct(SPLL_CNTL2, pll->ct.spll_cntl2, par); 606 /* 607 * SCLK has been started. Wait for the PLL to lock. 5 ms 608 * should be enough according to mach64 programmer's guide. 609 */ 610 mdelay(5); 611 } 612 613 aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par); 614 aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par); 615 aty_st_pll_ct(MCLK_FB_DIV, pll->ct.mclk_fb_div, par); 616 aty_st_pll_ct(PLL_EXT_CNTL, pll->ct.pll_ext_cntl, par); 617 aty_st_pll_ct(EXT_VPLL_CNTL, pll->ct.ext_vpll_cntl, par); 618} 619 620static int dummy(void) 621{ 622 return 0; 623} 624 625const struct aty_dac_ops aty_dac_ct = { 626 .set_dac = (void *) dummy, 627}; 628 629const struct aty_pll_ops aty_pll_ct = { 630 .var_to_pll = aty_var_to_pll_ct, 631 .pll_to_var = aty_pll_to_var_ct, 632 .set_pll = aty_set_pll_ct, 633 .get_pll = aty_get_pll_ct, 634 .init_pll = aty_init_pll_ct, 635 .resume_pll = aty_resume_pll_ct, 636}; 637