1/* cmode.S: clock mode management 2 * 3 * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved. 4 * Written by David Woodhouse (dwmw2@infradead.org) 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 * 11 */ 12 13#include <linux/sys.h> 14#include <linux/linkage.h> 15#include <asm/setup.h> 16#include <asm/segment.h> 17#include <asm/ptrace.h> 18#include <asm/errno.h> 19#include <asm/cache.h> 20#include <asm/spr-regs.h> 21 22#define __addr_MASK 0xfeff9820 /* interrupt controller mask */ 23 24#define __addr_SDRAMC 0xfe000400 /* SDRAM controller regs */ 25#define SDRAMC_DSTS 0x28 /* SDRAM status */ 26#define SDRAMC_DSTS_SSI 0x00000001 /* indicates that the SDRAM is in self-refresh mode */ 27#define SDRAMC_DRCN 0x30 /* SDRAM refresh control */ 28#define SDRAMC_DRCN_SR 0x00000001 /* transition SDRAM into self-refresh mode */ 29#define __addr_CLKC 0xfeff9a00 30#define CLKC_SWCMODE 0x00000008 31#define __addr_LEDS 0xe1200004 32 33.macro li v r 34 sethi.p %hi(\v),\r 35 setlo %lo(\v),\r 36.endm 37 38 .text 39 .balign 4 40 41 42############################################################################### 43# 44# Change CMODE 45# - void frv_change_cmode(int cmode) 46# 47############################################################################### 48 .globl frv_change_cmode 49 .type frv_change_cmode,@function 50 51.macro LEDS v 52#ifdef DEBUG_CMODE 53 setlos #~\v,gr10 54 sti gr10,@(gr11,#0) 55 membar 56#endif 57.endm 58 59frv_change_cmode: 60 movsg lr,gr9 61#ifdef DEBUG_CMODE 62 li __addr_LEDS,gr11 63#endif 64 dcef @(gr0,gr0),#1 65 66 # Shift argument left by 24 bits to fit in SWCMODE register later. 67 slli gr8,#24,gr8 68 69 # (1) Set '0' in the PSR.ET bit, and prohibit interrupts. 70 movsg psr,gr14 71 andi gr14,#~PSR_ET,gr3 72 movgs gr3,psr 73 74 75 # (3) Stop the transfer function of DMAC. Stop all the bus masters 76 # to access SDRAM and the internal resources. 77 78 # (already done by caller) 79 80 # (4) Preload a series of following instructions to the instruction 81 # cache. 82 li #__cmode_icache_lock_start,gr3 83 li #__cmode_icache_lock_end,gr4 84 851: icpl gr3,gr0,#1 86 addi gr3,#L1_CACHE_BYTES,gr3 87 cmp gr4,gr3,icc0 88 bhi icc0,#0,1b 89 90 # Set up addresses in regs for later steps. 91 setlos SDRAMC_DRCN_SR,gr3 92 li __addr_SDRAMC,gr4 93 li __addr_CLKC,gr5 94 ldi @(gr5,#0),gr6 95 li #0x80000000,gr7 96 or gr6,gr7,gr6 97 98 bra __cmode_icache_lock_start 99 100 .balign L1_CACHE_BYTES 101__cmode_icache_lock_start: 102 103 # (5) Flush the content of all caches by the DCEF instruction. 104 dcef @(gr0,gr0),#1 105 106 # (6) Execute loading the dummy for SDRAM. 107 ldi @(gr9,#0),gr0 108 109 # (7) Set '1' to the DRCN.SR bit, and change SDRAM to the 110 # self-refresh mode. Execute the dummy load to all memory 111 # devices set to cacheable on the external bus side in parallel 112 # with this. 113 sti gr3,@(gr4,#SDRAMC_DRCN) 114 115 # (8) Execute memory barrier instruction (MEMBAR). 116 membar 117 118 # (9) Read the DSTS register repeatedly until '1' stands in the 119 # DSTS.SSI field. 1201: ldi @(gr4,#SDRAMC_DSTS),gr3 121 andicc gr3,#SDRAMC_DSTS_SSI,gr3,icc0 122 beq icc0,#0,1b 123 124 # (10) Execute memory barrier instruction (MEMBAR). 125 membar 126 127 # (11) Set the value of CMODE that you want to change to 128 # SWCMODE.SWCM[3:0]. 129 sti gr8,@(gr5,#CLKC_SWCMODE) 130 131 # (12) Set '1' to the CLKC.SWEN bit. In that case, do not change 132 # fields other than SWEN of the CLKC register. 133 sti gr6,@(gr5,#0) 134 # (13) Execute the instruction just after the memory barrier 135 # instruction that executes the self-loop 256 times. (Meanwhile, 136 # the CMODE switch is done.) 137 membar 138 setlos #256,gr7 1392: subicc gr7,#1,gr7,icc0 140 bne icc0,#2,2b 141 142 LEDS 0x36 143 144 # (14) Release the self-refresh of SDRAM. 145 sti gr0,@(gr4,#SDRAMC_DRCN) 146 147 # Wait for it... 1483: ldi @(gr4,#SDRAMC_DSTS),gr3 149 andicc gr3,#SDRAMC_DSTS_SSI,gr3,icc0 150 bne icc0,#2,3b 151 152 153__cmode_icache_lock_end: 154 155 li #__cmode_icache_lock_start,gr3 156 li #__cmode_icache_lock_end,gr4 157 1584: icul gr3 159 addi gr3,#L1_CACHE_BYTES,gr3 160 cmp gr4,gr3,icc0 161 bhi icc0,#0,4b 162 163 # (16) Set 1' in the PSR.ET bit, and permit interrupt. 164 movgs gr14,psr 165 166 bralr 167 168 .size frv_change_cmode, .-frv_change_cmode 169