Searched refs:DMA_CSR (Results 1 - 5 of 5) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/scsi/
H A Dsun3x_esp.c22 #define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */ macro
77 if (dma_read32(DMA_CSR) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))
86 val = dma_read32(DMA_CSR);
87 dma_write32(val | DMA_RST_SCSI, DMA_CSR);
88 dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
91 val = dma_read32(DMA_CSR);
92 dma_write32(val | DMA_INT_ENAB, DMA_CSR);
100 csr = dma_read32(DMA_CSR);
104 dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR);
107 while (dma_read32(DMA_CSR)
[all...]
H A Dsun_esp.c57 switch (dma_read32(DMA_CSR) & DMA_DEVICE_ID) {
250 if (dma_read32(DMA_CSR) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))
274 val = dma_read32(DMA_CSR);
275 dma_write32(val | DMA_RST_SCSI, DMA_CSR);
276 dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
280 dma_write32(DMA_RESET_FAS366, DMA_CSR);
281 dma_write32(DMA_RST_SCSI, DMA_CSR);
300 while (dma_read32(DMA_CSR) & DMA_PEND_READ) {
310 dma_write32(0, DMA_CSR);
311 dma_write32(esp->prev_hme_dmacsr, DMA_CSR);
[all...]
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/include/asm/hardware/
H A Diop3xx-adma.h27 #define DMA_CSR(chan) (chan->mmr_base + 0x4) macro
298 u32 status = __raw_readl(DMA_CSR(chan));
852 return __raw_readl(DMA_CSR(chan));
872 u32 status = __raw_readl(DMA_CSR(chan));
874 __raw_writel(status, DMA_CSR(chan));
879 u32 status = __raw_readl(DMA_CSR(chan));
881 __raw_writel(status, DMA_CSR(chan));
886 u32 status = __raw_readl(DMA_CSR(chan));
900 __raw_writel(status, DMA_CSR(chan));
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/net/
H A Dsunlance.c442 u32 csr = sbus_readl(lp->dregs + DMA_CSR);
446 while (sbus_readl(lp->dregs + DMA_CSR) & DMA_FIFO_ISDRAIN)
450 csr = sbus_readl(lp->dregs + DMA_CSR);
464 sbus_writel(csr, lp->dregs + DMA_CSR);
491 printk("dcsr=%8.8x\n", sbus_readl(lp->dregs + DMA_CSR));
500 u32 csr = sbus_readl(lp->dregs + DMA_CSR);
503 sbus_writel(csr, lp->dregs + DMA_CSR);
866 u32 dma_csr = sbus_readl(lp->dregs + DMA_CSR);
869 sbus_writel(dma_csr, lp->dregs + DMA_CSR);
996 csr = sbus_readl(lp->dregs + DMA_CSR);
[all...]
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/sparc/include/asm/
H A Ddma.h17 #define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */ macro

Completed in 128 milliseconds