Lines Matching refs:DMA_CSR
22 #define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */
77 if (dma_read32(DMA_CSR) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))
86 val = dma_read32(DMA_CSR);
87 dma_write32(val | DMA_RST_SCSI, DMA_CSR);
88 dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
91 val = dma_read32(DMA_CSR);
92 dma_write32(val | DMA_INT_ENAB, DMA_CSR);
100 csr = dma_read32(DMA_CSR);
104 dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR);
107 while (dma_read32(DMA_CSR) & DMA_FIFO_ISDRAIN) {
123 while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) {
134 dma_write32(val, DMA_CSR);
136 dma_write32(val, DMA_CSR);
148 csr = dma_read32(DMA_CSR);
154 dma_write32(csr, DMA_CSR);
162 u32 csr = dma_read32(DMA_CSR);
268 val = dma_read32(DMA_CSR);
269 dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);