Lines Matching refs:DMA_CSR
57 switch (dma_read32(DMA_CSR) & DMA_DEVICE_ID) {
250 if (dma_read32(DMA_CSR) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))
274 val = dma_read32(DMA_CSR);
275 dma_write32(val | DMA_RST_SCSI, DMA_CSR);
276 dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
280 dma_write32(DMA_RESET_FAS366, DMA_CSR);
281 dma_write32(DMA_RST_SCSI, DMA_CSR);
300 while (dma_read32(DMA_CSR) & DMA_PEND_READ) {
310 dma_write32(0, DMA_CSR);
311 dma_write32(esp->prev_hme_dmacsr, DMA_CSR);
318 val = dma_read32(DMA_CSR);
319 dma_write32(val | DMA_3CLKS, DMA_CSR);
324 val = dma_read32(DMA_CSR);
331 dma_write32(val, DMA_CSR);
335 val = dma_read32(DMA_CSR);
343 dma_write32(val, DMA_CSR);
351 val = dma_read32(DMA_CSR);
352 dma_write32(val | DMA_INT_ENAB, DMA_CSR);
363 csr = dma_read32(DMA_CSR);
368 dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR);
371 while (dma_read32(DMA_CSR) & DMA_FIFO_ISDRAIN) {
384 dma_write32(DMA_RST_SCSI, DMA_CSR);
391 dma_write32(0, DMA_CSR);
392 dma_write32(esp->prev_hme_dmacsr, DMA_CSR);
403 while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) {
414 dma_write32(val, DMA_CSR);
416 dma_write32(val, DMA_CSR);
445 dma_write32(csr, DMA_CSR);
447 csr = dma_read32(DMA_CSR);
453 dma_write32(csr, DMA_CSR);
467 u32 csr = dma_read32(DMA_CSR);
538 u32 val = dma_read32(DMA_CSR);
540 dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
599 val = dma_read32(DMA_CSR);
600 dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);