Searched refs:CSR7 (Results 1 - 9 of 9) sorted by relevance
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/net/tulip/ |
H A D | pnic.c | 64 iowrite32((ioread32(ioaddr + CSR7) & ~TPLnkFail) | TPLnkPass, ioaddr + CSR7); 85 iowrite32((ioread32(ioaddr + CSR7) & ~TPLnkPass) | TPLnkFail, ioaddr + CSR7); 96 if(!ioread32(ioaddr + CSR7)) { 164 if(!ioread32(ioaddr + CSR7)) { 170 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
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H A D | interrupt.c | 317 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, tp->base_addr+CSR7); 545 iowrite32(tulip_tbl[tp->chip_id].valid_intrs&~RxPollInt, ioaddr + CSR7); 713 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7); 730 iowrite32(0x00, ioaddr + CSR7); 735 iowrite32(((~csr5) & 0x0001ebef) | AbnormalIntr | TimerInt, ioaddr + CSR7); 773 iowrite32(0x00, ioaddr + CSR7); 782 ioaddr + CSR7);
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H A D | xircom_cb.c | 64 #define CSR7 0x38 macro 105 CSR0, CSR6, CSR7, CSR9, CSR10, CSR15 928 val = inl(card->io_port + CSR7); /* Interrupt enable register */ 930 outl(val, card->io_port + CSR7); 946 val = inl(card->io_port + CSR7); /* Interrupt enable register */ 948 outl(val, card->io_port + CSR7); 963 val = inl(card->io_port + CSR7); /* Interrupt enable register */ 965 outl(val, card->io_port + CSR7); 983 outl(val, card->io_port + CSR7); 998 val = inl(card->io_port + CSR7); /* Interrup [all...] |
H A D | tulip.h | 47 int valid_intrs; /* CSR7 interrupt enable settings */ 116 CSR7 = 0x38, enumerator in enum:tulip_offsets
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H A D | tulip_core.c | 450 iowrite32(ioread32(ioaddr+CSR7)| 0x00008010, ioaddr + CSR7); local 496 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7); 570 (int)ioread32(ioaddr + CSR7), 772 iowrite32 (0x00000000, ioaddr + CSR7);
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/net/wireless/rt2x00/ |
H A D | rt2400pci.c | 891 rt2x00pci_register_read(rt2x00dev, CSR7, ®); 892 rt2x00pci_register_write(rt2x00dev, CSR7, reg); 1297 rt2x00pci_register_read(rt2x00dev, CSR7, ®); 1298 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
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H A D | rt2400pci.h | 119 * CSR7: Interrupt source register. 129 #define CSR7 0x001c macro
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H A D | rt2500pci.c | 1045 rt2x00pci_register_read(rt2x00dev, CSR7, ®); 1046 rt2x00pci_register_write(rt2x00dev, CSR7, reg); 1430 rt2x00pci_register_read(rt2x00dev, CSR7, ®); 1431 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
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H A D | rt2500pci.h | 130 * CSR7: Interrupt source register. 154 #define CSR7 0x001c macro
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