1/* tulip_core.c: A DEC 21x4x-family ethernet driver for Linux. 2 3 Copyright 2000,2001 The Linux Kernel Team 4 Written/copyright 1994-2001 by Donald Becker. 5 6 This software may be used and distributed according to the terms 7 of the GNU General Public License, incorporated herein by reference. 8 9 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html} 10 for more information on this driver. 11 12 Please submit bugs to http://bugzilla.kernel.org/ . 13*/ 14 15 16#define DRV_NAME "tulip" 17#ifdef CONFIG_TULIP_NAPI 18#define DRV_VERSION "1.1.15-NAPI" /* Keep at least for test */ 19#else 20#define DRV_VERSION "1.1.15" 21#endif 22#define DRV_RELDATE "Feb 27, 2007" 23 24 25#include <linux/module.h> 26#include <linux/pci.h> 27#include <linux/slab.h> 28#include "tulip.h" 29#include <linux/init.h> 30#include <linux/etherdevice.h> 31#include <linux/delay.h> 32#include <linux/mii.h> 33#include <linux/crc32.h> 34#include <asm/unaligned.h> 35#include <asm/uaccess.h> 36 37#ifdef CONFIG_SPARC 38#include <asm/prom.h> 39#endif 40 41static char version[] __devinitdata = 42 "Linux Tulip driver version " DRV_VERSION " (" DRV_RELDATE ")\n"; 43 44/* A few user-configurable values. */ 45 46/* Maximum events (Rx packets, etc.) to handle at each interrupt. */ 47static unsigned int max_interrupt_work = 25; 48 49#define MAX_UNITS 8 50/* Used to pass the full-duplex flag, etc. */ 51static int full_duplex[MAX_UNITS]; 52static int options[MAX_UNITS]; 53static int mtu[MAX_UNITS]; /* Jumbo MTU for interfaces. */ 54 55/* The possible media types that can be set in options[] are: */ 56const char * const medianame[32] = { 57 "10baseT", "10base2", "AUI", "100baseTx", 58 "10baseT-FDX", "100baseTx-FDX", "100baseT4", "100baseFx", 59 "100baseFx-FDX", "MII 10baseT", "MII 10baseT-FDX", "MII", 60 "10baseT(forced)", "MII 100baseTx", "MII 100baseTx-FDX", "MII 100baseT4", 61 "MII 100baseFx-HDX", "MII 100baseFx-FDX", "Home-PNA 1Mbps", "Invalid-19", 62 "","","","", "","","","", "","","","Transceiver reset", 63}; 64 65/* Set the copy breakpoint for the copy-only-tiny-buffer Rx structure. */ 66#if defined(__alpha__) || defined(__arm__) || defined(__hppa__) || \ 67 defined(CONFIG_SPARC) || defined(__ia64__) || defined(__sh__) || defined(__mips__) 68static int rx_copybreak = 1518; 69#else 70static int rx_copybreak = 100; 71#endif 72 73/* 74 Set the bus performance register. 75 Typical: Set 16 longword cache alignment, no burst limit. 76 Cache alignment bits 15:14 Burst length 13:8 77 0000 No alignment 0x00000000 unlimited 0800 8 longwords 78 4000 8 longwords 0100 1 longword 1000 16 longwords 79 8000 16 longwords 0200 2 longwords 2000 32 longwords 80 C000 32 longwords 0400 4 longwords 81 Warning: many older 486 systems are broken and require setting 0x00A04800 82 8 longword cache alignment, 8 longword burst. 83 ToDo: Non-Intel setting could be better. 84*/ 85 86#if defined(__alpha__) || defined(__ia64__) 87static int csr0 = 0x01A00000 | 0xE000; 88#elif defined(__i386__) || defined(__powerpc__) || defined(__x86_64__) 89static int csr0 = 0x01A00000 | 0x8000; 90#elif defined(CONFIG_SPARC) || defined(__hppa__) 91/* The UltraSparc PCI controllers will disconnect at every 64-byte 92 * crossing anyways so it makes no sense to tell Tulip to burst 93 * any more than that. 94 */ 95static int csr0 = 0x01A00000 | 0x9000; 96#elif defined(__arm__) || defined(__sh__) 97static int csr0 = 0x01A00000 | 0x4800; 98#elif defined(__mips__) 99static int csr0 = 0x00200000 | 0x4000; 100#else 101#warning Processor architecture undefined! 102static int csr0 = 0x00A00000 | 0x4800; 103#endif 104 105/* Operational parameters that usually are not changed. */ 106/* Time in jiffies before concluding the transmitter is hung. */ 107#define TX_TIMEOUT (4*HZ) 108 109 110MODULE_AUTHOR("The Linux Kernel Team"); 111MODULE_DESCRIPTION("Digital 21*4* Tulip ethernet driver"); 112MODULE_LICENSE("GPL"); 113MODULE_VERSION(DRV_VERSION); 114module_param(tulip_debug, int, 0); 115module_param(max_interrupt_work, int, 0); 116module_param(rx_copybreak, int, 0); 117module_param(csr0, int, 0); 118module_param_array(options, int, NULL, 0); 119module_param_array(full_duplex, int, NULL, 0); 120 121#define PFX DRV_NAME ": " 122 123#ifdef TULIP_DEBUG 124int tulip_debug = TULIP_DEBUG; 125#else 126int tulip_debug = 1; 127#endif 128 129static void tulip_timer(unsigned long data) 130{ 131 struct net_device *dev = (struct net_device *)data; 132 struct tulip_private *tp = netdev_priv(dev); 133 134 if (netif_running(dev)) 135 schedule_work(&tp->media_work); 136} 137 138/* 139 * This table use during operation for capabilities and media timer. 140 * 141 * It is indexed via the values in 'enum chips' 142 */ 143 144struct tulip_chip_table tulip_tbl[] = { 145 { }, /* placeholder for array, slot unused currently */ 146 { }, /* placeholder for array, slot unused currently */ 147 148 /* DC21140 */ 149 { "Digital DS21140 Tulip", 128, 0x0001ebef, 150 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_PCI_MWI, tulip_timer, 151 tulip_media_task }, 152 153 /* DC21142, DC21143 */ 154 { "Digital DS21142/43 Tulip", 128, 0x0801fbff, 155 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI | HAS_NWAY 156 | HAS_INTR_MITIGATION | HAS_PCI_MWI, tulip_timer, t21142_media_task }, 157 158 /* LC82C168 */ 159 { "Lite-On 82c168 PNIC", 256, 0x0001fbef, 160 HAS_MII | HAS_PNICNWAY, pnic_timer, }, 161 162 /* MX98713 */ 163 { "Macronix 98713 PMAC", 128, 0x0001ebef, 164 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, }, 165 166 /* MX98715 */ 167 { "Macronix 98715 PMAC", 256, 0x0001ebef, 168 HAS_MEDIA_TABLE, mxic_timer, }, 169 170 /* MX98725 */ 171 { "Macronix 98725 PMAC", 256, 0x0001ebef, 172 HAS_MEDIA_TABLE, mxic_timer, }, 173 174 /* AX88140 */ 175 { "ASIX AX88140", 128, 0x0001fbff, 176 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | MC_HASH_ONLY 177 | IS_ASIX, tulip_timer, tulip_media_task }, 178 179 /* PNIC2 */ 180 { "Lite-On PNIC-II", 256, 0x0801fbff, 181 HAS_MII | HAS_NWAY | HAS_8023X | HAS_PCI_MWI, pnic2_timer, }, 182 183 /* COMET */ 184 { "ADMtek Comet", 256, 0x0001abef, 185 HAS_MII | MC_HASH_ONLY | COMET_MAC_ADDR, comet_timer, }, 186 187 /* COMPEX9881 */ 188 { "Compex 9881 PMAC", 128, 0x0001ebef, 189 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, }, 190 191 /* I21145 */ 192 { "Intel DS21145 Tulip", 128, 0x0801fbff, 193 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI 194 | HAS_NWAY | HAS_PCI_MWI, tulip_timer, tulip_media_task }, 195 196 /* DM910X */ 197#ifdef CONFIG_TULIP_DM910X 198 { "Davicom DM9102/DM9102A", 128, 0x0001ebef, 199 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_ACPI, 200 tulip_timer, tulip_media_task }, 201#else 202 { NULL }, 203#endif 204 205 /* RS7112 */ 206 { "Conexant LANfinity", 256, 0x0001ebef, 207 HAS_MII | HAS_ACPI, tulip_timer, tulip_media_task }, 208 209}; 210 211 212static DEFINE_PCI_DEVICE_TABLE(tulip_pci_tbl) = { 213 { 0x1011, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21140 }, 214 { 0x1011, 0x0019, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21143 }, 215 { 0x11AD, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, LC82C168 }, 216 { 0x10d9, 0x0512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98713 }, 217 { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 }, 218/* { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98725 },*/ 219 { 0x125B, 0x1400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AX88140 }, 220 { 0x11AD, 0xc115, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PNIC2 }, 221 { 0x1317, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, 222 { 0x1317, 0x0985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, 223 { 0x1317, 0x1985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, 224 { 0x1317, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, 225 { 0x13D1, 0xAB02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, 226 { 0x13D1, 0xAB03, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, 227 { 0x13D1, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, 228 { 0x104A, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, 229 { 0x104A, 0x2774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, 230 { 0x1259, 0xa120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, 231 { 0x11F6, 0x9881, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMPEX9881 }, 232 { 0x8086, 0x0039, PCI_ANY_ID, PCI_ANY_ID, 0, 0, I21145 }, 233#ifdef CONFIG_TULIP_DM910X 234 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X }, 235 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X }, 236#endif 237 { 0x1113, 0x1216, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, 238 { 0x1113, 0x1217, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 }, 239 { 0x1113, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, 240 { 0x1186, 0x1541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, 241 { 0x1186, 0x1561, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, 242 { 0x1186, 0x1591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, 243 { 0x14f1, 0x1803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CONEXANT }, 244 { 0x1626, 0x8410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, 245 { 0x1737, 0xAB09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, 246 { 0x1737, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, 247 { 0x17B3, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, 248 { 0x10b7, 0x9300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* 3Com 3CSOHO100B-TX */ 249 { 0x14ea, 0xab08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Planex FNW-3602-TX */ 250 { 0x1414, 0x0001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Microsoft MN-120 */ 251 { 0x1414, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, 252 { } /* terminate list */ 253}; 254MODULE_DEVICE_TABLE(pci, tulip_pci_tbl); 255 256 257/* A full-duplex map for media types. */ 258const char tulip_media_cap[32] = 259{0,0,0,16, 3,19,16,24, 27,4,7,5, 0,20,23,20, 28,31,0,0, }; 260 261static void tulip_tx_timeout(struct net_device *dev); 262static void tulip_init_ring(struct net_device *dev); 263static void tulip_free_ring(struct net_device *dev); 264static netdev_tx_t tulip_start_xmit(struct sk_buff *skb, 265 struct net_device *dev); 266static int tulip_open(struct net_device *dev); 267static int tulip_close(struct net_device *dev); 268static void tulip_up(struct net_device *dev); 269static void tulip_down(struct net_device *dev); 270static struct net_device_stats *tulip_get_stats(struct net_device *dev); 271static int private_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 272static void set_rx_mode(struct net_device *dev); 273static void tulip_set_wolopts(struct pci_dev *pdev, u32 wolopts); 274#ifdef CONFIG_NET_POLL_CONTROLLER 275static void poll_tulip(struct net_device *dev); 276#endif 277 278static void tulip_set_power_state (struct tulip_private *tp, 279 int sleep, int snooze) 280{ 281 if (tp->flags & HAS_ACPI) { 282 u32 tmp, newtmp; 283 pci_read_config_dword (tp->pdev, CFDD, &tmp); 284 newtmp = tmp & ~(CFDD_Sleep | CFDD_Snooze); 285 if (sleep) 286 newtmp |= CFDD_Sleep; 287 else if (snooze) 288 newtmp |= CFDD_Snooze; 289 if (tmp != newtmp) 290 pci_write_config_dword (tp->pdev, CFDD, newtmp); 291 } 292 293} 294 295 296static void tulip_up(struct net_device *dev) 297{ 298 struct tulip_private *tp = netdev_priv(dev); 299 void __iomem *ioaddr = tp->base_addr; 300 int next_tick = 3*HZ; 301 u32 reg; 302 int i; 303 304#ifdef CONFIG_TULIP_NAPI 305 napi_enable(&tp->napi); 306#endif 307 308 /* Wake the chip from sleep/snooze mode. */ 309 tulip_set_power_state (tp, 0, 0); 310 311 /* Disable all WOL events */ 312 pci_enable_wake(tp->pdev, PCI_D3hot, 0); 313 pci_enable_wake(tp->pdev, PCI_D3cold, 0); 314 tulip_set_wolopts(tp->pdev, 0); 315 316 /* On some chip revs we must set the MII/SYM port before the reset!? */ 317 if (tp->mii_cnt || (tp->mtable && tp->mtable->has_mii)) 318 iowrite32(0x00040000, ioaddr + CSR6); 319 320 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */ 321 iowrite32(0x00000001, ioaddr + CSR0); 322 pci_read_config_dword(tp->pdev, PCI_COMMAND, ®); /* flush write */ 323 udelay(100); 324 325 /* Deassert reset. 326 Wait the specified 50 PCI cycles after a reset by initializing 327 Tx and Rx queues and the address filter list. */ 328 iowrite32(tp->csr0, ioaddr + CSR0); 329 pci_read_config_dword(tp->pdev, PCI_COMMAND, ®); /* flush write */ 330 udelay(100); 331 332 if (tulip_debug > 1) 333 printk(KERN_DEBUG "%s: tulip_up(), irq==%d\n", 334 dev->name, dev->irq); 335 336 iowrite32(tp->rx_ring_dma, ioaddr + CSR3); 337 iowrite32(tp->tx_ring_dma, ioaddr + CSR4); 338 tp->cur_rx = tp->cur_tx = 0; 339 tp->dirty_rx = tp->dirty_tx = 0; 340 341 if (tp->flags & MC_HASH_ONLY) { 342 u32 addr_low = get_unaligned_le32(dev->dev_addr); 343 u32 addr_high = get_unaligned_le16(dev->dev_addr + 4); 344 if (tp->chip_id == AX88140) { 345 iowrite32(0, ioaddr + CSR13); 346 iowrite32(addr_low, ioaddr + CSR14); 347 iowrite32(1, ioaddr + CSR13); 348 iowrite32(addr_high, ioaddr + CSR14); 349 } else if (tp->flags & COMET_MAC_ADDR) { 350 iowrite32(addr_low, ioaddr + 0xA4); 351 iowrite32(addr_high, ioaddr + 0xA8); 352 iowrite32(0, ioaddr + CSR27); 353 iowrite32(0, ioaddr + CSR28); 354 } 355 } else { 356 /* This is set_rx_mode(), but without starting the transmitter. */ 357 u16 *eaddrs = (u16 *)dev->dev_addr; 358 u16 *setup_frm = &tp->setup_frame[15*6]; 359 dma_addr_t mapping; 360 361 /* 21140 bug: you must add the broadcast address. */ 362 memset(tp->setup_frame, 0xff, sizeof(tp->setup_frame)); 363 /* Fill the final entry of the table with our physical address. */ 364 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0]; 365 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1]; 366 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2]; 367 368 mapping = pci_map_single(tp->pdev, tp->setup_frame, 369 sizeof(tp->setup_frame), 370 PCI_DMA_TODEVICE); 371 tp->tx_buffers[tp->cur_tx].skb = NULL; 372 tp->tx_buffers[tp->cur_tx].mapping = mapping; 373 374 /* Put the setup frame on the Tx list. */ 375 tp->tx_ring[tp->cur_tx].length = cpu_to_le32(0x08000000 | 192); 376 tp->tx_ring[tp->cur_tx].buffer1 = cpu_to_le32(mapping); 377 tp->tx_ring[tp->cur_tx].status = cpu_to_le32(DescOwned); 378 379 tp->cur_tx++; 380 } 381 382 tp->saved_if_port = dev->if_port; 383 if (dev->if_port == 0) 384 dev->if_port = tp->default_port; 385 386 /* Allow selecting a default media. */ 387 i = 0; 388 if (tp->mtable == NULL) 389 goto media_picked; 390 if (dev->if_port) { 391 int looking_for = tulip_media_cap[dev->if_port] & MediaIsMII ? 11 : 392 (dev->if_port == 12 ? 0 : dev->if_port); 393 for (i = 0; i < tp->mtable->leafcount; i++) 394 if (tp->mtable->mleaf[i].media == looking_for) { 395 dev_info(&dev->dev, 396 "Using user-specified media %s\n", 397 medianame[dev->if_port]); 398 goto media_picked; 399 } 400 } 401 if ((tp->mtable->defaultmedia & 0x0800) == 0) { 402 int looking_for = tp->mtable->defaultmedia & MEDIA_MASK; 403 for (i = 0; i < tp->mtable->leafcount; i++) 404 if (tp->mtable->mleaf[i].media == looking_for) { 405 dev_info(&dev->dev, 406 "Using EEPROM-set media %s\n", 407 medianame[looking_for]); 408 goto media_picked; 409 } 410 } 411 /* Start sensing first non-full-duplex media. */ 412 for (i = tp->mtable->leafcount - 1; 413 (tulip_media_cap[tp->mtable->mleaf[i].media] & MediaAlwaysFD) && i > 0; i--) 414 ; 415media_picked: 416 417 tp->csr6 = 0; 418 tp->cur_index = i; 419 tp->nwayset = 0; 420 421 if (dev->if_port) { 422 if (tp->chip_id == DC21143 && 423 (tulip_media_cap[dev->if_port] & MediaIsMII)) { 424 /* We must reset the media CSRs when we force-select MII mode. */ 425 iowrite32(0x0000, ioaddr + CSR13); 426 iowrite32(0x0000, ioaddr + CSR14); 427 iowrite32(0x0008, ioaddr + CSR15); 428 } 429 tulip_select_media(dev, 1); 430 } else if (tp->chip_id == DC21142) { 431 if (tp->mii_cnt) { 432 tulip_select_media(dev, 1); 433 if (tulip_debug > 1) 434 dev_info(&dev->dev, 435 "Using MII transceiver %d, status %04x\n", 436 tp->phys[0], 437 tulip_mdio_read(dev, tp->phys[0], 1)); 438 iowrite32(csr6_mask_defstate, ioaddr + CSR6); 439 tp->csr6 = csr6_mask_hdcap; 440 dev->if_port = 11; 441 iowrite32(0x0000, ioaddr + CSR13); 442 iowrite32(0x0000, ioaddr + CSR14); 443 } else 444 t21142_start_nway(dev); 445 } else if (tp->chip_id == PNIC2) { 446 /* for initial startup advertise 10/100 Full and Half */ 447 tp->sym_advertise = 0x01E0; 448 /* enable autonegotiate end interrupt */ 449 iowrite32(ioread32(ioaddr+CSR5)| 0x00008010, ioaddr + CSR5); 450 iowrite32(ioread32(ioaddr+CSR7)| 0x00008010, ioaddr + CSR7); 451 pnic2_start_nway(dev); 452 } else if (tp->chip_id == LC82C168 && ! tp->medialock) { 453 if (tp->mii_cnt) { 454 dev->if_port = 11; 455 tp->csr6 = 0x814C0000 | (tp->full_duplex ? 0x0200 : 0); 456 iowrite32(0x0001, ioaddr + CSR15); 457 } else if (ioread32(ioaddr + CSR5) & TPLnkPass) 458 pnic_do_nway(dev); 459 else { 460 /* Start with 10mbps to do autonegotiation. */ 461 iowrite32(0x32, ioaddr + CSR12); 462 tp->csr6 = 0x00420000; 463 iowrite32(0x0001B078, ioaddr + 0xB8); 464 iowrite32(0x0201B078, ioaddr + 0xB8); 465 next_tick = 1*HZ; 466 } 467 } else if ((tp->chip_id == MX98713 || tp->chip_id == COMPEX9881) && 468 ! tp->medialock) { 469 dev->if_port = 0; 470 tp->csr6 = 0x01880000 | (tp->full_duplex ? 0x0200 : 0); 471 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80); 472 } else if (tp->chip_id == MX98715 || tp->chip_id == MX98725) { 473 /* Provided by BOLO, Macronix - 12/10/1998. */ 474 dev->if_port = 0; 475 tp->csr6 = 0x01a80200; 476 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80); 477 iowrite32(0x11000 | ioread16(ioaddr + 0xa0), ioaddr + 0xa0); 478 } else if (tp->chip_id == COMET || tp->chip_id == CONEXANT) { 479 /* Enable automatic Tx underrun recovery. */ 480 iowrite32(ioread32(ioaddr + 0x88) | 1, ioaddr + 0x88); 481 dev->if_port = tp->mii_cnt ? 11 : 0; 482 tp->csr6 = 0x00040000; 483 } else if (tp->chip_id == AX88140) { 484 tp->csr6 = tp->mii_cnt ? 0x00040100 : 0x00000100; 485 } else 486 tulip_select_media(dev, 1); 487 488 /* Start the chip's Tx to process setup frame. */ 489 tulip_stop_rxtx(tp); 490 barrier(); 491 udelay(5); 492 iowrite32(tp->csr6 | TxOn, ioaddr + CSR6); 493 494 /* Enable interrupts by setting the interrupt mask. */ 495 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5); 496 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7); 497 tulip_start_rxtx(tp); 498 iowrite32(0, ioaddr + CSR2); /* Rx poll demand */ 499 500 if (tulip_debug > 2) { 501 printk(KERN_DEBUG "%s: Done tulip_up(), CSR0 %08x, CSR5 %08x CSR6 %08x\n", 502 dev->name, ioread32(ioaddr + CSR0), 503 ioread32(ioaddr + CSR5), 504 ioread32(ioaddr + CSR6)); 505 } 506 507 /* Set the timer to switch to check for link beat and perhaps switch 508 to an alternate media type. */ 509 tp->timer.expires = RUN_AT(next_tick); 510 add_timer(&tp->timer); 511#ifdef CONFIG_TULIP_NAPI 512 init_timer(&tp->oom_timer); 513 tp->oom_timer.data = (unsigned long)dev; 514 tp->oom_timer.function = oom_timer; 515#endif 516} 517 518static int 519tulip_open(struct net_device *dev) 520{ 521 int retval; 522 523 tulip_init_ring (dev); 524 525 retval = request_irq(dev->irq, tulip_interrupt, IRQF_SHARED, dev->name, dev); 526 if (retval) 527 goto free_ring; 528 529 tulip_up (dev); 530 531 netif_start_queue (dev); 532 533 return 0; 534 535free_ring: 536 tulip_free_ring (dev); 537 return retval; 538} 539 540 541static void tulip_tx_timeout(struct net_device *dev) 542{ 543 struct tulip_private *tp = netdev_priv(dev); 544 void __iomem *ioaddr = tp->base_addr; 545 unsigned long flags; 546 547 spin_lock_irqsave (&tp->lock, flags); 548 549 if (tulip_media_cap[dev->if_port] & MediaIsMII) { 550 /* Do nothing -- the media monitor should handle this. */ 551 if (tulip_debug > 1) 552 dev_warn(&dev->dev, 553 "Transmit timeout using MII device\n"); 554 } else if (tp->chip_id == DC21140 || tp->chip_id == DC21142 || 555 tp->chip_id == MX98713 || tp->chip_id == COMPEX9881 || 556 tp->chip_id == DM910X) { 557 dev_warn(&dev->dev, 558 "21140 transmit timed out, status %08x, SIA %08x %08x %08x %08x, resetting...\n", 559 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12), 560 ioread32(ioaddr + CSR13), ioread32(ioaddr + CSR14), 561 ioread32(ioaddr + CSR15)); 562 tp->timeout_recovery = 1; 563 schedule_work(&tp->media_work); 564 goto out_unlock; 565 } else if (tp->chip_id == PNIC2) { 566 dev_warn(&dev->dev, 567 "PNIC2 transmit timed out, status %08x, CSR6/7 %08x / %08x CSR12 %08x, resetting...\n", 568 (int)ioread32(ioaddr + CSR5), 569 (int)ioread32(ioaddr + CSR6), 570 (int)ioread32(ioaddr + CSR7), 571 (int)ioread32(ioaddr + CSR12)); 572 } else { 573 dev_warn(&dev->dev, 574 "Transmit timed out, status %08x, CSR12 %08x, resetting...\n", 575 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12)); 576 dev->if_port = 0; 577 } 578 579#if defined(way_too_many_messages) 580 if (tulip_debug > 3) { 581 int i; 582 for (i = 0; i < RX_RING_SIZE; i++) { 583 u8 *buf = (u8 *)(tp->rx_ring[i].buffer1); 584 int j; 585 printk(KERN_DEBUG 586 "%2d: %08x %08x %08x %08x %02x %02x %02x\n", 587 i, 588 (unsigned int)tp->rx_ring[i].status, 589 (unsigned int)tp->rx_ring[i].length, 590 (unsigned int)tp->rx_ring[i].buffer1, 591 (unsigned int)tp->rx_ring[i].buffer2, 592 buf[0], buf[1], buf[2]); 593 for (j = 0; buf[j] != 0xee && j < 1600; j++) 594 if (j < 100) 595 pr_cont(" %02x", buf[j]); 596 pr_cont(" j=%d\n", j); 597 } 598 printk(KERN_DEBUG " Rx ring %p: ", tp->rx_ring); 599 for (i = 0; i < RX_RING_SIZE; i++) 600 pr_cont(" %08x", (unsigned int)tp->rx_ring[i].status); 601 printk(KERN_DEBUG " Tx ring %p: ", tp->tx_ring); 602 for (i = 0; i < TX_RING_SIZE; i++) 603 pr_cont(" %08x", (unsigned int)tp->tx_ring[i].status); 604 pr_cont("\n"); 605 } 606#endif 607 608 tulip_tx_timeout_complete(tp, ioaddr); 609 610out_unlock: 611 spin_unlock_irqrestore (&tp->lock, flags); 612 dev->trans_start = jiffies; /* prevent tx timeout */ 613 netif_wake_queue (dev); 614} 615 616 617/* Initialize the Rx and Tx rings, along with various 'dev' bits. */ 618static void tulip_init_ring(struct net_device *dev) 619{ 620 struct tulip_private *tp = netdev_priv(dev); 621 int i; 622 623 tp->susp_rx = 0; 624 tp->ttimer = 0; 625 tp->nir = 0; 626 627 for (i = 0; i < RX_RING_SIZE; i++) { 628 tp->rx_ring[i].status = 0x00000000; 629 tp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ); 630 tp->rx_ring[i].buffer2 = cpu_to_le32(tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * (i + 1)); 631 tp->rx_buffers[i].skb = NULL; 632 tp->rx_buffers[i].mapping = 0; 633 } 634 /* Mark the last entry as wrapping the ring. */ 635 tp->rx_ring[i-1].length = cpu_to_le32(PKT_BUF_SZ | DESC_RING_WRAP); 636 tp->rx_ring[i-1].buffer2 = cpu_to_le32(tp->rx_ring_dma); 637 638 for (i = 0; i < RX_RING_SIZE; i++) { 639 dma_addr_t mapping; 640 641 /* Note the receive buffer must be longword aligned. 642 dev_alloc_skb() provides 16 byte alignment. But do *not* 643 use skb_reserve() to align the IP header! */ 644 struct sk_buff *skb = dev_alloc_skb(PKT_BUF_SZ); 645 tp->rx_buffers[i].skb = skb; 646 if (skb == NULL) 647 break; 648 mapping = pci_map_single(tp->pdev, skb->data, 649 PKT_BUF_SZ, PCI_DMA_FROMDEVICE); 650 tp->rx_buffers[i].mapping = mapping; 651 skb->dev = dev; /* Mark as being used by this device. */ 652 tp->rx_ring[i].status = cpu_to_le32(DescOwned); /* Owned by Tulip chip */ 653 tp->rx_ring[i].buffer1 = cpu_to_le32(mapping); 654 } 655 tp->dirty_rx = (unsigned int)(i - RX_RING_SIZE); 656 657 /* The Tx buffer descriptor is filled in as needed, but we 658 do need to clear the ownership bit. */ 659 for (i = 0; i < TX_RING_SIZE; i++) { 660 tp->tx_buffers[i].skb = NULL; 661 tp->tx_buffers[i].mapping = 0; 662 tp->tx_ring[i].status = 0x00000000; 663 tp->tx_ring[i].buffer2 = cpu_to_le32(tp->tx_ring_dma + sizeof(struct tulip_tx_desc) * (i + 1)); 664 } 665 tp->tx_ring[i-1].buffer2 = cpu_to_le32(tp->tx_ring_dma); 666} 667 668static netdev_tx_t 669tulip_start_xmit(struct sk_buff *skb, struct net_device *dev) 670{ 671 struct tulip_private *tp = netdev_priv(dev); 672 int entry; 673 u32 flag; 674 dma_addr_t mapping; 675 unsigned long flags; 676 677 spin_lock_irqsave(&tp->lock, flags); 678 679 /* Calculate the next Tx descriptor entry. */ 680 entry = tp->cur_tx % TX_RING_SIZE; 681 682 tp->tx_buffers[entry].skb = skb; 683 mapping = pci_map_single(tp->pdev, skb->data, 684 skb->len, PCI_DMA_TODEVICE); 685 tp->tx_buffers[entry].mapping = mapping; 686 tp->tx_ring[entry].buffer1 = cpu_to_le32(mapping); 687 688 if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE/2) {/* Typical path */ 689 flag = 0x60000000; /* No interrupt */ 690 } else if (tp->cur_tx - tp->dirty_tx == TX_RING_SIZE/2) { 691 flag = 0xe0000000; /* Tx-done intr. */ 692 } else if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE - 2) { 693 flag = 0x60000000; /* No Tx-done intr. */ 694 } else { /* Leave room for set_rx_mode() to fill entries. */ 695 flag = 0xe0000000; /* Tx-done intr. */ 696 netif_stop_queue(dev); 697 } 698 if (entry == TX_RING_SIZE-1) 699 flag = 0xe0000000 | DESC_RING_WRAP; 700 701 tp->tx_ring[entry].length = cpu_to_le32(skb->len | flag); 702 /* if we were using Transmit Automatic Polling, we would need a 703 * wmb() here. */ 704 tp->tx_ring[entry].status = cpu_to_le32(DescOwned); 705 wmb(); 706 707 tp->cur_tx++; 708 709 /* Trigger an immediate transmit demand. */ 710 iowrite32(0, tp->base_addr + CSR1); 711 712 spin_unlock_irqrestore(&tp->lock, flags); 713 714 return NETDEV_TX_OK; 715} 716 717static void tulip_clean_tx_ring(struct tulip_private *tp) 718{ 719 unsigned int dirty_tx; 720 721 for (dirty_tx = tp->dirty_tx ; tp->cur_tx - dirty_tx > 0; 722 dirty_tx++) { 723 int entry = dirty_tx % TX_RING_SIZE; 724 int status = le32_to_cpu(tp->tx_ring[entry].status); 725 726 if (status < 0) { 727 tp->stats.tx_errors++; /* It wasn't Txed */ 728 tp->tx_ring[entry].status = 0; 729 } 730 731 /* Check for Tx filter setup frames. */ 732 if (tp->tx_buffers[entry].skb == NULL) { 733 /* test because dummy frames not mapped */ 734 if (tp->tx_buffers[entry].mapping) 735 pci_unmap_single(tp->pdev, 736 tp->tx_buffers[entry].mapping, 737 sizeof(tp->setup_frame), 738 PCI_DMA_TODEVICE); 739 continue; 740 } 741 742 pci_unmap_single(tp->pdev, tp->tx_buffers[entry].mapping, 743 tp->tx_buffers[entry].skb->len, 744 PCI_DMA_TODEVICE); 745 746 /* Free the original skb. */ 747 dev_kfree_skb_irq(tp->tx_buffers[entry].skb); 748 tp->tx_buffers[entry].skb = NULL; 749 tp->tx_buffers[entry].mapping = 0; 750 } 751} 752 753static void tulip_down (struct net_device *dev) 754{ 755 struct tulip_private *tp = netdev_priv(dev); 756 void __iomem *ioaddr = tp->base_addr; 757 unsigned long flags; 758 759 cancel_work_sync(&tp->media_work); 760 761#ifdef CONFIG_TULIP_NAPI 762 napi_disable(&tp->napi); 763#endif 764 765 del_timer_sync (&tp->timer); 766#ifdef CONFIG_TULIP_NAPI 767 del_timer_sync (&tp->oom_timer); 768#endif 769 spin_lock_irqsave (&tp->lock, flags); 770 771 /* Disable interrupts by clearing the interrupt mask. */ 772 iowrite32 (0x00000000, ioaddr + CSR7); 773 774 /* Stop the Tx and Rx processes. */ 775 tulip_stop_rxtx(tp); 776 777 /* prepare receive buffers */ 778 tulip_refill_rx(dev); 779 780 /* release any unconsumed transmit buffers */ 781 tulip_clean_tx_ring(tp); 782 783 if (ioread32 (ioaddr + CSR6) != 0xffffffff) 784 tp->stats.rx_missed_errors += ioread32 (ioaddr + CSR8) & 0xffff; 785 786 spin_unlock_irqrestore (&tp->lock, flags); 787 788 init_timer(&tp->timer); 789 tp->timer.data = (unsigned long)dev; 790 tp->timer.function = tulip_tbl[tp->chip_id].media_timer; 791 792 dev->if_port = tp->saved_if_port; 793 794 /* Leave the driver in snooze, not sleep, mode. */ 795 tulip_set_power_state (tp, 0, 1); 796} 797 798static void tulip_free_ring (struct net_device *dev) 799{ 800 struct tulip_private *tp = netdev_priv(dev); 801 int i; 802 803 /* Free all the skbuffs in the Rx queue. */ 804 for (i = 0; i < RX_RING_SIZE; i++) { 805 struct sk_buff *skb = tp->rx_buffers[i].skb; 806 dma_addr_t mapping = tp->rx_buffers[i].mapping; 807 808 tp->rx_buffers[i].skb = NULL; 809 tp->rx_buffers[i].mapping = 0; 810 811 tp->rx_ring[i].status = 0; /* Not owned by Tulip chip. */ 812 tp->rx_ring[i].length = 0; 813 /* An invalid address. */ 814 tp->rx_ring[i].buffer1 = cpu_to_le32(0xBADF00D0); 815 if (skb) { 816 pci_unmap_single(tp->pdev, mapping, PKT_BUF_SZ, 817 PCI_DMA_FROMDEVICE); 818 dev_kfree_skb (skb); 819 } 820 } 821 822 for (i = 0; i < TX_RING_SIZE; i++) { 823 struct sk_buff *skb = tp->tx_buffers[i].skb; 824 825 if (skb != NULL) { 826 pci_unmap_single(tp->pdev, tp->tx_buffers[i].mapping, 827 skb->len, PCI_DMA_TODEVICE); 828 dev_kfree_skb (skb); 829 } 830 tp->tx_buffers[i].skb = NULL; 831 tp->tx_buffers[i].mapping = 0; 832 } 833} 834 835static int tulip_close (struct net_device *dev) 836{ 837 struct tulip_private *tp = netdev_priv(dev); 838 void __iomem *ioaddr = tp->base_addr; 839 840 netif_stop_queue (dev); 841 842 tulip_down (dev); 843 844 if (tulip_debug > 1) 845 dev_printk(KERN_DEBUG, &dev->dev, 846 "Shutting down ethercard, status was %02x\n", 847 ioread32 (ioaddr + CSR5)); 848 849 free_irq (dev->irq, dev); 850 851 tulip_free_ring (dev); 852 853 return 0; 854} 855 856static struct net_device_stats *tulip_get_stats(struct net_device *dev) 857{ 858 struct tulip_private *tp = netdev_priv(dev); 859 void __iomem *ioaddr = tp->base_addr; 860 861 if (netif_running(dev)) { 862 unsigned long flags; 863 864 spin_lock_irqsave (&tp->lock, flags); 865 866 tp->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff; 867 868 spin_unlock_irqrestore(&tp->lock, flags); 869 } 870 871 return &tp->stats; 872} 873 874 875static void tulip_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 876{ 877 struct tulip_private *np = netdev_priv(dev); 878 strcpy(info->driver, DRV_NAME); 879 strcpy(info->version, DRV_VERSION); 880 strcpy(info->bus_info, pci_name(np->pdev)); 881} 882 883 884static int tulip_ethtool_set_wol(struct net_device *dev, 885 struct ethtool_wolinfo *wolinfo) 886{ 887 struct tulip_private *tp = netdev_priv(dev); 888 889 if (wolinfo->wolopts & (~tp->wolinfo.supported)) 890 return -EOPNOTSUPP; 891 892 tp->wolinfo.wolopts = wolinfo->wolopts; 893 device_set_wakeup_enable(&tp->pdev->dev, tp->wolinfo.wolopts); 894 return 0; 895} 896 897static void tulip_ethtool_get_wol(struct net_device *dev, 898 struct ethtool_wolinfo *wolinfo) 899{ 900 struct tulip_private *tp = netdev_priv(dev); 901 902 wolinfo->supported = tp->wolinfo.supported; 903 wolinfo->wolopts = tp->wolinfo.wolopts; 904 return; 905} 906 907 908static const struct ethtool_ops ops = { 909 .get_drvinfo = tulip_get_drvinfo, 910 .set_wol = tulip_ethtool_set_wol, 911 .get_wol = tulip_ethtool_get_wol, 912}; 913 914/* Provide ioctl() calls to examine the MII xcvr state. */ 915static int private_ioctl (struct net_device *dev, struct ifreq *rq, int cmd) 916{ 917 struct tulip_private *tp = netdev_priv(dev); 918 void __iomem *ioaddr = tp->base_addr; 919 struct mii_ioctl_data *data = if_mii(rq); 920 const unsigned int phy_idx = 0; 921 int phy = tp->phys[phy_idx] & 0x1f; 922 unsigned int regnum = data->reg_num; 923 924 switch (cmd) { 925 case SIOCGMIIPHY: /* Get address of MII PHY in use. */ 926 if (tp->mii_cnt) 927 data->phy_id = phy; 928 else if (tp->flags & HAS_NWAY) 929 data->phy_id = 32; 930 else if (tp->chip_id == COMET) 931 data->phy_id = 1; 932 else 933 return -ENODEV; 934 935 case SIOCGMIIREG: /* Read MII PHY register. */ 936 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) { 937 int csr12 = ioread32 (ioaddr + CSR12); 938 int csr14 = ioread32 (ioaddr + CSR14); 939 switch (regnum) { 940 case 0: 941 if (((csr14<<5) & 0x1000) || 942 (dev->if_port == 5 && tp->nwayset)) 943 data->val_out = 0x1000; 944 else 945 data->val_out = (tulip_media_cap[dev->if_port]&MediaIs100 ? 0x2000 : 0) 946 | (tulip_media_cap[dev->if_port]&MediaIsFD ? 0x0100 : 0); 947 break; 948 case 1: 949 data->val_out = 950 0x1848 + 951 ((csr12&0x7000) == 0x5000 ? 0x20 : 0) + 952 ((csr12&0x06) == 6 ? 0 : 4); 953 data->val_out |= 0x6048; 954 break; 955 case 4: 956 /* Advertised value, bogus 10baseTx-FD value from CSR6. */ 957 data->val_out = 958 ((ioread32(ioaddr + CSR6) >> 3) & 0x0040) + 959 ((csr14 >> 1) & 0x20) + 1; 960 data->val_out |= ((csr14 >> 9) & 0x03C0); 961 break; 962 case 5: data->val_out = tp->lpar; break; 963 default: data->val_out = 0; break; 964 } 965 } else { 966 data->val_out = tulip_mdio_read (dev, data->phy_id & 0x1f, regnum); 967 } 968 return 0; 969 970 case SIOCSMIIREG: /* Write MII PHY register. */ 971 if (regnum & ~0x1f) 972 return -EINVAL; 973 if (data->phy_id == phy) { 974 u16 value = data->val_in; 975 switch (regnum) { 976 case 0: /* Check for autonegotiation on or reset. */ 977 tp->full_duplex_lock = (value & 0x9000) ? 0 : 1; 978 if (tp->full_duplex_lock) 979 tp->full_duplex = (value & 0x0100) ? 1 : 0; 980 break; 981 case 4: 982 tp->advertising[phy_idx] = 983 tp->mii_advertise = data->val_in; 984 break; 985 } 986 } 987 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) { 988 u16 value = data->val_in; 989 if (regnum == 0) { 990 if ((value & 0x1200) == 0x1200) { 991 if (tp->chip_id == PNIC2) { 992 pnic2_start_nway (dev); 993 } else { 994 t21142_start_nway (dev); 995 } 996 } 997 } else if (regnum == 4) 998 tp->sym_advertise = value; 999 } else { 1000 tulip_mdio_write (dev, data->phy_id & 0x1f, regnum, data->val_in); 1001 } 1002 return 0; 1003 default: 1004 return -EOPNOTSUPP; 1005 } 1006 1007 return -EOPNOTSUPP; 1008} 1009 1010 1011/* Set or clear the multicast filter for this adaptor. 1012 Note that we only use exclusion around actually queueing the 1013 new frame, not around filling tp->setup_frame. This is non-deterministic 1014 when re-entered but still correct. */ 1015 1016#undef set_bit_le 1017#define set_bit_le(i,p) do { ((char *)(p))[(i)/8] |= (1<<((i)%8)); } while(0) 1018 1019static void build_setup_frame_hash(u16 *setup_frm, struct net_device *dev) 1020{ 1021 struct tulip_private *tp = netdev_priv(dev); 1022 u16 hash_table[32]; 1023 struct netdev_hw_addr *ha; 1024 int i; 1025 u16 *eaddrs; 1026 1027 memset(hash_table, 0, sizeof(hash_table)); 1028 set_bit_le(255, hash_table); /* Broadcast entry */ 1029 /* This should work on big-endian machines as well. */ 1030 netdev_for_each_mc_addr(ha, dev) { 1031 int index = ether_crc_le(ETH_ALEN, ha->addr) & 0x1ff; 1032 1033 set_bit_le(index, hash_table); 1034 } 1035 for (i = 0; i < 32; i++) { 1036 *setup_frm++ = hash_table[i]; 1037 *setup_frm++ = hash_table[i]; 1038 } 1039 setup_frm = &tp->setup_frame[13*6]; 1040 1041 /* Fill the final entry with our physical address. */ 1042 eaddrs = (u16 *)dev->dev_addr; 1043 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0]; 1044 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1]; 1045 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2]; 1046} 1047 1048static void build_setup_frame_perfect(u16 *setup_frm, struct net_device *dev) 1049{ 1050 struct tulip_private *tp = netdev_priv(dev); 1051 struct netdev_hw_addr *ha; 1052 u16 *eaddrs; 1053 1054 /* We have <= 14 addresses so we can use the wonderful 1055 16 address perfect filtering of the Tulip. */ 1056 netdev_for_each_mc_addr(ha, dev) { 1057 eaddrs = (u16 *) ha->addr; 1058 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++; 1059 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++; 1060 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++; 1061 } 1062 /* Fill the unused entries with the broadcast address. */ 1063 memset(setup_frm, 0xff, (15 - netdev_mc_count(dev)) * 12); 1064 setup_frm = &tp->setup_frame[15*6]; 1065 1066 /* Fill the final entry with our physical address. */ 1067 eaddrs = (u16 *)dev->dev_addr; 1068 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0]; 1069 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1]; 1070 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2]; 1071} 1072 1073 1074static void set_rx_mode(struct net_device *dev) 1075{ 1076 struct tulip_private *tp = netdev_priv(dev); 1077 void __iomem *ioaddr = tp->base_addr; 1078 int csr6; 1079 1080 csr6 = ioread32(ioaddr + CSR6) & ~0x00D5; 1081 1082 tp->csr6 &= ~0x00D5; 1083 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ 1084 tp->csr6 |= AcceptAllMulticast | AcceptAllPhys; 1085 csr6 |= AcceptAllMulticast | AcceptAllPhys; 1086 } else if ((netdev_mc_count(dev) > 1000) || 1087 (dev->flags & IFF_ALLMULTI)) { 1088 /* Too many to filter well -- accept all multicasts. */ 1089 tp->csr6 |= AcceptAllMulticast; 1090 csr6 |= AcceptAllMulticast; 1091 } else if (tp->flags & MC_HASH_ONLY) { 1092 /* Some work-alikes have only a 64-entry hash filter table. */ 1093 /* Should verify correctness on big-endian/__powerpc__ */ 1094 struct netdev_hw_addr *ha; 1095 if (netdev_mc_count(dev) > 64) { 1096 /* Arbitrary non-effective limit. */ 1097 tp->csr6 |= AcceptAllMulticast; 1098 csr6 |= AcceptAllMulticast; 1099 } else { 1100 u32 mc_filter[2] = {0, 0}; /* Multicast hash filter */ 1101 int filterbit; 1102 netdev_for_each_mc_addr(ha, dev) { 1103 if (tp->flags & COMET_MAC_ADDR) 1104 filterbit = ether_crc_le(ETH_ALEN, 1105 ha->addr); 1106 else 1107 filterbit = ether_crc(ETH_ALEN, 1108 ha->addr) >> 26; 1109 filterbit &= 0x3f; 1110 mc_filter[filterbit >> 5] |= 1 << (filterbit & 31); 1111 if (tulip_debug > 2) 1112 dev_info(&dev->dev, 1113 "Added filter for %pM %08x bit %d\n", 1114 ha->addr, 1115 ether_crc(ETH_ALEN, ha->addr), 1116 filterbit); 1117 } 1118 if (mc_filter[0] == tp->mc_filter[0] && 1119 mc_filter[1] == tp->mc_filter[1]) 1120 ; /* No change. */ 1121 else if (tp->flags & IS_ASIX) { 1122 iowrite32(2, ioaddr + CSR13); 1123 iowrite32(mc_filter[0], ioaddr + CSR14); 1124 iowrite32(3, ioaddr + CSR13); 1125 iowrite32(mc_filter[1], ioaddr + CSR14); 1126 } else if (tp->flags & COMET_MAC_ADDR) { 1127 iowrite32(mc_filter[0], ioaddr + CSR27); 1128 iowrite32(mc_filter[1], ioaddr + CSR28); 1129 } 1130 tp->mc_filter[0] = mc_filter[0]; 1131 tp->mc_filter[1] = mc_filter[1]; 1132 } 1133 } else { 1134 unsigned long flags; 1135 u32 tx_flags = 0x08000000 | 192; 1136 1137 /* Note that only the low-address shortword of setup_frame is valid! 1138 The values are doubled for big-endian architectures. */ 1139 if (netdev_mc_count(dev) > 14) { 1140 /* Must use a multicast hash table. */ 1141 build_setup_frame_hash(tp->setup_frame, dev); 1142 tx_flags = 0x08400000 | 192; 1143 } else { 1144 build_setup_frame_perfect(tp->setup_frame, dev); 1145 } 1146 1147 spin_lock_irqsave(&tp->lock, flags); 1148 1149 if (tp->cur_tx - tp->dirty_tx > TX_RING_SIZE - 2) { 1150 /* Same setup recently queued, we need not add it. */ 1151 } else { 1152 unsigned int entry; 1153 int dummy = -1; 1154 1155 /* Now add this frame to the Tx list. */ 1156 1157 entry = tp->cur_tx++ % TX_RING_SIZE; 1158 1159 if (entry != 0) { 1160 /* Avoid a chip errata by prefixing a dummy entry. */ 1161 tp->tx_buffers[entry].skb = NULL; 1162 tp->tx_buffers[entry].mapping = 0; 1163 tp->tx_ring[entry].length = 1164 (entry == TX_RING_SIZE-1) ? cpu_to_le32(DESC_RING_WRAP) : 0; 1165 tp->tx_ring[entry].buffer1 = 0; 1166 /* Must set DescOwned later to avoid race with chip */ 1167 dummy = entry; 1168 entry = tp->cur_tx++ % TX_RING_SIZE; 1169 1170 } 1171 1172 tp->tx_buffers[entry].skb = NULL; 1173 tp->tx_buffers[entry].mapping = 1174 pci_map_single(tp->pdev, tp->setup_frame, 1175 sizeof(tp->setup_frame), 1176 PCI_DMA_TODEVICE); 1177 /* Put the setup frame on the Tx list. */ 1178 if (entry == TX_RING_SIZE-1) 1179 tx_flags |= DESC_RING_WRAP; /* Wrap ring. */ 1180 tp->tx_ring[entry].length = cpu_to_le32(tx_flags); 1181 tp->tx_ring[entry].buffer1 = 1182 cpu_to_le32(tp->tx_buffers[entry].mapping); 1183 tp->tx_ring[entry].status = cpu_to_le32(DescOwned); 1184 if (dummy >= 0) 1185 tp->tx_ring[dummy].status = cpu_to_le32(DescOwned); 1186 if (tp->cur_tx - tp->dirty_tx >= TX_RING_SIZE - 2) 1187 netif_stop_queue(dev); 1188 1189 /* Trigger an immediate transmit demand. */ 1190 iowrite32(0, ioaddr + CSR1); 1191 } 1192 1193 spin_unlock_irqrestore(&tp->lock, flags); 1194 } 1195 1196 iowrite32(csr6, ioaddr + CSR6); 1197} 1198 1199#ifdef CONFIG_TULIP_MWI 1200static void __devinit tulip_mwi_config (struct pci_dev *pdev, 1201 struct net_device *dev) 1202{ 1203 struct tulip_private *tp = netdev_priv(dev); 1204 u8 cache; 1205 u16 pci_command; 1206 u32 csr0; 1207 1208 if (tulip_debug > 3) 1209 printk(KERN_DEBUG "%s: tulip_mwi_config()\n", pci_name(pdev)); 1210 1211 tp->csr0 = csr0 = 0; 1212 1213 /* if we have any cache line size at all, we can do MRM and MWI */ 1214 csr0 |= MRM | MWI; 1215 1216 /* Enable MWI in the standard PCI command bit. 1217 * Check for the case where MWI is desired but not available 1218 */ 1219 pci_try_set_mwi(pdev); 1220 1221 /* read result from hardware (in case bit refused to enable) */ 1222 pci_read_config_word(pdev, PCI_COMMAND, &pci_command); 1223 if ((csr0 & MWI) && (!(pci_command & PCI_COMMAND_INVALIDATE))) 1224 csr0 &= ~MWI; 1225 1226 /* if cache line size hardwired to zero, no MWI */ 1227 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache); 1228 if ((csr0 & MWI) && (cache == 0)) { 1229 csr0 &= ~MWI; 1230 pci_clear_mwi(pdev); 1231 } 1232 1233 /* assign per-cacheline-size cache alignment and 1234 * burst length values 1235 */ 1236 switch (cache) { 1237 case 8: 1238 csr0 |= MRL | (1 << CALShift) | (16 << BurstLenShift); 1239 break; 1240 case 16: 1241 csr0 |= MRL | (2 << CALShift) | (16 << BurstLenShift); 1242 break; 1243 case 32: 1244 csr0 |= MRL | (3 << CALShift) | (32 << BurstLenShift); 1245 break; 1246 default: 1247 cache = 0; 1248 break; 1249 } 1250 1251 /* if we have a good cache line size, we by now have a good 1252 * csr0, so save it and exit 1253 */ 1254 if (cache) 1255 goto out; 1256 1257 /* we don't have a good csr0 or cache line size, disable MWI */ 1258 if (csr0 & MWI) { 1259 pci_clear_mwi(pdev); 1260 csr0 &= ~MWI; 1261 } 1262 1263 /* sane defaults for burst length and cache alignment 1264 * originally from de4x5 driver 1265 */ 1266 csr0 |= (8 << BurstLenShift) | (1 << CALShift); 1267 1268out: 1269 tp->csr0 = csr0; 1270 if (tulip_debug > 2) 1271 printk(KERN_DEBUG "%s: MWI config cacheline=%d, csr0=%08x\n", 1272 pci_name(pdev), cache, csr0); 1273} 1274#endif 1275 1276/* 1277 * Chips that have the MRM/reserved bit quirk and the burst quirk. That 1278 * is the DM910X and the on chip ULi devices 1279 */ 1280 1281static int tulip_uli_dm_quirk(struct pci_dev *pdev) 1282{ 1283 if (pdev->vendor == 0x1282 && pdev->device == 0x9102) 1284 return 1; 1285 return 0; 1286} 1287 1288static const struct net_device_ops tulip_netdev_ops = { 1289 .ndo_open = tulip_open, 1290 .ndo_start_xmit = tulip_start_xmit, 1291 .ndo_tx_timeout = tulip_tx_timeout, 1292 .ndo_stop = tulip_close, 1293 .ndo_get_stats = tulip_get_stats, 1294 .ndo_do_ioctl = private_ioctl, 1295 .ndo_set_multicast_list = set_rx_mode, 1296 .ndo_change_mtu = eth_change_mtu, 1297 .ndo_set_mac_address = eth_mac_addr, 1298 .ndo_validate_addr = eth_validate_addr, 1299#ifdef CONFIG_NET_POLL_CONTROLLER 1300 .ndo_poll_controller = poll_tulip, 1301#endif 1302}; 1303 1304static int __devinit tulip_init_one (struct pci_dev *pdev, 1305 const struct pci_device_id *ent) 1306{ 1307 struct tulip_private *tp; 1308 /* See note below on the multiport cards. */ 1309 static unsigned char last_phys_addr[6] = {0x00, 'L', 'i', 'n', 'u', 'x'}; 1310 static struct pci_device_id early_486_chipsets[] = { 1311 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82424) }, 1312 { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496) }, 1313 { }, 1314 }; 1315 static int last_irq; 1316 static int multiport_cnt; /* For four-port boards w/one EEPROM */ 1317 int i, irq; 1318 unsigned short sum; 1319 unsigned char *ee_data; 1320 struct net_device *dev; 1321 void __iomem *ioaddr; 1322 static int board_idx = -1; 1323 int chip_idx = ent->driver_data; 1324 const char *chip_name = tulip_tbl[chip_idx].chip_name; 1325 unsigned int eeprom_missing = 0; 1326 unsigned int force_csr0 = 0; 1327 1328#ifndef MODULE 1329 if (tulip_debug > 0) 1330 printk_once(KERN_INFO "%s", version); 1331#endif 1332 1333 board_idx++; 1334 1335 /* 1336 * Lan media wire a tulip chip to a wan interface. Needs a very 1337 * different driver (lmc driver) 1338 */ 1339 1340 if (pdev->subsystem_vendor == PCI_VENDOR_ID_LMC) { 1341 pr_err(PFX "skipping LMC card\n"); 1342 return -ENODEV; 1343 } else if (pdev->subsystem_vendor == PCI_VENDOR_ID_SBE && 1344 (pdev->subsystem_device == PCI_SUBDEVICE_ID_SBE_T3E3 || 1345 pdev->subsystem_device == PCI_SUBDEVICE_ID_SBE_2T3E3_P0 || 1346 pdev->subsystem_device == PCI_SUBDEVICE_ID_SBE_2T3E3_P1)) { 1347 pr_err(PFX "skipping SBE T3E3 port\n"); 1348 return -ENODEV; 1349 } 1350 1351 /* 1352 * DM910x chips should be handled by the dmfe driver, except 1353 * on-board chips on SPARC systems. Also, early DM9100s need 1354 * software CRC which only the dmfe driver supports. 1355 */ 1356 1357#ifdef CONFIG_TULIP_DM910X 1358 if (chip_idx == DM910X) { 1359 struct device_node *dp; 1360 1361 if (pdev->vendor == 0x1282 && pdev->device == 0x9100 && 1362 pdev->revision < 0x30) { 1363 pr_info(PFX "skipping early DM9100 with Crc bug (use dmfe)\n"); 1364 return -ENODEV; 1365 } 1366 1367 dp = pci_device_to_OF_node(pdev); 1368 if (!(dp && of_get_property(dp, "local-mac-address", NULL))) { 1369 pr_info(PFX "skipping DM910x expansion card (use dmfe)\n"); 1370 return -ENODEV; 1371 } 1372 } 1373#endif 1374 1375 /* 1376 * Looks for early PCI chipsets where people report hangs 1377 * without the workarounds being on. 1378 */ 1379 1380 1381 if (pci_dev_present(early_486_chipsets)) { 1382 csr0 = MRL | MRM | (8 << BurstLenShift) | (1 << CALShift); 1383 force_csr0 = 1; 1384 } 1385 1386 /* bugfix: the ASIX must have a burst limit or horrible things happen. */ 1387 if (chip_idx == AX88140) { 1388 if ((csr0 & 0x3f00) == 0) 1389 csr0 |= 0x2000; 1390 } 1391 1392 /* PNIC doesn't have MWI/MRL/MRM... */ 1393 if (chip_idx == LC82C168) 1394 csr0 &= ~0xfff10000; /* zero reserved bits 31:20, 16 */ 1395 1396 /* DM9102A has troubles with MRM & clear reserved bits 24:22, 20, 16, 7:1 */ 1397 if (tulip_uli_dm_quirk(pdev)) { 1398 csr0 &= ~0x01f100ff; 1399#if defined(CONFIG_SPARC) 1400 csr0 = (csr0 & ~0xff00) | 0xe000; 1401#endif 1402 } 1403 /* 1404 * And back to business 1405 */ 1406 1407 i = pci_enable_device(pdev); 1408 if (i) { 1409 pr_err(PFX "Cannot enable tulip board #%d, aborting\n", 1410 board_idx); 1411 return i; 1412 } 1413 1414 /* The chip will fail to enter a low-power state later unless 1415 * first explicitly commanded into D0 */ 1416 if (pci_set_power_state(pdev, PCI_D0)) { 1417 printk (KERN_NOTICE PFX 1418 "Failed to set power state to D0\n"); 1419 } 1420 1421 irq = pdev->irq; 1422 1423 /* alloc_etherdev ensures aligned and zeroed private structures */ 1424 dev = alloc_etherdev (sizeof (*tp)); 1425 if (!dev) { 1426 pr_err(PFX "ether device alloc failed, aborting\n"); 1427 return -ENOMEM; 1428 } 1429 1430 SET_NETDEV_DEV(dev, &pdev->dev); 1431 if (pci_resource_len (pdev, 0) < tulip_tbl[chip_idx].io_size) { 1432 pr_err(PFX "%s: I/O region (0x%llx@0x%llx) too small, aborting\n", 1433 pci_name(pdev), 1434 (unsigned long long)pci_resource_len (pdev, 0), 1435 (unsigned long long)pci_resource_start (pdev, 0)); 1436 goto err_out_free_netdev; 1437 } 1438 1439 /* grab all resources from both PIO and MMIO regions, as we 1440 * don't want anyone else messing around with our hardware */ 1441 if (pci_request_regions (pdev, DRV_NAME)) 1442 goto err_out_free_netdev; 1443 1444 ioaddr = pci_iomap(pdev, TULIP_BAR, tulip_tbl[chip_idx].io_size); 1445 1446 if (!ioaddr) 1447 goto err_out_free_res; 1448 1449 /* 1450 * initialize private data structure 'tp' 1451 * it is zeroed and aligned in alloc_etherdev 1452 */ 1453 tp = netdev_priv(dev); 1454 tp->dev = dev; 1455 1456 tp->rx_ring = pci_alloc_consistent(pdev, 1457 sizeof(struct tulip_rx_desc) * RX_RING_SIZE + 1458 sizeof(struct tulip_tx_desc) * TX_RING_SIZE, 1459 &tp->rx_ring_dma); 1460 if (!tp->rx_ring) 1461 goto err_out_mtable; 1462 tp->tx_ring = (struct tulip_tx_desc *)(tp->rx_ring + RX_RING_SIZE); 1463 tp->tx_ring_dma = tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * RX_RING_SIZE; 1464 1465 tp->chip_id = chip_idx; 1466 tp->flags = tulip_tbl[chip_idx].flags; 1467 1468 tp->wolinfo.supported = 0; 1469 tp->wolinfo.wolopts = 0; 1470 /* COMET: Enable power management only for AN983B */ 1471 if (chip_idx == COMET ) { 1472 u32 sig; 1473 pci_read_config_dword (pdev, 0x80, &sig); 1474 if (sig == 0x09811317) { 1475 tp->flags |= COMET_PM; 1476 tp->wolinfo.supported = WAKE_PHY | WAKE_MAGIC; 1477 printk(KERN_INFO "tulip_init_one: Enabled WOL support for AN983B\n"); 1478 } 1479 } 1480 tp->pdev = pdev; 1481 tp->base_addr = ioaddr; 1482 tp->revision = pdev->revision; 1483 tp->csr0 = csr0; 1484 spin_lock_init(&tp->lock); 1485 spin_lock_init(&tp->mii_lock); 1486 init_timer(&tp->timer); 1487 tp->timer.data = (unsigned long)dev; 1488 tp->timer.function = tulip_tbl[tp->chip_id].media_timer; 1489 1490 INIT_WORK(&tp->media_work, tulip_tbl[tp->chip_id].media_task); 1491 1492 dev->base_addr = (unsigned long)ioaddr; 1493 1494#ifdef CONFIG_TULIP_MWI 1495 if (!force_csr0 && (tp->flags & HAS_PCI_MWI)) 1496 tulip_mwi_config (pdev, dev); 1497#endif 1498 1499 /* Stop the chip's Tx and Rx processes. */ 1500 tulip_stop_rxtx(tp); 1501 1502 pci_set_master(pdev); 1503 1504#ifdef CONFIG_GSC 1505 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP) { 1506 switch (pdev->subsystem_device) { 1507 default: 1508 break; 1509 case 0x1061: 1510 case 0x1062: 1511 case 0x1063: 1512 case 0x1098: 1513 case 0x1099: 1514 case 0x10EE: 1515 tp->flags |= HAS_SWAPPED_SEEPROM | NEEDS_FAKE_MEDIA_TABLE; 1516 chip_name = "GSC DS21140 Tulip"; 1517 } 1518 } 1519#endif 1520 1521 /* Clear the missed-packet counter. */ 1522 ioread32(ioaddr + CSR8); 1523 1524 /* The station address ROM is read byte serially. The register must 1525 be polled, waiting for the value to be read bit serially from the 1526 EEPROM. 1527 */ 1528 ee_data = tp->eeprom; 1529 memset(ee_data, 0, sizeof(tp->eeprom)); 1530 sum = 0; 1531 if (chip_idx == LC82C168) { 1532 for (i = 0; i < 3; i++) { 1533 int value, boguscnt = 100000; 1534 iowrite32(0x600 | i, ioaddr + 0x98); 1535 do { 1536 value = ioread32(ioaddr + CSR9); 1537 } while (value < 0 && --boguscnt > 0); 1538 put_unaligned_le16(value, ((__le16 *)dev->dev_addr) + i); 1539 sum += value & 0xffff; 1540 } 1541 } else if (chip_idx == COMET) { 1542 /* No need to read the EEPROM. */ 1543 put_unaligned_le32(ioread32(ioaddr + 0xA4), dev->dev_addr); 1544 put_unaligned_le16(ioread32(ioaddr + 0xA8), dev->dev_addr + 4); 1545 for (i = 0; i < 6; i ++) 1546 sum += dev->dev_addr[i]; 1547 } else { 1548 /* A serial EEPROM interface, we read now and sort it out later. */ 1549 int sa_offset = 0; 1550 int ee_addr_size = tulip_read_eeprom(dev, 0xff, 8) & 0x40000 ? 8 : 6; 1551 int ee_max_addr = ((1 << ee_addr_size) - 1) * sizeof(u16); 1552 1553 if (ee_max_addr > sizeof(tp->eeprom)) 1554 ee_max_addr = sizeof(tp->eeprom); 1555 1556 for (i = 0; i < ee_max_addr ; i += sizeof(u16)) { 1557 u16 data = tulip_read_eeprom(dev, i/2, ee_addr_size); 1558 ee_data[i] = data & 0xff; 1559 ee_data[i + 1] = data >> 8; 1560 } 1561 1562 /* DEC now has a specification (see Notes) but early board makers 1563 just put the address in the first EEPROM locations. */ 1564 /* This does memcmp(ee_data, ee_data+16, 8) */ 1565 for (i = 0; i < 8; i ++) 1566 if (ee_data[i] != ee_data[16+i]) 1567 sa_offset = 20; 1568 if (chip_idx == CONEXANT) { 1569 /* Check that the tuple type and length is correct. */ 1570 if (ee_data[0x198] == 0x04 && ee_data[0x199] == 6) 1571 sa_offset = 0x19A; 1572 } else if (ee_data[0] == 0xff && ee_data[1] == 0xff && 1573 ee_data[2] == 0) { 1574 sa_offset = 2; /* Grrr, damn Matrox boards. */ 1575 multiport_cnt = 4; 1576 } 1577#ifdef CONFIG_MIPS_COBALT 1578 if ((pdev->bus->number == 0) && 1579 ((PCI_SLOT(pdev->devfn) == 7) || 1580 (PCI_SLOT(pdev->devfn) == 12))) { 1581 /* Cobalt MAC address in first EEPROM locations. */ 1582 sa_offset = 0; 1583 /* Ensure our media table fixup get's applied */ 1584 memcpy(ee_data + 16, ee_data, 8); 1585 } 1586#endif 1587#ifdef CONFIG_GSC 1588 /* Check to see if we have a broken srom */ 1589 if (ee_data[0] == 0x61 && ee_data[1] == 0x10) { 1590 /* pci_vendor_id and subsystem_id are swapped */ 1591 ee_data[0] = ee_data[2]; 1592 ee_data[1] = ee_data[3]; 1593 ee_data[2] = 0x61; 1594 ee_data[3] = 0x10; 1595 1596 /* HSC-PCI boards need to be byte-swaped and shifted 1597 * up 1 word. This shift needs to happen at the end 1598 * of the MAC first because of the 2 byte overlap. 1599 */ 1600 for (i = 4; i >= 0; i -= 2) { 1601 ee_data[17 + i + 3] = ee_data[17 + i]; 1602 ee_data[16 + i + 5] = ee_data[16 + i]; 1603 } 1604 } 1605#endif 1606 1607 for (i = 0; i < 6; i ++) { 1608 dev->dev_addr[i] = ee_data[i + sa_offset]; 1609 sum += ee_data[i + sa_offset]; 1610 } 1611 } 1612 /* Lite-On boards have the address byte-swapped. */ 1613 if ((dev->dev_addr[0] == 0xA0 || 1614 dev->dev_addr[0] == 0xC0 || 1615 dev->dev_addr[0] == 0x02) && 1616 dev->dev_addr[1] == 0x00) 1617 for (i = 0; i < 6; i+=2) { 1618 char tmp = dev->dev_addr[i]; 1619 dev->dev_addr[i] = dev->dev_addr[i+1]; 1620 dev->dev_addr[i+1] = tmp; 1621 } 1622 /* On the Zynx 315 Etherarray and other multiport boards only the 1623 first Tulip has an EEPROM. 1624 On Sparc systems the mac address is held in the OBP property 1625 "local-mac-address". 1626 The addresses of the subsequent ports are derived from the first. 1627 Many PCI BIOSes also incorrectly report the IRQ line, so we correct 1628 that here as well. */ 1629 if (sum == 0 || sum == 6*0xff) { 1630#if defined(CONFIG_SPARC) 1631 struct device_node *dp = pci_device_to_OF_node(pdev); 1632 const unsigned char *addr; 1633 int len; 1634#endif 1635 eeprom_missing = 1; 1636 for (i = 0; i < 5; i++) 1637 dev->dev_addr[i] = last_phys_addr[i]; 1638 dev->dev_addr[i] = last_phys_addr[i] + 1; 1639#if defined(CONFIG_SPARC) 1640 addr = of_get_property(dp, "local-mac-address", &len); 1641 if (addr && len == 6) 1642 memcpy(dev->dev_addr, addr, 6); 1643#endif 1644#if defined(__i386__) || defined(__x86_64__) /* Patch up x86 BIOS bug. */ 1645 if (last_irq) 1646 irq = last_irq; 1647#endif 1648 } 1649 1650 for (i = 0; i < 6; i++) 1651 last_phys_addr[i] = dev->dev_addr[i]; 1652 last_irq = irq; 1653 dev->irq = irq; 1654 1655 /* The lower four bits are the media type. */ 1656 if (board_idx >= 0 && board_idx < MAX_UNITS) { 1657 if (options[board_idx] & MEDIA_MASK) 1658 tp->default_port = options[board_idx] & MEDIA_MASK; 1659 if ((options[board_idx] & FullDuplex) || full_duplex[board_idx] > 0) 1660 tp->full_duplex = 1; 1661 if (mtu[board_idx] > 0) 1662 dev->mtu = mtu[board_idx]; 1663 } 1664 if (dev->mem_start & MEDIA_MASK) 1665 tp->default_port = dev->mem_start & MEDIA_MASK; 1666 if (tp->default_port) { 1667 pr_info(DRV_NAME "%d: Transceiver selection forced to %s\n", 1668 board_idx, medianame[tp->default_port & MEDIA_MASK]); 1669 tp->medialock = 1; 1670 if (tulip_media_cap[tp->default_port] & MediaAlwaysFD) 1671 tp->full_duplex = 1; 1672 } 1673 if (tp->full_duplex) 1674 tp->full_duplex_lock = 1; 1675 1676 if (tulip_media_cap[tp->default_port] & MediaIsMII) { 1677 u16 media2advert[] = { 0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200 }; 1678 tp->mii_advertise = media2advert[tp->default_port - 9]; 1679 tp->mii_advertise |= (tp->flags & HAS_8023X); /* Matching bits! */ 1680 } 1681 1682 if (tp->flags & HAS_MEDIA_TABLE) { 1683 sprintf(dev->name, DRV_NAME "%d", board_idx); /* hack */ 1684 tulip_parse_eeprom(dev); 1685 strcpy(dev->name, "eth%d"); /* un-hack */ 1686 } 1687 1688 if ((tp->flags & ALWAYS_CHECK_MII) || 1689 (tp->mtable && tp->mtable->has_mii) || 1690 ( ! tp->mtable && (tp->flags & HAS_MII))) { 1691 if (tp->mtable && tp->mtable->has_mii) { 1692 for (i = 0; i < tp->mtable->leafcount; i++) 1693 if (tp->mtable->mleaf[i].media == 11) { 1694 tp->cur_index = i; 1695 tp->saved_if_port = dev->if_port; 1696 tulip_select_media(dev, 2); 1697 dev->if_port = tp->saved_if_port; 1698 break; 1699 } 1700 } 1701 1702 /* Find the connected MII xcvrs. 1703 Doing this in open() would allow detecting external xcvrs 1704 later, but takes much time. */ 1705 tulip_find_mii (dev, board_idx); 1706 } 1707 1708 /* The Tulip-specific entries in the device structure. */ 1709 dev->netdev_ops = &tulip_netdev_ops; 1710 dev->watchdog_timeo = TX_TIMEOUT; 1711#ifdef CONFIG_TULIP_NAPI 1712 netif_napi_add(dev, &tp->napi, tulip_poll, 16); 1713#endif 1714 SET_ETHTOOL_OPS(dev, &ops); 1715 1716 if (register_netdev(dev)) 1717 goto err_out_free_ring; 1718 1719 pci_set_drvdata(pdev, dev); 1720 1721 dev_info(&dev->dev, 1722#ifdef CONFIG_TULIP_MMIO 1723 "%s rev %d at MMIO %#llx,%s %pM, IRQ %d\n", 1724#else 1725 "%s rev %d at Port %#llx,%s %pM, IRQ %d\n", 1726#endif 1727 chip_name, pdev->revision, 1728 (unsigned long long)pci_resource_start(pdev, TULIP_BAR), 1729 eeprom_missing ? " EEPROM not present," : "", 1730 dev->dev_addr, irq); 1731 1732 if (tp->chip_id == PNIC2) 1733 tp->link_change = pnic2_lnk_change; 1734 else if (tp->flags & HAS_NWAY) 1735 tp->link_change = t21142_lnk_change; 1736 else if (tp->flags & HAS_PNICNWAY) 1737 tp->link_change = pnic_lnk_change; 1738 1739 /* Reset the xcvr interface and turn on heartbeat. */ 1740 switch (chip_idx) { 1741 case DC21140: 1742 case DM910X: 1743 default: 1744 if (tp->mtable) 1745 iowrite32(tp->mtable->csr12dir | 0x100, ioaddr + CSR12); 1746 break; 1747 case DC21142: 1748 if (tp->mii_cnt || tulip_media_cap[dev->if_port] & MediaIsMII) { 1749 iowrite32(csr6_mask_defstate, ioaddr + CSR6); 1750 iowrite32(0x0000, ioaddr + CSR13); 1751 iowrite32(0x0000, ioaddr + CSR14); 1752 iowrite32(csr6_mask_hdcap, ioaddr + CSR6); 1753 } else 1754 t21142_start_nway(dev); 1755 break; 1756 case PNIC2: 1757 /* just do a reset for sanity sake */ 1758 iowrite32(0x0000, ioaddr + CSR13); 1759 iowrite32(0x0000, ioaddr + CSR14); 1760 break; 1761 case LC82C168: 1762 if ( ! tp->mii_cnt) { 1763 tp->nway = 1; 1764 tp->nwayset = 0; 1765 iowrite32(csr6_ttm | csr6_ca, ioaddr + CSR6); 1766 iowrite32(0x30, ioaddr + CSR12); 1767 iowrite32(0x0001F078, ioaddr + CSR6); 1768 iowrite32(0x0201F078, ioaddr + CSR6); /* Turn on autonegotiation. */ 1769 } 1770 break; 1771 case MX98713: 1772 case COMPEX9881: 1773 iowrite32(0x00000000, ioaddr + CSR6); 1774 iowrite32(0x000711C0, ioaddr + CSR14); /* Turn on NWay. */ 1775 iowrite32(0x00000001, ioaddr + CSR13); 1776 break; 1777 case MX98715: 1778 case MX98725: 1779 iowrite32(0x01a80000, ioaddr + CSR6); 1780 iowrite32(0xFFFFFFFF, ioaddr + CSR14); 1781 iowrite32(0x00001000, ioaddr + CSR12); 1782 break; 1783 case COMET: 1784 /* No initialization necessary. */ 1785 break; 1786 } 1787 1788 /* put the chip in snooze mode until opened */ 1789 tulip_set_power_state (tp, 0, 1); 1790 1791 return 0; 1792 1793err_out_free_ring: 1794 pci_free_consistent (pdev, 1795 sizeof (struct tulip_rx_desc) * RX_RING_SIZE + 1796 sizeof (struct tulip_tx_desc) * TX_RING_SIZE, 1797 tp->rx_ring, tp->rx_ring_dma); 1798 1799err_out_mtable: 1800 kfree (tp->mtable); 1801 pci_iounmap(pdev, ioaddr); 1802 1803err_out_free_res: 1804 pci_release_regions (pdev); 1805 1806err_out_free_netdev: 1807 free_netdev (dev); 1808 return -ENODEV; 1809} 1810 1811 1812/* set the registers according to the given wolopts */ 1813static void tulip_set_wolopts (struct pci_dev *pdev, u32 wolopts) 1814{ 1815 struct net_device *dev = pci_get_drvdata(pdev); 1816 struct tulip_private *tp = netdev_priv(dev); 1817 void __iomem *ioaddr = tp->base_addr; 1818 1819 if (tp->flags & COMET_PM) { 1820 1821 unsigned int tmp; 1822 1823 tmp = ioread32(ioaddr + CSR18); 1824 tmp &= ~(comet_csr18_pmes_sticky | comet_csr18_apm_mode | comet_csr18_d3a); 1825 tmp |= comet_csr18_pm_mode; 1826 iowrite32(tmp, ioaddr + CSR18); 1827 1828 /* Set the Wake-up Control/Status Register to the given WOL options*/ 1829 tmp = ioread32(ioaddr + CSR13); 1830 tmp &= ~(comet_csr13_linkoffe | comet_csr13_linkone | comet_csr13_wfre | comet_csr13_lsce | comet_csr13_mpre); 1831 if (wolopts & WAKE_MAGIC) 1832 tmp |= comet_csr13_mpre; 1833 if (wolopts & WAKE_PHY) 1834 tmp |= comet_csr13_linkoffe | comet_csr13_linkone | comet_csr13_lsce; 1835 /* Clear the event flags */ 1836 tmp |= comet_csr13_wfr | comet_csr13_mpr | comet_csr13_lsc; 1837 iowrite32(tmp, ioaddr + CSR13); 1838 } 1839} 1840 1841#ifdef CONFIG_PM 1842 1843 1844static int tulip_suspend (struct pci_dev *pdev, pm_message_t state) 1845{ 1846 pci_power_t pstate; 1847 struct net_device *dev = pci_get_drvdata(pdev); 1848 struct tulip_private *tp = netdev_priv(dev); 1849 1850 if (!dev) 1851 return -EINVAL; 1852 1853 if (!netif_running(dev)) 1854 goto save_state; 1855 1856 tulip_down(dev); 1857 1858 netif_device_detach(dev); 1859 free_irq(dev->irq, dev); 1860 1861save_state: 1862 pci_save_state(pdev); 1863 pci_disable_device(pdev); 1864 pstate = pci_choose_state(pdev, state); 1865 if (state.event == PM_EVENT_SUSPEND && pstate != PCI_D0) { 1866 int rc; 1867 1868 tulip_set_wolopts(pdev, tp->wolinfo.wolopts); 1869 rc = pci_enable_wake(pdev, pstate, tp->wolinfo.wolopts); 1870 if (rc) 1871 printk("tulip: pci_enable_wake failed (%d)\n", rc); 1872 } 1873 pci_set_power_state(pdev, pstate); 1874 1875 return 0; 1876} 1877 1878 1879static int tulip_resume(struct pci_dev *pdev) 1880{ 1881 struct net_device *dev = pci_get_drvdata(pdev); 1882 struct tulip_private *tp = netdev_priv(dev); 1883 void __iomem *ioaddr = tp->base_addr; 1884 int retval; 1885 unsigned int tmp; 1886 1887 if (!dev) 1888 return -EINVAL; 1889 1890 pci_set_power_state(pdev, PCI_D0); 1891 pci_restore_state(pdev); 1892 1893 if (!netif_running(dev)) 1894 return 0; 1895 1896 if ((retval = pci_enable_device(pdev))) { 1897 pr_err(PFX "pci_enable_device failed in resume\n"); 1898 return retval; 1899 } 1900 1901 if ((retval = request_irq(dev->irq, tulip_interrupt, IRQF_SHARED, dev->name, dev))) { 1902 pr_err(PFX "request_irq failed in resume\n"); 1903 return retval; 1904 } 1905 1906 if (tp->flags & COMET_PM) { 1907 pci_enable_wake(pdev, PCI_D3hot, 0); 1908 pci_enable_wake(pdev, PCI_D3cold, 0); 1909 1910 /* Clear the PMES flag */ 1911 tmp = ioread32(ioaddr + CSR20); 1912 tmp |= comet_csr20_pmes; 1913 iowrite32(tmp, ioaddr + CSR20); 1914 1915 /* Disable all wake-up events */ 1916 tulip_set_wolopts(pdev, 0); 1917 } 1918 netif_device_attach(dev); 1919 1920 if (netif_running(dev)) 1921 tulip_up(dev); 1922 1923 return 0; 1924} 1925 1926#endif /* CONFIG_PM */ 1927 1928 1929static void __devexit tulip_remove_one (struct pci_dev *pdev) 1930{ 1931 struct net_device *dev = pci_get_drvdata (pdev); 1932 struct tulip_private *tp; 1933 1934 if (!dev) 1935 return; 1936 1937 tp = netdev_priv(dev); 1938 unregister_netdev(dev); 1939 pci_free_consistent (pdev, 1940 sizeof (struct tulip_rx_desc) * RX_RING_SIZE + 1941 sizeof (struct tulip_tx_desc) * TX_RING_SIZE, 1942 tp->rx_ring, tp->rx_ring_dma); 1943 kfree (tp->mtable); 1944 pci_iounmap(pdev, tp->base_addr); 1945 free_netdev (dev); 1946 pci_release_regions (pdev); 1947 pci_set_drvdata (pdev, NULL); 1948 1949 /* pci_power_off (pdev, -1); */ 1950} 1951 1952#ifdef CONFIG_NET_POLL_CONTROLLER 1953/* 1954 * Polling 'interrupt' - used by things like netconsole to send skbs 1955 * without having to re-enable interrupts. It's not called while 1956 * the interrupt routine is executing. 1957 */ 1958 1959static void poll_tulip (struct net_device *dev) 1960{ 1961 /* disable_irq here is not very nice, but with the lockless 1962 interrupt handler we have no other choice. */ 1963 disable_irq(dev->irq); 1964 tulip_interrupt (dev->irq, dev); 1965 enable_irq(dev->irq); 1966} 1967#endif 1968 1969static struct pci_driver tulip_driver = { 1970 .name = DRV_NAME, 1971 .id_table = tulip_pci_tbl, 1972 .probe = tulip_init_one, 1973 .remove = __devexit_p(tulip_remove_one), 1974#ifdef CONFIG_PM 1975 .suspend = tulip_suspend, 1976 .resume = tulip_resume, 1977#endif /* CONFIG_PM */ 1978}; 1979 1980 1981static int __init tulip_init (void) 1982{ 1983#ifdef MODULE 1984 pr_info("%s", version); 1985#endif 1986 1987 /* copy module parms into globals */ 1988 tulip_rx_copybreak = rx_copybreak; 1989 tulip_max_interrupt_work = max_interrupt_work; 1990 1991 /* probe for and init boards */ 1992 return pci_register_driver(&tulip_driver); 1993} 1994 1995 1996static void __exit tulip_cleanup (void) 1997{ 1998 pci_unregister_driver (&tulip_driver); 1999} 2000 2001 2002module_init(tulip_init); 2003module_exit(tulip_cleanup); 2004