/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
H A D | ci_smumgr.h | 64 uint32_t soft_regs_start; member in struct:ci_smumgr
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H A D | smu7_smumgr.h | 46 uint32_t soft_regs_start; member in struct:smu7_smumgr
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H A D | amdgpu_smu7_smumgr.c | 353 if (smu_data->soft_regs_start) 355 smu_data->soft_regs_start + smum_get_offsetof(hwmgr, 455 smu_data->soft_regs_start + smum_get_offsetof(hwmgr,
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H A D | amdgpu_vegam_smumgr.c | 222 &(smu_data->smu7_data.soft_regs_start), 254 data->soft_regs_start = tmp; 255 smu_data->smu7_data.soft_regs_start = tmp; 1708 smu_data->smu7_data.soft_regs_start + 1722 smu_data->smu7_data.soft_regs_start +
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H A D | amdgpu_fiji_smumgr.c | 316 &(priv->smu7_data.soft_regs_start), 0x40000); 2473 data->soft_regs_start = tmp; 2474 smu_data->smu7_data.soft_regs_start = tmp;
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H A D | amdgpu_iceland_smumgr.c | 258 &(priv->smu7_data.soft_regs_start), 0x40000); 2308 data->soft_regs_start = tmp; 2309 smu7_data->soft_regs_start = tmp;
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H A D | amdgpu_polaris10_smumgr.c | 320 &(smu_data->smu7_data.soft_regs_start), 0x40000); 1634 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start + 2413 data->soft_regs_start = tmp; 2414 smu_data->smu7_data.soft_regs_start = tmp;
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H A D | amdgpu_tonga_smumgr.c | 225 &(priv->smu7_data.soft_regs_start), 0x40000); 2785 data->soft_regs_start = tmp; 2786 smu_data->smu7_data.soft_regs_start = tmp;
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H A D | amdgpu_ci_smumgr.c | 2398 data->soft_regs_start = tmp; 2399 ci_data->soft_regs_start = tmp;
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
H A D | kv_dpm.h | 151 u32 soft_regs_start; member in struct:kv_power_info
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H A D | si_dpm.h | 594 u16 soft_regs_start; member in struct:rv7xx_power_info 987 u32 soft_regs_start; member in struct:si_power_info
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H A D | amdgpu_kv_dpm.c | 605 pi->soft_regs_start = tmp; 1413 return amdgpu_kv_copy_bytes_to_smc(adev, pi->soft_regs_start + reg_offset, 1422 return amdgpu_kv_read_smc_sram_dword(adev, pi->soft_regs_start + reg_offset,
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H A D | amdgpu_si_dpm.c | 3654 si_pi->soft_regs_start + reg_offset, value, 3665 si_pi->soft_regs_start + reg_offset, 3965 si_pi->soft_regs_start = tmp;
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/netbsd-current/sys/external/bsd/drm2/dist/drm/radeon/ |
H A D | kv_dpm.h | 125 u32 soft_regs_start; member in struct:kv_power_info
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H A D | si_dpm.h | 180 u32 soft_regs_start; member in struct:si_power_info
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H A D | ci_dpm.h | 221 u32 soft_regs_start; member in struct:ci_power_info
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H A D | rv770_dpm.h | 138 u16 soft_regs_start; member in struct:rv7xx_power_info
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H A D | radeon_rv770_dpm.c | 245 pi->soft_regs_start + reg_offset, 256 pi->soft_regs_start + reg_offset, 2432 pi->soft_regs_start = RV770_SMC_SOFT_REGISTERS_START;
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H A D | radeon_kv_dpm.c | 478 pi->soft_regs_start = tmp; 1344 return kv_copy_bytes_to_smc(rdev, pi->soft_regs_start + reg_offset, 1353 return kv_read_smc_sram_dword(rdev, pi->soft_regs_start + reg_offset,
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H A D | radeon_ci_dpm.c | 1291 pi->soft_regs_start + reg_offset, 1302 pi->soft_regs_start + reg_offset, 1844 pi->soft_regs_start = tmp;
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H A D | radeon_cypress_dpm.c | 1720 pi->soft_regs_start = (u16)tmp;
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
H A D | smu10_hwmgr.h | 247 uint32_t soft_regs_start; member in struct:smu10_hwmgr
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H A D | smu7_hwmgr.h | 249 uint32_t soft_regs_start; member in struct:smu7_hwmgr
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H A D | smu8_hwmgr.h | 261 uint32_t soft_regs_start; member in struct:smu8_hwmgr
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H A D | amdgpu_smu7_hwmgr.c | 1061 uint32_t handshake_disables_offset = data->soft_regs_start 1077 uint32_t handshake_disables_offset = data->soft_regs_start 1164 data->soft_regs_start + 3558 offset = data->soft_regs_start + smum_get_offsetof(hwmgr, 4109 data->soft_regs_start + smum_get_offsetof(hwmgr, 4114 data->soft_regs_start + smum_get_offsetof(hwmgr, 4751 data->soft_regs_start + 4757 data->soft_regs_start + 4763 data->soft_regs_start + 4769 data->soft_regs_start [all...] |