Searched refs:soft_regs_start (Results 1 - 25 of 27) sorted by relevance

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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
H A Dci_smumgr.h64 uint32_t soft_regs_start; member in struct:ci_smumgr
H A Dsmu7_smumgr.h46 uint32_t soft_regs_start; member in struct:smu7_smumgr
H A Damdgpu_smu7_smumgr.c353 if (smu_data->soft_regs_start)
355 smu_data->soft_regs_start + smum_get_offsetof(hwmgr,
455 smu_data->soft_regs_start + smum_get_offsetof(hwmgr,
H A Damdgpu_vegam_smumgr.c222 &(smu_data->smu7_data.soft_regs_start),
254 data->soft_regs_start = tmp;
255 smu_data->smu7_data.soft_regs_start = tmp;
1708 smu_data->smu7_data.soft_regs_start +
1722 smu_data->smu7_data.soft_regs_start +
H A Damdgpu_fiji_smumgr.c316 &(priv->smu7_data.soft_regs_start), 0x40000);
2473 data->soft_regs_start = tmp;
2474 smu_data->smu7_data.soft_regs_start = tmp;
H A Damdgpu_iceland_smumgr.c258 &(priv->smu7_data.soft_regs_start), 0x40000);
2308 data->soft_regs_start = tmp;
2309 smu7_data->soft_regs_start = tmp;
H A Damdgpu_polaris10_smumgr.c320 &(smu_data->smu7_data.soft_regs_start), 0x40000);
1634 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start +
2413 data->soft_regs_start = tmp;
2414 smu_data->smu7_data.soft_regs_start = tmp;
H A Damdgpu_tonga_smumgr.c225 &(priv->smu7_data.soft_regs_start), 0x40000);
2785 data->soft_regs_start = tmp;
2786 smu_data->smu7_data.soft_regs_start = tmp;
H A Damdgpu_ci_smumgr.c2398 data->soft_regs_start = tmp;
2399 ci_data->soft_regs_start = tmp;
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Dkv_dpm.h151 u32 soft_regs_start; member in struct:kv_power_info
H A Dsi_dpm.h594 u16 soft_regs_start; member in struct:rv7xx_power_info
987 u32 soft_regs_start; member in struct:si_power_info
H A Damdgpu_kv_dpm.c605 pi->soft_regs_start = tmp;
1413 return amdgpu_kv_copy_bytes_to_smc(adev, pi->soft_regs_start + reg_offset,
1422 return amdgpu_kv_read_smc_sram_dword(adev, pi->soft_regs_start + reg_offset,
H A Damdgpu_si_dpm.c3654 si_pi->soft_regs_start + reg_offset, value,
3665 si_pi->soft_regs_start + reg_offset,
3965 si_pi->soft_regs_start = tmp;
/netbsd-current/sys/external/bsd/drm2/dist/drm/radeon/
H A Dkv_dpm.h125 u32 soft_regs_start; member in struct:kv_power_info
H A Dsi_dpm.h180 u32 soft_regs_start; member in struct:si_power_info
H A Dci_dpm.h221 u32 soft_regs_start; member in struct:ci_power_info
H A Drv770_dpm.h138 u16 soft_regs_start; member in struct:rv7xx_power_info
H A Dradeon_rv770_dpm.c245 pi->soft_regs_start + reg_offset,
256 pi->soft_regs_start + reg_offset,
2432 pi->soft_regs_start = RV770_SMC_SOFT_REGISTERS_START;
H A Dradeon_kv_dpm.c478 pi->soft_regs_start = tmp;
1344 return kv_copy_bytes_to_smc(rdev, pi->soft_regs_start + reg_offset,
1353 return kv_read_smc_sram_dword(rdev, pi->soft_regs_start + reg_offset,
H A Dradeon_ci_dpm.c1291 pi->soft_regs_start + reg_offset,
1302 pi->soft_regs_start + reg_offset,
1844 pi->soft_regs_start = tmp;
H A Dradeon_cypress_dpm.c1720 pi->soft_regs_start = (u16)tmp;
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Dsmu10_hwmgr.h247 uint32_t soft_regs_start; member in struct:smu10_hwmgr
H A Dsmu7_hwmgr.h249 uint32_t soft_regs_start; member in struct:smu7_hwmgr
H A Dsmu8_hwmgr.h261 uint32_t soft_regs_start; member in struct:smu8_hwmgr
H A Damdgpu_smu7_hwmgr.c1061 uint32_t handshake_disables_offset = data->soft_regs_start
1077 uint32_t handshake_disables_offset = data->soft_regs_start
1164 data->soft_regs_start +
3558 offset = data->soft_regs_start + smum_get_offsetof(hwmgr,
4109 data->soft_regs_start + smum_get_offsetof(hwmgr,
4114 data->soft_regs_start + smum_get_offsetof(hwmgr,
4751 data->soft_regs_start +
4757 data->soft_regs_start +
4763 data->soft_regs_start +
4769 data->soft_regs_start
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