Searched refs:YCLK_POST_DIV_MASK (Results 1 - 14 of 14) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/radeon/
H A Drv740d.h55 #define YCLK_POST_DIV_MASK (3 << 17) macro
H A Dradeon_rv740_dpm.c217 YCLK_POST_DIV_MASK |
234 YCLK_POST_DIV_MASK |
H A Drv770d.h128 #define YCLK_POST_DIV_MASK (3 << 17) macro
H A Dradeon_rv770_dpm.c433 YCLK_POST_DIV_MASK |
461 YCLK_POST_DIV_MASK |
H A Dradeon_cypress_dpm.c521 YCLK_POST_DIV_MASK |
538 YCLK_POST_DIV_MASK |
H A Dnid.h570 #define YCLK_POST_DIV_MASK (3 << 17) macro
H A Dcikd.h750 #define YCLK_POST_DIV_MASK (7 << 0) macro
H A Dsid.h627 #define YCLK_POST_DIV_MASK (7 << 0) macro
H A Devergreend.h108 #define YCLK_POST_DIV_MASK (3 << 17) macro
H A Dradeon_ni_dpm.c2202 YCLK_POST_DIV_MASK |
2219 YCLK_POST_DIV_MASK |
H A Dradeon_ci_dpm.c2824 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
2828 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
H A Dradeon_si_dpm.c4908 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4912 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Dsid.h629 #define YCLK_POST_DIV_MASK (7 << 0) macro
H A Damdgpu_si_dpm.c5372 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
5376 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);

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