Searched refs:SCLK_MUX_SEL_MASK (Results 1 - 17 of 17) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/radeon/
H A Drv740d.h38 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
H A Drv730d.h41 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
H A Dradeon_rv740_dpm.c156 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
375 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
H A Dradeon_rv730_dpm.c88 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
298 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
H A Drv770d.h104 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
H A Dradeon_rv770_dpm.c535 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
983 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
H A Dnid.h551 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
H A Dcikd.h261 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
H A Dsid.h98 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
H A Devergreend.h86 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
H A Dradeon_cypress_dpm.c1436 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
H A Dradeon_rv770.c1151 tmp &= SCLK_MUX_SEL_MASK;
H A Dradeon_ni_dpm.c1906 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
2037 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
H A Dradeon_si_dpm.c4579 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4819 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
H A Dradeon_ci_dpm.c3031 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Dsid.h100 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
H A Damdgpu_si_dpm.c5044 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5283 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;

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