Searched refs:MPLL_SS2 (Results 1 - 14 of 14) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/radeon/
H A Drv740d.h115 #define MPLL_SS2 0x860 macro
H A Dradeon_rv740_dpm.c316 pi->clk_regs.rv770.mpll_ss2 = RREG32(MPLL_SS2);
H A Dnid.h692 #define MPLL_SS2 0x860 macro
H A Dcikd.h758 #define MPLL_SS2 0x2bd0 macro
H A Dsid.h635 #define MPLL_SS2 0x2bd0 macro
H A Devergreend.h230 #define MPLL_SS2 0x860 macro
H A Dradeon_ni_dpm.c1202 ni_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
H A Dradeon_ci_dpm.c1900 pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
H A Dradeon_si_dpm.c3590 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Dsid.h637 #define MPLL_SS2 0xAF4 macro
H A Damdgpu_si_dpm.c4051 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
H A Damdgpu_iceland_smumgr.c1146 mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
H A Damdgpu_ci_smumgr.c1096 mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
H A Damdgpu_tonga_smumgr.c898 mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);

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