Searched refs:MPLL_SS1 (Results 1 - 14 of 14) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/radeon/
H A Drv740d.h112 #define MPLL_SS1 0x85c macro
H A Dradeon_rv740_dpm.c315 pi->clk_regs.rv770.mpll_ss1 = RREG32(MPLL_SS1);
H A Dnid.h689 #define MPLL_SS1 0x85c macro
H A Dcikd.h755 #define MPLL_SS1 0x2bcc macro
H A Dsid.h632 #define MPLL_SS1 0x2bcc macro
H A Devergreend.h227 #define MPLL_SS1 0x85c macro
H A Dradeon_ni_dpm.c1201 ni_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
H A Dradeon_ci_dpm.c1899 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
H A Dradeon_si_dpm.c3589 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Dsid.h634 #define MPLL_SS1 0xAF3 macro
H A Damdgpu_si_dpm.c4050 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
H A Damdgpu_iceland_smumgr.c1145 mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
H A Damdgpu_ci_smumgr.c1095 mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
H A Damdgpu_tonga_smumgr.c897 mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);

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