Searched refs:AR_PHY_TIMING_CTRL4 (Results 1 - 14 of 14) sorted by relevance

/netbsd-current/sys/external/isc/atheros_hal/dist/ar5211/
H A Dar5211phy.h54 #define AR_PHY_TIMING_CTRL4 0x9920 /* PHY */ macro
H A Dar5211_reset.c486 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4,
687 !(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_IQCAL)) {
725 data = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) |
729 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, data);
/netbsd-current/sys/external/isc/atheros_hal/dist/ar5416/
H A Dar5416_cal_iq.c130 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
H A Dar5416_cal.c68 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
96 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, AR_PHY_TIMING_CTRL4_DO_CAL);
140 if (!ath_hal_wait(ah, AR_PHY_TIMING_CTRL4, AR_PHY_TIMING_CTRL4_DO_CAL, 0)) {
358 if (!(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_CAL)) {
H A Dar5416phy.h58 (AR_PHY_TIMING_CTRL4 + ((_i) << 12))
H A Dar9285_reset.c259 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4,
260 (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) &
H A Dar5416_reset.c1290 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4 + regChainOffset,
1291 (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4 + regChainOffset) &
/netbsd-current/sys/external/isc/atheros_hal/dist/ar5212/
H A Dar5212_reset.c529 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
532 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
1005 !(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_IQCAL)) {
1022 OS_REG_WRITE (ah, AR_PHY_TIMING_CTRL4,
1023 OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) |
1068 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
1070 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
1072 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
1086 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
1089 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
[all...]
H A Dar5212phy.h162 #define AR_PHY_TIMING_CTRL4 0x9920 /* timing control */ macro
/netbsd-current/sys/external/isc/atheros_hal/dist/ar5312/
H A Dar5312_reset.c492 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
495 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
/netbsd-current/sys/dev/usb/
H A Dif_otusreg.h213 #define AR_PHY_TIMING_CTRL4 (AR_PHY_BASE + 0x0120) macro
H A Dif_otus.c2659 tmp = otus_phy_get_def(sc, AR_PHY_TIMING_CTRL4);
2662 otus_write(sc, AR_PHY_TIMING_CTRL4, tmp);
2664 tmp = otus_phy_get_def(sc, AR_PHY_TIMING_CTRL4 + offset);
2667 otus_write(sc, AR_PHY_TIMING_CTRL4 + offset, tmp);
/netbsd-current/sys/dev/ic/
H A Darn5008reg.h94 #define AR_PHY_TIMING_CTRL4(i) (0x9920 + (i) * 0x1000) macro
H A Darn5008.c2079 reg = AR_READ(sc, AR_PHY_TIMING_CTRL4(i));
2082 AR_WRITE(sc, AR_PHY_TIMING_CTRL4(i), reg);

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