Searched refs:AR_PHY_BASE (Results 1 - 13 of 13) sorted by relevance

/netbsd-current/sys/external/isc/atheros_hal/dist/ar5210/
H A Dar5210phy.h27 #define AR_PHY_BASE 0x9800 /* PHY register base */ macro
28 #define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))
H A Dar5210_attach.c237 OS_REG_WRITE(ah, (AR_PHY_BASE + (0x34 << 2)), 0x00001c16);
239 OS_REG_WRITE(ah, (AR_PHY_BASE + (0x20 << 2)), 0x00010000);
240 revid = (OS_REG_READ(ah, AR_PHY_BASE + (256 << 2)) >> 28) & 0xf;
H A Dar5210_misc.c384 nf = (OS_REG_READ(ah, AR_PHY_BASE + (25 << 2)) >> 19) & 0x1ff;
/netbsd-current/sys/dev/usb/
H A Dif_otusreg.h201 #define AR_PHY_BASE 0x1c5800 macro
202 #define AR_PHY(reg) (AR_PHY_BASE + (reg) * 4)
203 #define AR_PHY_TURBO (AR_PHY_BASE + 0x0004)
204 #define AR_PHY_RF_CTL3 (AR_PHY_BASE + 0x0028)
205 #define AR_PHY_RF_CTL4 (AR_PHY_BASE + 0x0034)
206 #define AR_PHY_SETTLING (AR_PHY_BASE + 0x0044)
207 #define AR_PHY_RXGAIN (AR_PHY_BASE + 0x0048)
208 #define AR_PHY_DESIRED_SZ (AR_PHY_BASE + 0x0050)
209 #define AR_PHY_FIND_SIG (AR_PHY_BASE + 0x0058)
210 #define AR_PHY_AGC_CTL1 (AR_PHY_BASE
[all...]
/netbsd-current/sys/external/isc/atheros_hal/dist/ar5211/
H A Dar5211phy.h27 #define AR_PHY_BASE 0x9800 /* PHY registers base address */ macro
28 #define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))
H A Dar5211_attach.c185 OS_REG_WRITE(ah, (AR_PHY_BASE + (0x34 << 2)), 0x00001c16);
187 OS_REG_WRITE(ah, (AR_PHY_BASE + (0x20 << 2)), 0x00010000);
188 val = (OS_REG_READ(ah, AR_PHY_BASE + (256 << 2)) >> 24) & 0xff;
277 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007);
279 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000047);
310 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00004007);
315 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007);
381 uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) };
H A Dar5211_reset.c293 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007);
295 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000047);
1265 OS_REG_WRITE(ah, AR_PHY_BASE + (90 << 2),
1268 OS_REG_WRITE(ah, AR_PHY_BASE + (17 << 2),
1269 (OS_REG_READ(ah, AR_PHY_BASE + (17 << 2)) & 0xFFFFC07F) |
1271 OS_REG_WRITE(ah, AR_PHY_BASE + (18 << 2),
1272 (OS_REG_READ(ah, AR_PHY_BASE + (18 << 2)) & 0xFFFC0FFF) |
1274 OS_REG_WRITE(ah, AR_PHY_BASE + (20 << 2),
1275 (OS_REG_READ(ah, AR_PHY_BASE + (20 << 2)) & 0xFFFF0000) |
1278 OS_REG_WRITE(ah, AR_PHY_BASE
[all...]
H A Dar5211_misc.c179 OS_REG_SET_BIT(ah, AR_PHY_BASE, 0x00002000);
/netbsd-current/sys/external/isc/atheros_hal/dist/ar5212/
H A Dar5212phy.h23 #define AR_PHY_BASE 0x9800 /* base address of phy regs */ macro
24 #define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))
H A Dar5212_attach.c588 uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) };
/netbsd-current/sys/dev/ic/
H A Darn5008reg.h59 #define AR_PHY_BASE 0x9800 macro
60 #define AR_PHY(i) (AR_PHY_BASE + (i) * 4)
/netbsd-current/sys/external/isc/atheros_hal/dist/ar5416/
H A Dar9285_reset.c633 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
H A Dar5416_reset.c1908 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;

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