/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/Target/ |
H A D | TargetSelectionDAGInfo.h | 59 SDValue Op1, SDValue Op2, 76 SDValue Op1, SDValue Op2, 92 SDValue Op1, SDValue Op2, 57 EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument 74 EmitTargetCodeForMemmove(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument 90 EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument
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H A D | TargetLowering.h | 1742 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.h | 60 SDValue Op1, SDValue Op2,
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H A D | ARMISelLowering.h | 527 unsigned Op2,
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H A D | ARMFastISel.cpp | 117 unsigned Op2, bool Op2IsKill); 345 unsigned Op2, bool Op2IsKill) { 353 .addReg(Op2, Op2IsKill * RegState::Kill)); 358 .addReg(Op2, Op2IsKill * RegState::Kill)); 1835 unsigned Op2 = getRegForValue(I->getOperand(1)); local 1836 if (Op2 == 0) return false; 1841 .addReg(Op1).addReg(Op2)); 341 FastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument
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/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/CodeGen/ |
H A D | SelectionDAG.h | 533 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, argument 539 Ops.push_back(Op2); 758 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2); 759 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, 761 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, 763 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, 775 SDValue Op1, SDValue Op2); 777 SDValue Op1, SDValue Op2, SDValue Op3); 791 EVT VT2, SDValue Op1, SDValue Op2); 793 EVT VT2, SDValue Op1, SDValue Op2, SDValu [all...] |
H A D | ISDOpcodes.h | 794 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger); 800 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
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H A D | FastISel.h | 270 unsigned Op2, bool Op2IsKill);
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H A D | SelectionDAGNodes.h | 727 const SDValue &Op2) { 733 Ops[2].setInitial(Op2); 741 const SDValue &Op2, const SDValue &Op3) { 747 Ops[2].setInitial(Op2);
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/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorOps.cpp | 451 SDValue Op2 = Op.getOperand(2); local 454 && Op1.getValueType() == Op2.getValueType() && "Invalid type"); 490 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2); 497 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask); 498 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2); 510 SDValue Op2 = Op.getOperand(2); local 532 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2); [all...] |
H A D | SelectionDAG.cpp | 287 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, argument 289 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 293 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 311 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, argument 313 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 318 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 770 SDValue Op1, SDValue Op2, 775 SDValue Ops[] = { Op1, Op2 }; 4814 SDNode *SelectionDAG::UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2) { argument 4818 if (Op1 == N->getOperand(0) && Op2 769 FindModifiedNodeSlot(SDNode *N, SDValue Op1, SDValue Op2, void *&InsertPos) argument 4843 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) argument 4849 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4) argument 4856 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4, SDValue Op5) argument 4926 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2) argument 4934 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) argument 4984 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) argument 4992 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) argument 5001 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) argument 5144 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT, SDValue Op1, SDValue Op2) argument 5152 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) argument 5181 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) argument 5189 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) argument 5206 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2) argument 5215 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) argument [all...] |
H A D | SelectionDAGBuilder.cpp | 1918 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2); local 1919 Chain = Op2.getValue(1); 1920 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32); 1923 Ops[1] = Op2; 2628 SDValue Op2 = getValue(I.getOperand(1)); local 2630 Op2.getValueType(), Op2)); 2639 SDValue Op2 = getValue(I.getOperand(1)); local 2641 Op1.getValueType(), Op1, Op2)); 2646 SDValue Op2 = getValue(I.getOperand(1)); local 2678 SDValue Op2 = getValue(I.getOperand(1)); local 2699 SDValue Op2 = getValue(I.getOperand(1)); local 2713 SDValue Op2 = getValue(I.getOperand(1)); local 4566 SDValue Op2 = getValue(I.getArgOperand(1)); local 4582 SDValue Op2 = getValue(I.getArgOperand(1)); local 4599 SDValue Op2 = getValue(I.getArgOperand(1)); local 5217 SDValue Op2 = getValue(I.getArgOperand(1)); local [all...] |
H A D | LegalizeIntegerTypes.cpp | 181 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); local 185 Op2, N->getMemOperand(), N->getOrdering(), 194 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); local 198 Op2, Op3, N->getMemOperand(), N->getOrdering(), 853 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); local 855 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(), 1413 unsigned Op1, Op2; local 1416 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; 1418 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; 1427 SDValue Sh1 = DAG.getNode(Op2, d [all...] |
H A D | FastISel.cpp | 1217 unsigned Op2, bool Op2IsKill) { 1225 .addReg(Op2, Op2IsKill * RegState::Kill); 1230 .addReg(Op2, Op2IsKill * RegState::Kill); 1213 FastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument
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H A D | TargetLowering.cpp | 3297 SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl, argument 3299 ConstantSDNode *C = cast<ConstantSDNode>(Op2); 3317 Op2 = DAG.getConstant(xn, Op1.getValueType()); 3318 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Hexagon/ |
H A D | HexagonPeephole.cpp | 276 MachineOperand Op2 = MI->getOperand(S2); local 277 ChangeOpInto(MI->getOperand(S1), Op2);
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 1376 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; local 1377 if (Op.isReg() && Op.getReg() == X86::DX && isDstOp(Op2)) { 1381 delete &Op2; 1389 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; local 1390 if (isSrcOp(Op) && Op2.isReg() && Op2.getReg() == X86::DX) { 1394 delete &Op2; 1403 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; local 1404 if (isSrcOp(Op) && isDstOp(Op2)) { 1408 delete &Op2; 1416 X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]); local 1446 X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]); local [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/Analysis/ |
H A D | ScalarEvolution.h | 585 const SCEV *getAddExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, argument 590 Ops.push_back(Op2); 603 const SCEV *getMulExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, argument 608 Ops.push_back(Op2);
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Analysis/ |
H A D | ConstantFolding.cpp | 1389 if (ConstantFP *Op2 = dyn_cast<ConstantFP>(Operands[1])) { 1390 if (Op2->getType() != Op1->getType()) 1394 (double)Op2->getValueAPF().convertToFloat(): 1395 Op2->getValueAPF().convertToDouble(); 1422 if (ConstantInt *Op2 = dyn_cast<ConstantInt>(Operands[1])) { 1436 Res = Op1->getValue().sadd_ov(Op2->getValue(), Overflow); 1439 Res = Op1->getValue().uadd_ov(Op2->getValue(), Overflow); 1442 Res = Op1->getValue().ssub_ov(Op2->getValue(), Overflow); 1445 Res = Op1->getValue().usub_ov(Op2->getValue(), Overflow); 1448 Res = Op1->getValue().smul_ov(Op2 [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/AsmParser/ |
H A D | LLParser.cpp | 3138 BasicBlock *Op1, *Op2; 3152 ParseTypeAndBasicBlock(Op2, Loc2, PFS)) 3155 Inst = BranchInst::Create(Op1, Op2, Op0); 3463 Value *Op0, *Op1, *Op2; 3468 ParseTypeAndValue(Op2, PFS)) 3471 if (const char *Reason = SelectInst::areInvalidOperands(Op0, Op1, Op2)) 3474 Inst = SelectInst::Create(Op0, Op1, Op2); 3517 Value *Op0, *Op1, *Op2; 3522 ParseTypeAndValue(Op2, PFS)) 3525 if (!InsertElementInst::isValidOperands(Op0, Op1, Op2)) [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Transforms/InstCombine/ |
H A D | InstCombineCompares.cpp | 2225 Value *Op1 = 0, *Op2 = 0; local 2229 Op2 = ConstantExpr::getICmp(I.getPredicate(), C, RHSC); 2237 if ((Op1 && Op2) || (LHSI->hasOneUse() && (Op1 || Op2))) { 2241 if (!Op2) 2242 Op2 = Builder->CreateICmp(I.getPredicate(), LHSI->getOperand(2), 2244 return SelectInst::Create(LHSI->getOperand(0), Op1, Op2); 2950 Value *Op1 = 0, *Op2 = 0; local 2956 Op2 = Builder->CreateFCmp(I.getPredicate(), 2960 Op2 [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/ |
H A D | RegisterCoalescer.cpp | 585 unsigned Op1, Op2, NewDstIdx; local 586 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2)) 589 NewDstIdx = Op2; 590 else if (Op2 == UseOpIdx)
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Bitcode/Reader/ |
H A D | BitcodeReader.cpp | 1207 Constant *Op2 = ValueList.getConstantFwdRef(Record[2], Type::getInt32Ty(Context)); local 1208 V = ConstantExpr::getInsertElement(Op0, Op1, Op2); 1219 Constant *Op2 = ValueList.getConstantFwdRef(Record[2], ShufTy); local 1220 V = ConstantExpr::getShuffleVector(Op0, Op1, Op2); 1233 Constant *Op2 = ValueList.getConstantFwdRef(Record[3], ShufTy); local 1234 V = ConstantExpr::getShuffleVector(Op0, Op1, Op2);
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Transforms/Scalar/ |
H A D | SimplifyLibCalls.cpp | 982 Value *Op1 = CI->getArgOperand(0), *Op2 = CI->getArgOperand(1); 987 return EmitUnaryFloatFnCall(Op2, "exp2", B, Callee->getAttributes()); 990 ConstantFP *Op2C = dyn_cast<ConstantFP>(Op2);
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/X86/ |
H A D | X86FastISel.cpp | 1487 const Value *Op2 = I.getArgOperand(1); local 1489 unsigned Reg2 = getRegForValue(Op2);
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