/macosx-10.9.5/BerkeleyDB-21/db/java/src/com/sleepycat/asm/ |
H A D | Opcodes.java | 199 int FMUL = 106; // - field in interface:Opcodes
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/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGBuilder.cpp | 3706 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3726 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3730 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3749 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3753 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3756 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3778 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3782 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3785 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3788 SDValue t8 = DAG.getNode(ISD::FMUL, d [all...] |
H A D | DAGCombiner.cpp | 436 case ISD::FMUL: 504 case ISD::FMUL: 1138 case ISD::FMUL: return visitFMUL(N); 5696 TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && 5698 if (N0.getOpcode() == ISD::FMUL) { 5707 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5716 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5723 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5734 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5745 return DAG.getNode(ISD::FMUL, [all...] |
H A D | LegalizeVectorOps.cpp | 181 case ISD::FMUL: 576 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
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H A D | SelectionDAGBuilder.h | 479 void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); }
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H A D | SelectionDAGDumper.cpp | 178 case ISD::FMUL: return "fmul";
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H A D | LegalizeFloatTypes.cpp | 79 case ISD::FMUL: R = SoftenFloatRes_FMUL(N); break; 862 case ISD::FMUL: ExpandFloatRes_FMUL(N, Lo, Hi); break;
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H A D | LegalizeVectorTypes.cpp | 101 case ISD::FMUL: 538 case ISD::FMUL: 1309 case ISD::FMUL:
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H A D | FastISel.cpp | 956 return SelectBinaryOp(I, ISD::FMUL);
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H A D | SelectionDAG.cpp | 2804 case ISD::FMUL: 2822 } else if (Opcode == ISD::FMUL) { 3069 case ISD::FMUL: 3151 case ISD::FMUL:
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H A D | LegalizeDAG.cpp | 2238 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
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/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 234 FADD, FSUB, FMUL, FMA, FDIV, FREM, enumerator in enum:llvm::ISD::NodeType
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H A D | SelectionDAG.h | 929 case ISD::FMUL:
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/macosx-10.9.5/cxxfilt-11/cxxfilt/opcodes/ |
H A D | m88k-dis.c | 192 {0x84000000,"fmul.sss ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,1,PFLT,FMUL ,0,1,1,1,0,0,0,1,0,0,0,0} }, 193 {0x84000080,"fmul.ssd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {9,2,PFLT,FMUL ,0,1,1,1,0,0,0,1,0,0,1,0} }, 194 {0x84000200,"fmul.sds ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {9,2,PFLT,FMUL ,0,1,1,1,0,0,0,1,0,1,0,0} }, 195 {0x84000280,"fmul.sdd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {9,2,PFLT,FMUL ,0,1,1,1,0,0,0,1,0,1,1,0} }, 196 {0x84000020,"fmul.dss ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {9,2,PFLT,FMUL ,0,1,1,1,0,0,0,1,1,0,0,0} }, 197 {0x840000a0,"fmul.dsd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {9,2,PFLT,FMUL ,0,1,1,1,0,0,0,1,1,0,1,0} }, 198 {0x84000220,"fmul.dds ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {9,2,PFLT,FMUL ,0,1,1,1,0,0,0,1,1,1,0,0} }, 199 {0x840002a0,"fmul.ddd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {9,2,PFLT,FMUL ,0,1,1,1,0,0,0,1,1,1,1,0} },
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/macosx-10.9.5/cxxfilt-11/cxxfilt/include/opcode/ |
H A D | m88k.h | 344 #define FMUL NOP +3 macro
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/macosx-10.9.5/vim-53/runtime/syntax/ |
H A D | tasm.vim | 50 syn keyword tasmCoprocInstr FLDL2E FLDL2T FLDLG2 FLDLN2 FLDPI FLDZ FMUL FMULP
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H A D | masm.vim | 233 syn keyword masmOpFloat FLDL2T FLDPI FLDZ FLD1 FMUL FMULP FNOP FPATAN
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H A D | nasm.vim | 353 syn keyword nasmFpuInstruction FLDLN2 FLDPI FLDZ FMUL[P]
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MBlaze/Disassembler/ |
H A D | MBlazeDisassembler.cpp | 231 case 0x100: return MBlaze::FMUL;
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/CellSPU/ |
H A D | SPUISelDAGToDAG.cpp | 792 if (Op00.getOpcode() == ISD::FMUL) {
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 1828 case ISD::FMUL: 2729 return SelectBinaryFPOp(I, ISD::FMUL);
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H A D | ARMISelLowering.cpp | 475 setOperationAction(ISD::FMUL, MVT::v2f64, Expand); 5021 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y); 5052 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); 5057 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); 5157 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); 5161 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); 5166 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); 8493 Op.getOpcode() != ISD::FMUL)
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 1239 setOperationAction(ISD::FMUL, MVT::f64, Expand);
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 729 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 835 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 869 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 1035 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 1044 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
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