Searched refs:uart_parents (Results 1 - 23 of 23) sorted by relevance

/linux-master/drivers/clk/spear/
H A Dspear1310_clock.c375 static const char *uart_parents[] = { "ras_apb_clk", "gen_syn3_clk", }; variable
944 clk = clk_register_mux(NULL, "uart1_mclk", uart_parents,
945 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
955 clk = clk_register_mux(NULL, "uart2_mclk", uart_parents,
956 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
966 clk = clk_register_mux(NULL, "uart3_mclk", uart_parents,
967 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
977 clk = clk_register_mux(NULL, "uart4_mclk", uart_parents,
978 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
988 clk = clk_register_mux(NULL, "uart5_mclk", uart_parents,
[all...]
H A Dspear6xx_clock.c99 static const char *uart_parents[] = { "pll3_clk", "uart_syn_gclk", }; variable
166 clk = clk_register_mux(NULL, "uart_mclk", uart_parents,
167 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
/linux-master/drivers/clk/mediatek/
H A Dclk-mt7622.c106 static const char * const uart_parents[] = { variable
406 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
412 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
H A Dclk-mt6795-topckgen.c306 static const char * const uart_parents[] = { variable
466 TOP_MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x60, 8, 1, 15, 0),
H A Dclk-mt7986-topckgen.c82 static const char *const uart_parents[] __initconst = { "top_xtal",
184 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
H A Dclk-mt7629.c137 static const char * const uart_parents[] = { variable
480 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
486 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
H A Dclk-mt8173-topckgen.c127 static const char * const uart_parents[] = { variable
545 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
H A Dclk-mt8135.c227 static const char * const uart_parents[] = { variable
375 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0150, 24, 2, 31),
H A Dclk-mt7981-topckgen.c134 static const char * const uart_parents[] __initconst = {
301 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
H A Dclk-mt8186-topckgen.c117 static const char * const uart_parents[] = { variable
530 uart_parents, 0x0060, 0x0064, 0x0068, 16, 1, 23, 0x0004, 10),
H A Dclk-mt7988-topckgen.c66 static const char *const uart_parents[] = { "top_xtal", "mpll_d8", "mpll_d8_d2" }; variable
127 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020, 0x024, 0x028, 8, 2,
H A Dclk-mt2712.c219 static const char * const uart_parents[] = { variable
656 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060, 8, 1, 15),
H A Dclk-mt8365.c152 static const char * const uart_parents[] = { variable
429 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060,
H A Dclk-mt6797.c156 static const char * const uart_parents[] = { variable
338 MUX_GATE(CLK_TOP_MUX_UART, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
H A Dclk-mt2701.c215 static const char * const uart_parents[] = { variable
504 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
H A Dclk-mt6765.c221 static const char * const uart_parents[] = { variable
402 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
H A Dclk-mt8188-topckgen.c385 static const char * const uart_parents[] = { variable
1014 uart_parents, 0x068, 0x06C, 0x070, 0, 4, 7, 0x04, 24),
H A Dclk-mt8183.c254 static const char * const uart_parents[] = { variable
492 uart_parents, 0x70, 0x74, 0x78, 16, 1, 23, 0x004, 14),
H A Dclk-mt8192.c262 static const char * const uart_parents[] = { variable
599 uart_parents, 0x070, 0x074, 0x078, 8, 1, 15, 0x004, 25),
H A Dclk-mt6779.c354 static const char * const uart_parents[] = { variable
684 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "uart_sel", uart_parents,
H A Dclk-mt8195-topckgen.c322 static const char * const uart_parents[] = { variable
938 uart_parents, 0x068, 0x06C, 0x070, 16, 1, 23, 0x04, 26),
/linux-master/drivers/clk/sprd/
H A Dsc9860-clk.c387 static const char * const uart_parents[] = { "ext-26m", "twpll-48m", variable
389 static SPRD_COMP_CLK(uart0_clk, "uart0", uart_parents, 0x30,
391 static SPRD_COMP_CLK(uart1_clk, "uart1", uart_parents, 0x34,
393 static SPRD_COMP_CLK(uart2_clk, "uart2", uart_parents, 0x38,
395 static SPRD_COMP_CLK(uart3_clk, "uart3", uart_parents, 0x3c,
397 static SPRD_COMP_CLK(uart4_clk, "uart4", uart_parents, 0x40,
611 static SPRD_MUX_CLK(avs_clk, "avs", uart_parents, 0x284,
H A Dums512-clk.c788 static const struct clk_parent_data uart_parents[] = { variable in typeref:struct:clk_parent_data
797 static SPRD_MUX_CLK_DATA(uart0_clk, "uart0-clk", uart_parents,
799 static SPRD_MUX_CLK_DATA(uart1_clk, "uart1-clk", uart_parents,

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