1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * SPEAr6xx machines clock framework source file 4 * 5 * Copyright (C) 2012 ST Microelectronics 6 * Viresh Kumar <vireshk@kernel.org> 7 */ 8 9#include <linux/clkdev.h> 10#include <linux/clk/spear.h> 11#include <linux/io.h> 12#include <linux/spinlock_types.h> 13#include "clk.h" 14 15static DEFINE_SPINLOCK(_lock); 16 17#define PLL1_CTR (misc_base + 0x008) 18#define PLL1_FRQ (misc_base + 0x00C) 19#define PLL2_CTR (misc_base + 0x014) 20#define PLL2_FRQ (misc_base + 0x018) 21#define PLL_CLK_CFG (misc_base + 0x020) 22 /* PLL_CLK_CFG register masks */ 23 #define MCTR_CLK_SHIFT 28 24 #define MCTR_CLK_MASK 3 25 26#define CORE_CLK_CFG (misc_base + 0x024) 27 /* CORE CLK CFG register masks */ 28 #define HCLK_RATIO_SHIFT 10 29 #define HCLK_RATIO_MASK 2 30 #define PCLK_RATIO_SHIFT 8 31 #define PCLK_RATIO_MASK 2 32 33#define PERIP_CLK_CFG (misc_base + 0x028) 34 /* PERIP_CLK_CFG register masks */ 35 #define CLCD_CLK_SHIFT 2 36 #define CLCD_CLK_MASK 2 37 #define UART_CLK_SHIFT 4 38 #define UART_CLK_MASK 1 39 #define FIRDA_CLK_SHIFT 5 40 #define FIRDA_CLK_MASK 2 41 #define GPT0_CLK_SHIFT 8 42 #define GPT1_CLK_SHIFT 10 43 #define GPT2_CLK_SHIFT 11 44 #define GPT3_CLK_SHIFT 12 45 #define GPT_CLK_MASK 1 46 47#define PERIP1_CLK_ENB (misc_base + 0x02C) 48 /* PERIP1_CLK_ENB register masks */ 49 #define UART0_CLK_ENB 3 50 #define UART1_CLK_ENB 4 51 #define SSP0_CLK_ENB 5 52 #define SSP1_CLK_ENB 6 53 #define I2C_CLK_ENB 7 54 #define JPEG_CLK_ENB 8 55 #define FSMC_CLK_ENB 9 56 #define FIRDA_CLK_ENB 10 57 #define GPT2_CLK_ENB 11 58 #define GPT3_CLK_ENB 12 59 #define GPIO2_CLK_ENB 13 60 #define SSP2_CLK_ENB 14 61 #define ADC_CLK_ENB 15 62 #define GPT1_CLK_ENB 11 63 #define RTC_CLK_ENB 17 64 #define GPIO1_CLK_ENB 18 65 #define DMA_CLK_ENB 19 66 #define SMI_CLK_ENB 21 67 #define CLCD_CLK_ENB 22 68 #define GMAC_CLK_ENB 23 69 #define USBD_CLK_ENB 24 70 #define USBH0_CLK_ENB 25 71 #define USBH1_CLK_ENB 26 72 73#define PRSC0_CLK_CFG (misc_base + 0x044) 74#define PRSC1_CLK_CFG (misc_base + 0x048) 75#define PRSC2_CLK_CFG (misc_base + 0x04C) 76 77#define CLCD_CLK_SYNT (misc_base + 0x05C) 78#define FIRDA_CLK_SYNT (misc_base + 0x060) 79#define UART_CLK_SYNT (misc_base + 0x064) 80 81/* vco rate configuration table, in ascending order of rates */ 82static struct pll_rate_tbl pll_rtbl[] = { 83 {.mode = 0, .m = 0x53, .n = 0x0F, .p = 0x1}, /* vco 332 & pll 166 MHz */ 84 {.mode = 0, .m = 0x85, .n = 0x0F, .p = 0x1}, /* vco 532 & pll 266 MHz */ 85 {.mode = 0, .m = 0xA6, .n = 0x0F, .p = 0x1}, /* vco 664 & pll 332 MHz */ 86}; 87 88/* aux rate configuration table, in ascending order of rates */ 89static struct aux_rate_tbl aux_rtbl[] = { 90 /* For PLL1 = 332 MHz */ 91 {.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */ 92 {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */ 93 {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */ 94 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */ 95}; 96 97static const char *clcd_parents[] = { "pll3_clk", "clcd_syn_gclk", }; 98static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk", }; 99static const char *uart_parents[] = { "pll3_clk", "uart_syn_gclk", }; 100static const char *gpt0_1_parents[] = { "pll3_clk", "gpt0_1_syn_clk", }; 101static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", }; 102static const char *gpt3_parents[] = { "pll3_clk", "gpt3_syn_clk", }; 103static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none", 104 "pll2_clk", }; 105 106/* gpt rate configuration table, in ascending order of rates */ 107static struct gpt_rate_tbl gpt_rtbl[] = { 108 /* For pll1 = 332 MHz */ 109 {.mscale = 4, .nscale = 0}, /* 41.5 MHz */ 110 {.mscale = 2, .nscale = 0}, /* 55.3 MHz */ 111 {.mscale = 1, .nscale = 0}, /* 83 MHz */ 112}; 113 114void __init spear6xx_clk_init(void __iomem *misc_base) 115{ 116 struct clk *clk, *clk1; 117 118 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000); 119 clk_register_clkdev(clk, "osc_32k_clk", NULL); 120 121 clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, 0, 30000000); 122 clk_register_clkdev(clk, "osc_30m_clk", NULL); 123 124 /* clock derived from 32 KHz osc clk */ 125 clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0, 126 PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock); 127 clk_register_clkdev(clk, NULL, "rtc-spear"); 128 129 /* clock derived from 30 MHz osc clk */ 130 clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0, 131 48000000); 132 clk_register_clkdev(clk, "pll3_clk", NULL); 133 134 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk", 135 0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), 136 &_lock, &clk1, NULL); 137 clk_register_clkdev(clk, "vco1_clk", NULL); 138 clk_register_clkdev(clk1, "pll1_clk", NULL); 139 140 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "osc_30m_clk", 141 0, PLL2_CTR, PLL2_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), 142 &_lock, &clk1, NULL); 143 clk_register_clkdev(clk, "vco2_clk", NULL); 144 clk_register_clkdev(clk1, "pll2_clk", NULL); 145 146 clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1, 147 1); 148 clk_register_clkdev(clk, NULL, "fc880000.wdt"); 149 150 /* clock derived from pll1 clk */ 151 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 152 CLK_SET_RATE_PARENT, 1, 1); 153 clk_register_clkdev(clk, "cpu_clk", NULL); 154 155 clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk", 156 CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT, 157 HCLK_RATIO_MASK, 0, &_lock); 158 clk_register_clkdev(clk, "ahb_clk", NULL); 159 160 clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0, 161 UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), 162 &_lock, &clk1); 163 clk_register_clkdev(clk, "uart_syn_clk", NULL); 164 clk_register_clkdev(clk1, "uart_syn_gclk", NULL); 165 166 clk = clk_register_mux(NULL, "uart_mclk", uart_parents, 167 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, 168 PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0, 169 &_lock); 170 clk_register_clkdev(clk, "uart_mclk", NULL); 171 172 clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB, 173 UART0_CLK_ENB, 0, &_lock); 174 clk_register_clkdev(clk, NULL, "d0000000.serial"); 175 176 clk = clk_register_gate(NULL, "uart1", "uart_mclk", 0, PERIP1_CLK_ENB, 177 UART1_CLK_ENB, 0, &_lock); 178 clk_register_clkdev(clk, NULL, "d0080000.serial"); 179 180 clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk", 181 0, FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), 182 &_lock, &clk1); 183 clk_register_clkdev(clk, "firda_syn_clk", NULL); 184 clk_register_clkdev(clk1, "firda_syn_gclk", NULL); 185 186 clk = clk_register_mux(NULL, "firda_mclk", firda_parents, 187 ARRAY_SIZE(firda_parents), CLK_SET_RATE_NO_REPARENT, 188 PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, 189 &_lock); 190 clk_register_clkdev(clk, "firda_mclk", NULL); 191 192 clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0, 193 PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock); 194 clk_register_clkdev(clk, NULL, "firda"); 195 196 clk = clk_register_aux("clcd_syn_clk", "clcd_syn_gclk", "pll1_clk", 197 0, CLCD_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), 198 &_lock, &clk1); 199 clk_register_clkdev(clk, "clcd_syn_clk", NULL); 200 clk_register_clkdev(clk1, "clcd_syn_gclk", NULL); 201 202 clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents, 203 ARRAY_SIZE(clcd_parents), CLK_SET_RATE_NO_REPARENT, 204 PERIP_CLK_CFG, CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0, 205 &_lock); 206 clk_register_clkdev(clk, "clcd_mclk", NULL); 207 208 clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0, 209 PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock); 210 clk_register_clkdev(clk, NULL, "fc200000.clcd"); 211 212 /* gpt clocks */ 213 clk = clk_register_gpt("gpt0_1_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, 214 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); 215 clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL); 216 217 clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents, 218 ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT, 219 PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 220 clk_register_clkdev(clk, NULL, "gpt0"); 221 222 clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents, 223 ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT, 224 PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 225 clk_register_clkdev(clk, "gpt1_mclk", NULL); 226 227 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, 228 PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock); 229 clk_register_clkdev(clk, NULL, "gpt1"); 230 231 clk = clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, 232 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); 233 clk_register_clkdev(clk, "gpt2_syn_clk", NULL); 234 235 clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents, 236 ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_NO_REPARENT, 237 PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 238 clk_register_clkdev(clk, "gpt2_mclk", NULL); 239 240 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, 241 PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock); 242 clk_register_clkdev(clk, NULL, "gpt2"); 243 244 clk = clk_register_gpt("gpt3_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, 245 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); 246 clk_register_clkdev(clk, "gpt3_syn_clk", NULL); 247 248 clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents, 249 ARRAY_SIZE(gpt3_parents), CLK_SET_RATE_NO_REPARENT, 250 PERIP_CLK_CFG, GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 251 clk_register_clkdev(clk, "gpt3_mclk", NULL); 252 253 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, 254 PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock); 255 clk_register_clkdev(clk, NULL, "gpt3"); 256 257 /* clock derived from pll3 clk */ 258 clk = clk_register_gate(NULL, "usbh0_clk", "pll3_clk", 0, 259 PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock); 260 clk_register_clkdev(clk, NULL, "e1800000.ehci"); 261 clk_register_clkdev(clk, NULL, "e1900000.ohci"); 262 263 clk = clk_register_gate(NULL, "usbh1_clk", "pll3_clk", 0, 264 PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock); 265 clk_register_clkdev(clk, NULL, "e2000000.ehci"); 266 clk_register_clkdev(clk, NULL, "e2100000.ohci"); 267 268 clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB, 269 USBD_CLK_ENB, 0, &_lock); 270 clk_register_clkdev(clk, NULL, "designware_udc"); 271 272 /* clock derived from ahb clk */ 273 clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2, 274 1); 275 clk_register_clkdev(clk, "ahbmult2_clk", NULL); 276 277 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents, 278 ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT, 279 PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock); 280 clk_register_clkdev(clk, "ddr_clk", NULL); 281 282 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk", 283 CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT, 284 PCLK_RATIO_MASK, 0, &_lock); 285 clk_register_clkdev(clk, "apb_clk", NULL); 286 287 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 288 DMA_CLK_ENB, 0, &_lock); 289 clk_register_clkdev(clk, NULL, "fc400000.dma"); 290 291 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 292 FSMC_CLK_ENB, 0, &_lock); 293 clk_register_clkdev(clk, NULL, "d1800000.flash"); 294 295 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 296 GMAC_CLK_ENB, 0, &_lock); 297 clk_register_clkdev(clk, NULL, "e0800000.ethernet"); 298 299 clk = clk_register_gate(NULL, "i2c_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 300 I2C_CLK_ENB, 0, &_lock); 301 clk_register_clkdev(clk, NULL, "d0200000.i2c"); 302 303 clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 304 JPEG_CLK_ENB, 0, &_lock); 305 clk_register_clkdev(clk, NULL, "jpeg"); 306 307 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 308 SMI_CLK_ENB, 0, &_lock); 309 clk_register_clkdev(clk, NULL, "fc000000.flash"); 310 311 /* clock derived from apb clk */ 312 clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB, 313 ADC_CLK_ENB, 0, &_lock); 314 clk_register_clkdev(clk, NULL, "d820b000.adc"); 315 316 clk = clk_register_fixed_factor(NULL, "gpio0_clk", "apb_clk", 0, 1, 1); 317 clk_register_clkdev(clk, NULL, "f0100000.gpio"); 318 319 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, PERIP1_CLK_ENB, 320 GPIO1_CLK_ENB, 0, &_lock); 321 clk_register_clkdev(clk, NULL, "fc980000.gpio"); 322 323 clk = clk_register_gate(NULL, "gpio2_clk", "apb_clk", 0, PERIP1_CLK_ENB, 324 GPIO2_CLK_ENB, 0, &_lock); 325 clk_register_clkdev(clk, NULL, "d8100000.gpio"); 326 327 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB, 328 SSP0_CLK_ENB, 0, &_lock); 329 clk_register_clkdev(clk, NULL, "d0100000.spi"); 330 331 clk = clk_register_gate(NULL, "ssp1_clk", "apb_clk", 0, PERIP1_CLK_ENB, 332 SSP1_CLK_ENB, 0, &_lock); 333 clk_register_clkdev(clk, NULL, "d0180000.spi"); 334 335 clk = clk_register_gate(NULL, "ssp2_clk", "apb_clk", 0, PERIP1_CLK_ENB, 336 SSP2_CLK_ENB, 0, &_lock); 337 clk_register_clkdev(clk, NULL, "d8180000.spi"); 338} 339