Searched refs:parent_names (Results 1 - 25 of 326) sorted by relevance

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/linux-master/drivers/clk/renesas/
H A Dclk-div6.h6 const char **parent_names, void __iomem *reg,
H A Dclk-div6.c238 * @parent_names: Array containing the names of the parent clocks
244 const char **parent_names,
288 if (parent_names[i]) {
289 parent_names[valid_parents] = parent_names[i];
298 init.parent_names = parent_names;
322 const char **parent_names; local
335 parent_names = kmalloc_array(num_parents, sizeof(*parent_names),
242 cpg_div6_register(const char *name, unsigned int num_parents, const char **parent_names, void __iomem *reg, struct raw_notifier_head *notifiers) argument
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/linux-master/drivers/clk/at91/
H A Dsama5d4.c134 const char *parent_names[5]; local
173 parent_names[0] = "main_rc_osc";
174 parent_names[1] = "main_osc";
175 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);
196 parent_names[0] = slck_name;
197 parent_names[1] = "mainck";
198 parent_names[2] = "plladivck";
199 parent_names[3] = "utmick";
201 parent_names, NULL,
223 parent_names[
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H A Dsama5d3.c119 const char *parent_names[5]; local
158 parent_names[0] = "main_rc_osc";
159 parent_names[1] = "main_osc";
160 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);
181 parent_names[0] = slck_name;
182 parent_names[1] = "mainck";
183 parent_names[2] = "plladivck";
184 parent_names[3] = "utmick";
186 parent_names, NULL,
202 parent_names[
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H A Dat91sam9rl.c72 const char *parent_names[6]; local
118 parent_names[0] = slck_name;
119 parent_names[1] = "mainck";
120 parent_names[2] = "pllack";
121 parent_names[3] = "utmick";
123 parent_names, NULL,
140 parent_names[0] = slck_name;
141 parent_names[1] = "mainck";
142 parent_names[2] = "pllack";
143 parent_names[
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H A Dsama5d2.c170 const char *parent_names[6]; local
210 parent_names[0] = "main_rc_osc";
211 parent_names[1] = "main_osc";
212 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);
258 parent_names[0] = slck_name;
259 parent_names[1] = "mainck";
260 parent_names[2] = "plladivck";
261 parent_names[3] = "utmick";
263 parent_names, NULL,
285 parent_names[
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H A Dclk-slow.c41 const char **parent_names,
52 if (!parent_names || !num_parents)
61 init.parent_names = parent_names;
39 at91_clk_register_sam9260_slow(struct regmap *regmap, const char *name, const char **parent_names, int num_parents) argument
H A Dsam9x60.c183 const char *parent_names[6]; local
227 parent_names[0] = "main_rc_osc";
228 parent_names[1] = "main_osc";
229 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);
279 parent_names[0] = md_slck_name;
280 parent_names[1] = "mainck";
281 parent_names[2] = "pllack_divck";
283 parent_names, NULL, &sam9x60_master_layout,
297 parent_names[0] = "pllack_divck";
298 parent_names[
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H A Dat91sam9g45.c97 const char *parent_names[6]; local
154 parent_names[0] = slck_name;
155 parent_names[1] = "mainck";
156 parent_names[2] = "plladivck";
157 parent_names[3] = "utmick";
159 parent_names, NULL,
177 parent_names[0] = "plladivck";
178 parent_names[1] = "utmick";
179 hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
183 parent_names[
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H A Dat91sam9n12.c117 const char *parent_names[6]; local
155 parent_names[0] = "main_rc_osc";
156 parent_names[1] = "main_osc";
157 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);
181 parent_names[0] = slck_name;
182 parent_names[1] = "mainck";
183 parent_names[2] = "plladivck";
184 parent_names[3] = "pllbck";
186 parent_names, NULL,
208 parent_names[
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H A Dat91sam9x5.c139 const char *parent_names[6]; local
177 parent_names[0] = "main_rc_osc";
178 parent_names[1] = "main_osc";
179 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);
202 parent_names[0] = slck_name;
203 parent_names[1] = "mainck";
204 parent_names[2] = "plladivck";
205 parent_names[3] = "utmick";
207 parent_names, NULL,
223 parent_names[
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H A Dat91rm9200.c82 const char *parent_names[6]; local
138 parent_names[0] = slowxtal_name;
139 parent_names[1] = "mainck";
140 parent_names[2] = "pllack";
141 parent_names[3] = "pllbck";
143 parent_names, NULL,
164 parent_names[0] = slowxtal_name;
165 parent_names[1] = "mainck";
166 parent_names[2] = "pllack";
167 parent_names[
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H A Dclk-i2s-mux.c53 const char * const *parent_names,
66 init.parent_names = parent_names;
52 at91_clk_i2s_mux_register(struct regmap *regmap, const char *name, const char * const *parent_names, unsigned int num_parents, u8 bus_id) argument
H A Dpmc.h146 const char *name, const char **parent_names,
157 const char * const *parent_names,
174 const char **parent_names,
179 int num_parents, const char **parent_names,
187 const char *parent_names, struct clk_hw *parent_hw,
195 const char **parent_names,
238 const char **parent_names, struct clk_hw **parent_hws,
246 const char **parent_names,
251 const char **parent_names, u8 num_parents);
260 const char **parent_names, u
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/linux-master/drivers/clk/x86/
H A Dclk-pmc-atom.c151 const char **parent_names,
165 init.parent_names = parent_names;
240 static void plt_clk_free_parent_names_loop(const char **parent_names, argument
244 kfree_const(parent_names[i]);
245 kfree(parent_names);
259 const char **parent_names; local
273 parent_names = kcalloc(nparents, sizeof(*parent_names),
275 if (!parent_names)
149 plt_clk_register(struct platform_device *pdev, int id, const struct pmc_clk_data *pmc_data, const char **parent_names, int num_parents) argument
307 const char **parent_names; local
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/linux-master/drivers/clk/ti/
H A Dcomposite.c55 const char **parent_names; member in struct:component_clk
119 const char **parent_names = NULL; local
158 parent_names = comp->parent_names;
170 parent_names, num_parents,
193 kfree(cclk->comp_clks[i]->parent_names);
240 const char **parent_names; local
250 parent_names = kcalloc(num_parents, sizeof(char *), GFP_KERNEL);
251 if (!parent_names)
254 of_clk_parent_fill(node, parent_names, num_parent
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H A Dmux.c122 const char * const *parent_names,
139 init.parent_names = parent_names;
170 const char **parent_names; local
183 parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
184 if (!parent_names)
187 of_clk_parent_fill(node, parent_names, num_parents);
210 clk = _register_mux(node, name, parent_names, num_parents,
218 kfree(parent_names);
121 _register_mux(struct device_node *node, const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, struct clk_omap_reg *reg, u8 shift, u32 mask, s8 latch, u8 clk_mux_flags, u32 *table) argument
/linux-master/drivers/clk/
H A Dclk-axm5516.c145 .parent_names = (const char *[]){
157 .parent_names = (const char *[]){
169 .parent_names = (const char *[]){
181 .parent_names = (const char *[]){
193 .parent_names = (const char *[]){
209 .parent_names = (const char *[]){
223 .parent_names = (const char *[]){
237 .parent_names = (const char *[]){
251 .parent_names = (const char *[]){
265 .parent_names
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/linux-master/drivers/clk/berlin/
H A Dbg2.c495 const char *parent_names[9]; local
576 parent_names[0] = clk_names[SYSPLL];
577 parent_names[1] = clk_names[REFCLK];
578 hw = clk_hw_register_mux(NULL, "syspll_byp", parent_names, 2,
584 parent_names[0] = clk_names[MEMPLL];
585 parent_names[1] = clk_names[REFCLK];
586 hw = clk_hw_register_mux(NULL, "mempll_byp", parent_names, 2,
592 parent_names[0] = clk_names[CPUPLL];
593 parent_names[1] = clk_names[REFCLK];
594 hw = clk_hw_register_mux(NULL, "cpupll_byp", parent_names,
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/linux-master/drivers/clk/imx/
H A Dclk.h241 const char * const *parent_names,
315 const char * const *parent_names, int num_parents);
318 const char * const *parent_names,
324 const char * const *parent_names,
419 const char * const *parent_names,
425 #define _imx8m_clk_hw_composite(name, parent_names, reg, composite_flags, flags) \
426 __imx8m_clk_hw_composite(name, parent_names, \
427 ARRAY_SIZE(parent_names), reg, composite_flags, flags)
429 #define imx8m_clk_hw_composite(name, parent_names, reg) \
430 _imx8m_clk_hw_composite(name, parent_names, re
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H A Dclk-imx95-blk-ctl.c42 const char * const *parent_names; member in struct:imx95_blk_ctl_clk_dev_data
63 .parent_names = (const char *[]){ "vpu", },
73 .parent_names = (const char *[]){ "vpujpeg", },
83 .parent_names = (const char *[]){ "vpujpeg", },
103 .parent_names = (const char *[]){ "camisi", },
113 .parent_names = (const char *[]){ "camisi", },
123 .parent_names = (const char *[]){ "camaxi", },
133 .parent_names = (const char *[]){ "camisi", },
143 .parent_names = (const char *[]){ "camisi", },
162 .parent_names
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H A Dclk-composite-7ulp.c69 const char * const *parent_names,
136 hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
150 struct clk_hw *imx7ulp_clk_hw_composite(const char *name, const char * const *parent_names, argument
154 return imx_ulp_clk_hw_composite(name, parent_names, num_parents, mux_present, rate_present,
158 struct clk_hw *imx8ulp_clk_hw_composite(const char *name, const char * const *parent_names, argument
162 return imx_ulp_clk_hw_composite(name, parent_names, num_parents, mux_present, rate_present,
68 imx_ulp_clk_hw_composite(const char *name, const char * const *parent_names, int num_parents, bool mux_present, bool rate_present, bool gate_present, void __iomem *reg, bool has_swrst) argument
/linux-master/drivers/clk/rockchip/
H A Dclk.c39 const char *const *parent_names, u8 num_parents,
106 hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
208 const char *const *parent_names, u8 num_parents,
253 hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
269 frac->mux_frac_idx = match_string(child->parent_names,
286 init.parent_names = child->parent_names;
315 const char *const *parent_names, u8 num_parents,
327 parent_names[0], flags, mult,
349 hw = clk_hw_register_composite(NULL, name, parent_names, num_parent
38 rockchip_clk_register_branch(const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, u32 *mux_table, int div_offset, u8 div_shift, u8 div_width, u8 div_flags, struct clk_div_table *div_table, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, spinlock_t *lock) argument
206 rockchip_clk_register_frac_branch( struct rockchip_clk_provider *ctx, const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 div_flags, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, struct rockchip_clk_branch *child, spinlock_t *lock) argument
314 rockchip_clk_register_factor_branch(const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, unsigned int mult, unsigned int div, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, spinlock_t *lock) argument
593 rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx, unsigned int lookup_id, const char *name, const char *const *parent_names, u8 num_parents, const struct rockchip_cpuclk_reg_data *reg_data, const struct rockchip_cpuclk_rate_table *rates, int nrates) argument
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H A Dclk.h380 * @parent_names: name of the parent clock.
398 const char *const *parent_names; member in struct:rockchip_pll_clock
418 .parent_names = _pnames, \
431 const char *name, const char *const *parent_names,
476 const char *const *parent_names, u8 num_parents,
482 const char *const *parent_names, u8 num_parents,
492 const char *const *parent_names,
502 const char *const *parent_names, u8 num_parents,
507 const char *const *parent_names, u8 num_parents,
531 const char *const *parent_names; member in struct:rockchip_clk_branch
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/linux-master/drivers/clk/ux500/
H A Dclk-sysctrl.c120 const char **parent_names,
167 clk_sysctrl_init.parent_names = parent_names;
187 const char **parent_names = (parent_name ? &parent_name : NULL); local
190 return clk_reg_sysctrl(dev, name, parent_names, num_parents,
205 const char **parent_names = (parent_name ? &parent_name : NULL); local
208 return clk_reg_sysctrl(dev, name, parent_names, num_parents,
216 const char **parent_names,
223 return clk_reg_sysctrl(dev, name, parent_names, num_parents,
118 clk_reg_sysctrl(struct device *dev, const char *name, const char **parent_names, u8 num_parents, u16 *reg_sel, u8 *reg_mask, u8 *reg_bits, unsigned long rate, unsigned long enable_delay_us, unsigned long flags, const struct clk_ops *clk_sysctrl_ops) argument
214 clk_reg_sysctrl_set_parent(struct device *dev, const char *name, const char **parent_names, u8 num_parents, u16 *reg_sel, u8 *reg_mask, u8 *reg_bits, unsigned long flags) argument

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