1// SPDX-License-Identifier: GPL-2.0 2#include <linux/clk-provider.h> 3#include <linux/mfd/syscon.h> 4#include <linux/slab.h> 5 6#include <dt-bindings/clock/at91.h> 7 8#include "pmc.h" 9 10static DEFINE_SPINLOCK(at91sam9g45_mck_lock); 11 12static const struct clk_master_characteristics mck_characteristics = { 13 .output = { .min = 0, .max = 133333333 }, 14 .divisors = { 1, 2, 4, 3 }, 15}; 16 17static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 }; 18 19static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 }; 20 21static const struct clk_range plla_outputs[] = { 22 { .min = 745000000, .max = 800000000 }, 23 { .min = 695000000, .max = 750000000 }, 24 { .min = 645000000, .max = 700000000 }, 25 { .min = 595000000, .max = 650000000 }, 26 { .min = 545000000, .max = 600000000 }, 27 { .min = 495000000, .max = 555000000 }, 28 { .min = 445000000, .max = 500000000 }, 29 { .min = 400000000, .max = 450000000 }, 30}; 31 32static const struct clk_pll_characteristics plla_characteristics = { 33 .input = { .min = 2000000, .max = 32000000 }, 34 .num_output = ARRAY_SIZE(plla_outputs), 35 .output = plla_outputs, 36 .icpll = plla_icpll, 37 .out = plla_out, 38}; 39 40static const struct { 41 char *n; 42 char *p; 43 unsigned long flags; 44 u8 id; 45} at91sam9g45_systemck[] = { 46 /* 47 * ddrck feeds DDR controller and is enabled by bootloader thus we need 48 * to keep it enabled in case there is no Linux consumer for it. 49 */ 50 { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL }, 51 { .n = "uhpck", .p = "usbck", .id = 6 }, 52 { .n = "pck0", .p = "prog0", .id = 8 }, 53 { .n = "pck1", .p = "prog1", .id = 9 }, 54}; 55 56struct pck { 57 char *n; 58 u8 id; 59}; 60 61static const struct pck at91sam9g45_periphck[] = { 62 { .n = "pioA_clk", .id = 2, }, 63 { .n = "pioB_clk", .id = 3, }, 64 { .n = "pioC_clk", .id = 4, }, 65 { .n = "pioDE_clk", .id = 5, }, 66 { .n = "trng_clk", .id = 6, }, 67 { .n = "usart0_clk", .id = 7, }, 68 { .n = "usart1_clk", .id = 8, }, 69 { .n = "usart2_clk", .id = 9, }, 70 { .n = "usart3_clk", .id = 10, }, 71 { .n = "mci0_clk", .id = 11, }, 72 { .n = "twi0_clk", .id = 12, }, 73 { .n = "twi1_clk", .id = 13, }, 74 { .n = "spi0_clk", .id = 14, }, 75 { .n = "spi1_clk", .id = 15, }, 76 { .n = "ssc0_clk", .id = 16, }, 77 { .n = "ssc1_clk", .id = 17, }, 78 { .n = "tcb0_clk", .id = 18, }, 79 { .n = "pwm_clk", .id = 19, }, 80 { .n = "adc_clk", .id = 20, }, 81 { .n = "dma0_clk", .id = 21, }, 82 { .n = "uhphs_clk", .id = 22, }, 83 { .n = "lcd_clk", .id = 23, }, 84 { .n = "ac97_clk", .id = 24, }, 85 { .n = "macb0_clk", .id = 25, }, 86 { .n = "isi_clk", .id = 26, }, 87 { .n = "udphs_clk", .id = 27, }, 88 { .n = "aestdessha_clk", .id = 28, }, 89 { .n = "mci1_clk", .id = 29, }, 90 { .n = "vdec_clk", .id = 30, }, 91}; 92 93static void __init at91sam9g45_pmc_setup(struct device_node *np) 94{ 95 const char *slck_name, *mainxtal_name; 96 struct pmc_data *at91sam9g45_pmc; 97 const char *parent_names[6]; 98 struct regmap *regmap; 99 struct clk_hw *hw; 100 int i; 101 bool bypass; 102 103 i = of_property_match_string(np, "clock-names", "slow_clk"); 104 if (i < 0) 105 return; 106 107 slck_name = of_clk_get_parent_name(np, i); 108 109 i = of_property_match_string(np, "clock-names", "main_xtal"); 110 if (i < 0) 111 return; 112 mainxtal_name = of_clk_get_parent_name(np, i); 113 114 regmap = device_node_to_regmap(np); 115 if (IS_ERR(regmap)) 116 return; 117 118 at91sam9g45_pmc = pmc_data_allocate(PMC_PLLACK + 1, 119 nck(at91sam9g45_systemck), 120 nck(at91sam9g45_periphck), 0, 2); 121 if (!at91sam9g45_pmc) 122 return; 123 124 bypass = of_property_read_bool(np, "atmel,osc-bypass"); 125 126 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, 127 bypass); 128 if (IS_ERR(hw)) 129 goto err_free; 130 131 hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc", NULL); 132 if (IS_ERR(hw)) 133 goto err_free; 134 135 at91sam9g45_pmc->chws[PMC_MAIN] = hw; 136 137 hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0, 138 &at91rm9200_pll_layout, &plla_characteristics); 139 if (IS_ERR(hw)) 140 goto err_free; 141 142 hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack"); 143 if (IS_ERR(hw)) 144 goto err_free; 145 146 at91sam9g45_pmc->chws[PMC_PLLACK] = hw; 147 148 hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL); 149 if (IS_ERR(hw)) 150 goto err_free; 151 152 at91sam9g45_pmc->chws[PMC_UTMI] = hw; 153 154 parent_names[0] = slck_name; 155 parent_names[1] = "mainck"; 156 parent_names[2] = "plladivck"; 157 parent_names[3] = "utmick"; 158 hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, 159 parent_names, NULL, 160 &at91rm9200_master_layout, 161 &mck_characteristics, 162 &at91sam9g45_mck_lock); 163 if (IS_ERR(hw)) 164 goto err_free; 165 166 hw = at91_clk_register_master_div(regmap, "masterck_div", 167 "masterck_pres", NULL, 168 &at91rm9200_master_layout, 169 &mck_characteristics, 170 &at91sam9g45_mck_lock, 171 CLK_SET_RATE_GATE, 0); 172 if (IS_ERR(hw)) 173 goto err_free; 174 175 at91sam9g45_pmc->chws[PMC_MCK] = hw; 176 177 parent_names[0] = "plladivck"; 178 parent_names[1] = "utmick"; 179 hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2); 180 if (IS_ERR(hw)) 181 goto err_free; 182 183 parent_names[0] = slck_name; 184 parent_names[1] = "mainck"; 185 parent_names[2] = "plladivck"; 186 parent_names[3] = "utmick"; 187 parent_names[4] = "masterck_div"; 188 for (i = 0; i < 2; i++) { 189 char name[6]; 190 191 snprintf(name, sizeof(name), "prog%d", i); 192 193 hw = at91_clk_register_programmable(regmap, name, 194 parent_names, NULL, 5, i, 195 &at91sam9g45_programmable_layout, 196 NULL); 197 if (IS_ERR(hw)) 198 goto err_free; 199 200 at91sam9g45_pmc->pchws[i] = hw; 201 } 202 203 for (i = 0; i < ARRAY_SIZE(at91sam9g45_systemck); i++) { 204 hw = at91_clk_register_system(regmap, at91sam9g45_systemck[i].n, 205 at91sam9g45_systemck[i].p, NULL, 206 at91sam9g45_systemck[i].id, 207 at91sam9g45_systemck[i].flags); 208 if (IS_ERR(hw)) 209 goto err_free; 210 211 at91sam9g45_pmc->shws[at91sam9g45_systemck[i].id] = hw; 212 } 213 214 for (i = 0; i < ARRAY_SIZE(at91sam9g45_periphck); i++) { 215 hw = at91_clk_register_peripheral(regmap, 216 at91sam9g45_periphck[i].n, 217 "masterck_div", NULL, 218 at91sam9g45_periphck[i].id); 219 if (IS_ERR(hw)) 220 goto err_free; 221 222 at91sam9g45_pmc->phws[at91sam9g45_periphck[i].id] = hw; 223 } 224 225 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9g45_pmc); 226 227 return; 228 229err_free: 230 kfree(at91sam9g45_pmc); 231} 232/* 233 * The TCB is used as the clocksource so its clock is needed early. This means 234 * this can't be a platform driver. 235 */ 236CLK_OF_DECLARE(at91sam9g45_pmc, "atmel,at91sam9g45-pmc", at91sam9g45_pmc_setup); 237