Searched refs:ctrl_status (Results 1 - 18 of 18) sorted by relevance

/linux-master/drivers/scsi/qla4xxx/
H A Dql4_inline.h45 writel(set_rmask(CSR_SCSI_INTR_ENABLE), &ha->reg->ctrl_status);
46 readl(&ha->reg->ctrl_status);
59 writel(clr_rmask(CSR_SCSI_INTR_ENABLE), &ha->reg->ctrl_status);
60 readl(&ha->reg->ctrl_status);
H A Dql4_dbg.c55 printk(KERN_INFO "0x%02X ctrl_status = 0x%08X\n",
56 (uint8_t) offsetof(struct isp_reg, ctrl_status),
57 readw(&ha->reg->ctrl_status));
125 &ha->reg->ctrl_status);
130 &ha->reg->ctrl_status);
H A Dql4_init.c20 value = readw(&ha->reg->ctrl_status);
711 writel(set_rmask(CSR_BOOT_ENABLE), &ha->reg->ctrl_status);
712 readl(&ha->reg->ctrl_status);
721 uint32_t ctrl_status; local
724 ctrl_status = readw(&ha->reg->ctrl_status);
728 if (ctrl_status & set_rmask(CSR_SCSI_PROCESSOR_INTR))
735 ha->host_no, __func__, ctrl_status, max_wait_time));
746 &ha->reg->ctrl_status);
747 readl(&ha->reg->ctrl_status);
[all...]
H A Dql4_isr.c1089 &ha->reg->ctrl_status);
1090 readl(&ha->reg->ctrl_status);
1150 intr_status = readl(&ha->reg->ctrl_status);
1171 if ((readl(&ha->reg->ctrl_status) &
1174 &ha->reg->ctrl_status);
1175 readl(&ha->reg->ctrl_status);
1179 &ha->reg->ctrl_status);
1180 readl(&ha->reg->ctrl_status);
1192 &ha->reg->ctrl_status);
1193 readl(&ha->reg->ctrl_status);
[all...]
H A Dql4_os.c309 reg_val = readw(&ha->reg->ctrl_status);
4670 uint32_t ctrl_status; local
4684 ctrl_status = readw(&ha->reg->ctrl_status);
4685 if ((ctrl_status & CSR_SCSI_RESET_INTR) != 0)
4686 writel(set_rmask(CSR_SCSI_RESET_INTR), &ha->reg->ctrl_status);
4689 writel(set_rmask(CSR_SOFT_RESET), &ha->reg->ctrl_status);
4690 readl(&ha->reg->ctrl_status);
4705 uint32_t ctrl_status; local
4716 ctrl_status
[all...]
H A Dql4_mbx.c26 writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status);
27 readl(&ha->reg->ctrl_status);
34 intr_status = readl(&ha->reg->ctrl_status);
H A Dql4_fw.h108 __le32 ctrl_status; member in struct:isp_reg
210 /* ctrl_status definitions */
/linux-master/drivers/crypto/virtio/
H A Dvirtio_crypto_skcipher_algs.c202 struct virtio_crypto_inhdr *ctrl_status; local
209 ctrl_status = &vc_ctrl_req->ctrl_status;
210 ctrl_status->status = VIRTIO_CRYPTO_ERR;
228 sg_init_one(&status_sg, &ctrl_status->status, sizeof(ctrl_status->status));
235 if (ctrl_status->status != VIRTIO_CRYPTO_OK) {
237 ctrl_status->status, destroy_session->session_id);
H A Dvirtio_crypto_akcipher_algs.c175 struct virtio_crypto_inhdr *ctrl_status; local
185 ctrl_status = &vc_ctrl_req->ctrl_status;
186 ctrl_status->status = VIRTIO_CRYPTO_ERR;
197 sg_init_one(&inhdr_sg, &ctrl_status->status, sizeof(ctrl_status->status));
204 if (ctrl_status->status != VIRTIO_CRYPTO_OK) {
206 ctrl_status->status, destroy_session->session_id);
H A Dvirtio_crypto_common.h97 struct virtio_crypto_inhdr ctrl_status; member in struct:virtio_crypto_ctrl_request
/linux-master/drivers/scsi/qla2xxx/
H A Dqla_sup.c1201 wrt_reg_dword(&reg->ctrl_status,
1202 rd_reg_dword(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1203 rd_reg_dword(&reg->ctrl_status); /* PCI Posting. */
1244 wrt_reg_dword(&reg->ctrl_status,
1245 rd_reg_dword(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1470 wrt_reg_dword(&reg->ctrl_status,
1471 rd_reg_dword(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1472 rd_reg_dword(&reg->ctrl_status); /* PCI Posting. */
1494 wrt_reg_dword(&reg->ctrl_status,
1495 rd_reg_dword(&reg->ctrl_status)
[all...]
H A Dqla_dbg.c333 wrt_reg_dword(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335 if ((rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
340 if (!(rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
343 wrt_reg_dword(&reg->ctrl_status,
351 if ((rd_reg_dword(&reg->ctrl_status) &
357 if (!(rd_reg_dword(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
803 wrt_reg_word(&reg->ctrl_status, 0x40);
806 wrt_reg_word(&reg->ctrl_status, 0x50);
809 wrt_reg_word(&reg->ctrl_status, 0x00);
839 wrt_reg_word(&reg->ctrl_status,
[all...]
H A Dqla_init.c2897 ha->pci_attr = rd_reg_word(&reg->ctrl_status);
2948 wrt_reg_word(&reg->ctrl_status, 0x20);
2949 rd_reg_word(&reg->ctrl_status);
2958 wrt_reg_word(&reg->ctrl_status, 0x0);
2959 rd_reg_word(&reg->ctrl_status);
2979 ha->pci_attr = rd_reg_word(&reg->ctrl_status);
3023 ha->pci_attr = rd_reg_dword(&reg->ctrl_status);
3141 wrt_reg_word(&reg->ctrl_status, 0x20);
3142 rd_reg_word(&reg->ctrl_status); /* PCI Posting. */
3155 wrt_reg_word(&reg->ctrl_status,
[all...]
H A Dqla_fw.h1172 __le32 ctrl_status; /* Control/Status. */ member in struct:device_reg_24xx
H A Dqla_def.h822 __le16 ctrl_status; /* Control/Status */ member in struct:device_reg_2xxx
H A Dqla_mbx.c593 "ctrl_status=%#x ictrl=%#x istatus=%#x\n",
594 rd_reg_word(&reg->isp.ctrl_status),
/linux-master/drivers/media/platform/qcom/venus/
H A Dhfi_venus.c460 u32 ctrl_status = 0, mask_val = 0; local
479 while (!ctrl_status && count < max_tries) {
480 ctrl_status = readl(cpu_cs_base + CPU_CS_SCIACMDARG0);
481 if ((ctrl_status & CPU_CS_SCIACMDARG0_ERROR_STATUS_MASK) == 4) {
1470 u32 ctrl_status; local
1504 ctrl_status = readl(cpu_cs_base + CPU_CS_SCIACMDARG0);
1505 if (!(ctrl_status & CPU_CS_SCIACMDARG0_PC_READY)) {
1528 u32 ctrl_status, cpu_status; local
1534 ctrl_status = readl(cpu_cs_base + CPU_CS_SCIACMDARG0);
1537 ctrl_status
1548 u32 ctrl_status, cpu_status; local
1568 u32 ctrl_status; local
[all...]
/linux-master/drivers/dma/
H A Dimg-mdc-dma.c95 u32 ctrl_status; member in struct:mdc_hw_list_desc
224 ldesc->ctrl_status = MDC_CONTROL_AND_STATUS_LIST_EN |

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