Lines Matching refs:ctrl_status
309 reg_val = readw(&ha->reg->ctrl_status);
4670 uint32_t ctrl_status;
4684 ctrl_status = readw(&ha->reg->ctrl_status);
4685 if ((ctrl_status & CSR_SCSI_RESET_INTR) != 0)
4686 writel(set_rmask(CSR_SCSI_RESET_INTR), &ha->reg->ctrl_status);
4689 writel(set_rmask(CSR_SOFT_RESET), &ha->reg->ctrl_status);
4690 readl(&ha->reg->ctrl_status);
4705 uint32_t ctrl_status;
4716 ctrl_status = readw(&ha->reg->ctrl_status);
4719 if ((ctrl_status & CSR_NET_RESET_INTR) == 0)
4725 if ((ctrl_status & CSR_NET_RESET_INTR) != 0) {
4731 writel(set_rmask(CSR_NET_RESET_INTR), &ha->reg->ctrl_status);
4732 readl(&ha->reg->ctrl_status);
4740 ctrl_status = readw(&ha->reg->ctrl_status);
4743 if ((ctrl_status & CSR_SOFT_RESET) == 0) {
4756 ctrl_status = readw(&ha->reg->ctrl_status);
4757 if ((ctrl_status & CSR_SCSI_RESET_INTR) != 0) {
4758 writel(set_rmask(CSR_SCSI_RESET_INTR), &ha->reg->ctrl_status);
4759 readl(&ha->reg->ctrl_status);
4772 writel(set_rmask(CSR_FORCE_SOFT_RESET), &ha->reg->ctrl_status);
4773 readl(&ha->reg->ctrl_status);
4779 ctrl_status = readw(&ha->reg->ctrl_status);
4782 if ((ctrl_status & CSR_FORCE_SOFT_RESET) == 0) {
5409 while ((readw(&ha->reg->ctrl_status) &
5486 &ha->reg->ctrl_status);
5487 readl(&ha->reg->ctrl_status);