Lines Matching refs:ctrl_status
460 u32 ctrl_status = 0, mask_val = 0;
479 while (!ctrl_status && count < max_tries) {
480 ctrl_status = readl(cpu_cs_base + CPU_CS_SCIACMDARG0);
481 if ((ctrl_status & CPU_CS_SCIACMDARG0_ERROR_STATUS_MASK) == 4) {
1470 u32 ctrl_status;
1504 ctrl_status = readl(cpu_cs_base + CPU_CS_SCIACMDARG0);
1505 if (!(ctrl_status & CPU_CS_SCIACMDARG0_PC_READY)) {
1528 u32 ctrl_status, cpu_status;
1534 ctrl_status = readl(cpu_cs_base + CPU_CS_SCIACMDARG0);
1537 ctrl_status & CPU_CS_SCIACMDARG0_INIT_IDLE_MSG_MASK)
1548 u32 ctrl_status, cpu_status;
1554 ctrl_status = readl(cpu_cs_base + CPU_CS_SCIACMDARG0);
1557 ctrl_status & CPU_CS_SCIACMDARG0_PC_READY)
1568 u32 ctrl_status;
1584 ctrl_status = readl(cpu_cs_base + CPU_CS_SCIACMDARG0);
1585 if (ctrl_status & CPU_CS_SCIACMDARG0_PC_READY)