Searched refs:clk_base (Results 1 - 25 of 25) sorted by relevance

/linux-master/drivers/clk/nuvoton/
H A Dclk-ma35d1.c463 void __iomem *clk_base; local
478 clk_base = devm_platform_ioremap_resource(pdev, 0);
479 if (IS_ERR(clk_base))
480 return PTR_ERR(clk_base);
490 clk_base + REG_CLK_PWRCTL, 0);
493 clk_base + REG_CLK_PWRCTL, 1);
496 clk_base + REG_CLK_PWRCTL, 2);
499 clk_base + REG_CLK_PWRCTL, 3);
502 hws[HXT], clk_base + REG_CLK_PLL0CTL0);
505 hws[HXT], clk_base
[all...]
/linux-master/drivers/clk/tegra/
H A Dclk-tegra-super-gen4.c95 static void __init tegra_sclk_init(void __iomem *clk_base, argument
109 clk_base + SCLK_BURST_POLICY,
119 clk_base + SCLK_DIVIDER, 0, 8,
132 clk_base + SCLK_BURST_POLICY,
142 clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
146 clk_base + SYSTEM_CLK_RATE,
157 clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
160 CLK_IS_CRITICAL, clk_base + SYSTEM_CLK_RATE,
165 static void __init tegra_super_clk_init(void __iomem *clk_base, argument
182 clk_base
253 tegra_super_clk_gen4_init(void __iomem *clk_base, void __iomem *pmc_base, struct tegra_clk *tegra_clks, struct tegra_clk_pll_params *params) argument
262 tegra_super_clk_gen5_init(void __iomem *clk_base, void __iomem *pmc_base, struct tegra_clk *tegra_clks, struct tegra_clk_pll_params *params) argument
[all...]
H A Dclk-tegra210.c298 static void __iomem *clk_base; variable
504 value = readl_relaxed(clk_base + PLLE_AUX);
520 value = readl_relaxed(clk_base + PLLE_MISC0);
525 writel_relaxed(value, clk_base + PLLE_MISC0);
527 value = readl_relaxed(clk_base + PLLE_AUX);
530 writel_relaxed(value, clk_base + PLLE_AUX);
532 fence_udelay(1, clk_base);
535 writel_relaxed(value, clk_base + PLLE_AUX);
537 fence_udelay(1, clk_base);
547 val = readl_relaxed(clk_base
3089 tegra210_periph_clk_init(struct device_node *np, void __iomem *clk_base, void __iomem *pmc_base) argument
3194 tegra210_pll_init(void __iomem *clk_base, void __iomem *pmc) argument
[all...]
H A Dclk-periph-gate.c20 readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
22 writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
24 writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
27 readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
29 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
59 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
60 writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE);
62 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
137 const char *parent_name, u8 gate_flags, void __iomem *clk_base,
162 gate->clk_base
136 tegra_clk_register_periph_gate(const char *name, const char *parent_name, u8 gate_flags, void __iomem *clk_base, unsigned long flags, int clk_num, int *enable_refcnt) argument
[all...]
H A Dclk-tegra20.c132 static void __iomem *clk_base; variable
574 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL);
608 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) &
630 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0,
636 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
639 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
644 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL,
650 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
653 clk_base + PLLM_OUT, 1, 0,
658 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NUL
[all...]
H A Dclk-tegra-fixed.c25 int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, argument
35 val = readl_relaxed(clk_base + OSC_CTRL);
110 void tegra_clk_osc_resume(void __iomem *clk_base) argument
114 val = readl_relaxed(clk_base + OSC_CTRL) & ~OSC_CTRL_MASK;
116 writel_relaxed(val, clk_base + OSC_CTRL);
117 fence_udelay(2, clk_base);
H A Dclk-tegra-audio.c128 static void __init tegra_audio_sync_clk_init(void __iomem *clk_base, argument
148 clk_base + data->offset, 0, 3, 0,
157 0, clk_base + data->offset, 4,
163 void __init tegra_audio_clk_init(void __iomem *clk_base, argument
184 clk_base, pmc_base, 0, info->pll_params,
194 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
197 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
215 tegra_audio_sync_clk_init(clk_base, tegra_clks, audio_clks,
221 writel_relaxed(1, clk_base + dmic_clks[i].offset);
223 tegra_audio_sync_clk_init(clk_base, tegra_clk
[all...]
H A Dclk.h372 * @clk_base: address of CAR controller
379 void __iomem *clk_base; member in struct:tegra_clk_pll
405 void __iomem *clk_base, void __iomem *pmc,
410 void __iomem *clk_base, void __iomem *pmc,
415 void __iomem *clk_base, void __iomem *pmc,
421 void __iomem *clk_base, void __iomem *pmc,
427 void __iomem *clk_base, void __iomem *pmc,
433 void __iomem *clk_base, void __iomem *pmc,
439 const char *parent_name, void __iomem *clk_base,
446 void __iomem *clk_base, unsigne
564 void __iomem *clk_base; member in struct:tegra_clk_periph_gate
[all...]
H A Dclk-tegra30.c150 static void __iomem *clk_base; variable
819 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
822 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
828 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
831 clk_base + PLLM_OUT, 1, 0,
836 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0,
846 clk = tegra_clk_register_pllu("pll_u", "pll_ref", clk_base, 0,
851 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,
861 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,
874 clk_base
[all...]
H A Dclk-periph.c171 void __iomem *clk_base, u32 offset,
199 periph->mux.reg = clk_base + offset;
200 periph->divider.reg = div ? (clk_base + offset) : NULL;
201 periph->gate.clk_base = clk_base;
218 struct tegra_clk_periph *periph, void __iomem *clk_base,
222 periph, clk_base, offset, flags);
227 struct tegra_clk_periph *periph, void __iomem *clk_base,
232 periph, clk_base, offset, CLK_SET_RATE_PARENT);
235 struct clk *tegra_clk_register_periph_data(void __iomem *clk_base, argument
168 _tegra_clk_register_periph(const char *name, const char * const *parent_names, int num_parents, struct tegra_clk_periph *periph, void __iomem *clk_base, u32 offset, unsigned long flags) argument
216 tegra_clk_register_periph(const char *name, const char * const *parent_names, int num_parents, struct tegra_clk_periph *periph, void __iomem *clk_base, u32 offset, unsigned long flags) argument
225 tegra_clk_register_periph_nodiv(const char *name, const char * const *parent_names, int num_parents, struct tegra_clk_periph *periph, void __iomem *clk_base, u32 offset) argument
[all...]
H A Dclk-tegra114.c130 static void __iomem *clk_base; variable
890 static void __init tegra114_fixed_clk_init(void __iomem *clk_base) argument
899 static void __init tegra114_pll_init(void __iomem *clk_base, argument
905 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
911 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
914 clk_base + PLLC_OUT, 1, 0,
919 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,
924 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,
929 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
935 clk_base
1014 tegra114_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base) argument
[all...]
H A Dclk-tegra124.c119 static void __iomem *clk_base; variable
1024 static __init void tegra124_periph_clk_init(void __iomem *clk_base, argument
1035 clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base,
1040 clk_base + PLLD_MISC, 30, 0, &pll_d_lock);
1044 clk_base, 0, 48,
1049 clk_base, 0, 82,
1053 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
1058 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1064 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1079 clk = tegra_clk_register_periph_data(clk_base, ini
1086 tegra124_pll_init(void __iomem *clk_base, void __iomem *pmc) argument
[all...]
H A Dclk.c99 static void __iomem *clk_base; variable
115 clk_base + periph_regs[id / 32].rst_set_reg);
129 clk_base + periph_regs[id / 32].rst_clr_reg);
168 val = readl_relaxed(clk_base + CLK_OUT_ENB_Y);
174 writel_relaxed(val, clk_base + CLK_OUT_ENB_Y);
184 readl_relaxed(clk_base + periph_regs[i].enb_reg);
188 readl_relaxed(clk_base + periph_regs[i].rst_reg);
198 clk_base + periph_regs[i].enb_reg);
204 fence_udelay(5, clk_base);
208 clk_base
[all...]
H A Dclk-pll.c230 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
237 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
302 lock_addr = pll->clk_base;
1002 val = readl(pll->clk_base + PLLE_SS_CTRL);
1005 writel(val, pll->clk_base + PLLE_SS_CTRL);
1162 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1172 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1174 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1184 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1268 void __iomem *clk_base,
1267 _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params, void __iomem *clk_base, unsigned long parent_rate) argument
1869 _tegra_init_pll(void __iomem *clk_base, void __iomem *pmc, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) argument
1920 tegra_clk_register_pll(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) argument
1951 tegra_clk_register_plle(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) argument
1976 tegra_clk_register_pllu(const char *name, const char *parent_name, void __iomem *clk_base, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) argument
2042 tegra_clk_register_pllxc(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) argument
2106 tegra_clk_register_pllre(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock, unsigned long parent_rate) argument
2155 tegra_clk_register_pllm(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) argument
2197 tegra_clk_register_pllc(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) argument
2271 tegra_clk_register_plle_tegra114(const char *name, const char *parent_name, void __iomem *clk_base, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) argument
2295 tegra_clk_register_pllu_tegra114(const char *name, const char *parent_name, void __iomem *clk_base, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) argument
2329 tegra_clk_register_pllss(const char *name, const char *parent_name, void __iomem *clk_base, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) argument
2411 tegra_clk_register_pllre_tegra210(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock, unsigned long parent_rate) argument
2574 tegra_clk_register_plle_tegra210(const char *name, const char *parent_name, void __iomem *clk_base, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) argument
2597 tegra_clk_register_pllc_tegra210(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) argument
2639 tegra_clk_register_pllss_tegra210(const char *name, const char *parent_name, void __iomem *clk_base, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) argument
2688 tegra_clk_register_pllmb(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) argument
[all...]
H A Dclk-sdmmc-mux.c235 void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags,
259 sdmmc_mux->reg = clk_base + offset;
261 sdmmc_mux->gate.clk_base = clk_base;
234 tegra_clk_register_sdmmc_mux_div(const char *name, void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags, unsigned long flags, void *lock) argument
H A Dclk-tegra-periph.c860 static void __init periph_clk_init(void __iomem *clk_base, argument
882 clk = tegra_clk_register_periph_data(clk_base, data);
887 static void __init gate_clk_init(void __iomem *clk_base, argument
905 clk_base, data->flags,
912 static void __init div_clk_init(void __iomem *clk_base, argument
929 data->p.parent_name, clk_base + data->offset,
939 static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base, argument
950 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base,
966 clk_base + data->offset, 0, data->div_flags,
969 data->div_name, clk_base
1022 tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base, struct tegra_clk *tegra_clks, struct tegra_clk_pll_params *pll_params) argument
[all...]
/linux-master/drivers/clk/
H A Dclk-npcm7xx.c407 void __iomem *clk_base; local
420 clk_base = ioremap(res.start, resource_size(&res));
421 if (!clk_base)
438 hw = npcm7xx_clk_register_pll(clk_base + pll_data->reg,
471 mux_data->flags, clk_base + NPCM7XX_CLKSEL,
491 clk_base + div_data->reg,
515 iounmap(clk_base);
H A Dclk-sp7021.c601 void __iomem *clk_base, *pll_base, *sys_base; local
606 clk_base = devm_platform_ioremap_resource(pdev, 0);
607 if (IS_ERR(clk_base))
608 return PTR_ERR(clk_base);
618 writel((sp_clken[i] << 16) | sp_clken[i], clk_base + i * 4);
684 clk_base + (j >> 4) * 4,
/linux-master/drivers/cpufreq/
H A Ds5pv210-cpufreq.c24 static void __iomem *clk_base; variable
27 #define S5P_CLKREG(x) (clk_base + (x))
624 clk_base = of_iomap(np, 0);
626 if (!clk_base) {
670 iounmap(clk_base);
H A Darmada-37xx-cpufreq.c133 struct regmap *clk_base, u8 *divider)
139 regmap_read(clk_base, ARMADA_37XX_CLK_TBG_SEL, &cpu_tbg_sel);
132 armada37xx_cpufreq_dvfs_setup(struct regmap *base, struct regmap *clk_base, u8 *divider) argument
/linux-master/drivers/clk/ralink/
H A Dclk-mtmips.c99 struct mtmips_clk *clk_base; member in struct:mtmips_clk_data
725 sclk = &priv->data->clk_base[i];
740 sclk = &priv->data->clk_base[i];
747 .clk_base = rt2880_clks_base,
758 .clk_base = rt305x_clks_base,
769 .clk_base = rt3352_clks_base,
780 .clk_base = rt3883_clks_base,
791 .clk_base = rt5350_clks_base,
802 .clk_base = mt7620_clks_base,
813 .clk_base
[all...]
/linux-master/drivers/clk/nxp/
H A Dclk-lpc18xx-cgu.c633 static struct clk *clk_base[BASE_CLK_MAX]; variable in typeref:struct:clk
635 .clks = clk_base,
644 clk_base[i] = lpc18xx_register_base_clk(&lpc18xx_cgu_base_clks[i],
646 if (IS_ERR(clk_base[i]) && PTR_ERR(clk_base[i]) != -ENOENT)
/linux-master/drivers/pinctrl/samsung/
H A Dpinctrl-exynos-arm.c45 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv; local
48 tmp = __raw_readl(clk_base + S5P_OTHERS);
51 __raw_writel(tmp, clk_base + S5P_OTHERS);
60 void __iomem *clk_base; local
73 clk_base = of_iomap(np, 0);
75 if (!clk_base) {
80 ctrl->priv = (void __force *)clk_base;
H A Dpinctrl-exynos.c482 void __iomem *clk_base; local
491 clk_base = (void __iomem *) drvdata->retention_ctrl->priv;
494 clk_base + irq_chip->eint_wake_mask_reg);
/linux-master/drivers/mmc/host/
H A Dsdhci-of-at91.c173 unsigned int clk_base, clk_mul; local
187 clk_base = clk_base_rate / 1000000;
191 caps0 |= FIELD_PREP(SDHCI_CLOCK_V3_BASE_MASK, clk_base);

Completed in 407 milliseconds