Searched refs:UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT (Results 1 - 13 of 13) sorted by relevance

/linux-master/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_2_sh_mask.h278 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 macro
H A Duvd_5_0_sh_mask.h302 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 macro
H A Duvd_6_0_sh_mask.h304 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 macro
H A Duvd_4_0_sh_mask.h213 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x00000005 macro
H A Duvd_3_1_sh_mask.h278 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 macro
/linux-master/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_0_0_sh_mask.h1983 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 macro
H A Dvcn_2_6_0_sh_mask.h3702 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 macro
H A Dvcn_2_5_sh_mask.h2031 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 macro
H A Dvcn_3_0_0_sh_mask.h2761 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 macro
H A Dvcn_5_0_0_sh_mask.h3435 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 macro
H A Dvcn_4_0_3_sh_mask.h3914 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 macro
[all...]
H A Dvcn_4_0_0_sh_mask.h3879 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 macro
H A Dvcn_4_0_5_sh_mask.h3745 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 macro

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