Searched refs:CLK_TOP_MUX_AUD_2 (Results 1 - 11 of 11) sorted by relevance
/linux-master/sound/soc/mediatek/mt8183/ |
H A D | mt8183-afe-clk.c | 32 CLK_TOP_MUX_AUD_2, enumerator in enum:__anon406 71 [CLK_TOP_MUX_AUD_2] = "top_mux_aud_2", 311 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]); 314 __func__, aud_clks[CLK_TOP_MUX_AUD_2], ret); 317 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], 321 __func__, aud_clks[CLK_TOP_MUX_AUD_2], 352 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], 356 __func__, aud_clks[CLK_TOP_MUX_AUD_2], 360 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]); 371 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], [all...] |
/linux-master/sound/soc/mediatek/mt8186/ |
H A D | mt8186-afe-clk.h | 60 CLK_TOP_MUX_AUD_2, enumerator in enum:__anon5164
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H A D | mt8186-afe-clk.c | 53 [CLK_TOP_MUX_AUD_2] = "top_mux_aud_2", 158 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]); 161 __func__, aud_clks[CLK_TOP_MUX_AUD_2], ret); 164 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], 168 __func__, aud_clks[CLK_TOP_MUX_AUD_2], 199 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], 203 __func__, aud_clks[CLK_TOP_MUX_AUD_2], 207 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]); 545 CLK_TOP_MUX_AUD_1 : CLK_TOP_MUX_AUD_2;
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/linux-master/sound/soc/mediatek/mt8192/ |
H A D | mt8192-afe-clk.c | 32 [CLK_TOP_MUX_AUD_2] = "top_mux_aud_2", 148 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]); 151 __func__, aud_clks[CLK_TOP_MUX_AUD_2], ret); 154 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], 158 __func__, aud_clks[CLK_TOP_MUX_AUD_2], 189 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], 193 __func__, aud_clks[CLK_TOP_MUX_AUD_2], 197 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]); 567 CLK_TOP_MUX_AUD_1 : CLK_TOP_MUX_AUD_2;
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H A D | mt8192-afe-clk.h | 189 CLK_TOP_MUX_AUD_2, enumerator in enum:__anon408
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/linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/ |
H A D | mt6797-clk.h | 38 #define CLK_TOP_MUX_AUD_2 28 macro
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H A D | mt8183-clk.h | 56 #define CLK_TOP_MUX_AUD_2 20 macro
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/linux-master/include/dt-bindings/clock/ |
H A D | mt6797-clk.h | 38 #define CLK_TOP_MUX_AUD_2 28 macro
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H A D | mt8183-clk.h | 56 #define CLK_TOP_MUX_AUD_2 20 macro
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/linux-master/drivers/clk/mediatek/ |
H A D | clk-mt6797.c | 366 MUX_GATE(CLK_TOP_MUX_AUD_2, "aud_2_sel", aud_2_parents,
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H A D | clk-mt8183.c | 554 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_2, "aud_2_sel",
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