| /linux-master/drivers/clk/mediatek/ |
| H A D | clk-mt6765-mm.c | 46 GATE_MM(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_ck", 20),
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| H A D | clk-mt2701-mm.c | 35 GATE_DISP0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
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| H A D | clk-mt8167-mm.c | 39 GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "smi_mm", 1),
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| H A D | clk-mt8183-mm.c | 37 GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
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| H A D | clk-mt6795-mm.c | 34 GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
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| H A D | clk-mt6797-mm.c | 34 GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
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| H A D | clk-mt6779-mm.c | 37 GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
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| H A D | clk-mt8173-mm.c | 38 GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
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| H A D | clk-mt2712-mm.c | 45 GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
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| /linux-master/include/dt-bindings/clock/ |
| H A D | mt8167-clk.h | 80 #define CLK_MM_SMI_LARB0 1 macro
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| H A D | mt6797-clk.h | 216 #define CLK_MM_SMI_LARB0 2 macro
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| H A D | mt6765-clk.h | 271 #define CLK_MM_SMI_LARB0 20 macro
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| H A D | mt8173-clk.h | 249 #define CLK_MM_SMI_LARB0 2 macro
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| H A D | mediatek,mt6795-clk.h | 220 #define CLK_MM_SMI_LARB0 1 macro
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| H A D | mt2701-clk.h | 354 #define CLK_MM_SMI_LARB0 2 macro
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| H A D | mt2712-clk.h | 302 #define CLK_MM_SMI_LARB0 1 macro
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| H A D | mt6779-clk.h | 342 #define CLK_MM_SMI_LARB0 2 macro
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| H A D | mt8183-clk.h | 310 #define CLK_MM_SMI_LARB0 1 macro
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| /linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/ |
| H A D | mt8167-clk.h | 80 #define CLK_MM_SMI_LARB0 1 macro
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| H A D | mt6797-clk.h | 216 #define CLK_MM_SMI_LARB0 2 macro
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| H A D | mt6765-clk.h | 271 #define CLK_MM_SMI_LARB0 20 macro
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| H A D | mt8173-clk.h | 249 #define CLK_MM_SMI_LARB0 2 macro
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| H A D | mediatek,mt6795-clk.h | 220 #define CLK_MM_SMI_LARB0 1 macro
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| H A D | mt2701-clk.h | 354 #define CLK_MM_SMI_LARB0 2 macro
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| H A D | mt2712-clk.h | 302 #define CLK_MM_SMI_LARB0 1 macro
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