Searched refs:CLK_MM_DISP_RDMA0 (Results 1 - 25 of 30) sorted by relevance

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/linux-master/drivers/clk/mediatek/
H A Dclk-mt6765-mm.c36 GATE_MM(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_ck", 10),
H A Dclk-mt8186-mm.c36 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "top_disp", 3),
H A Dclk-mt8167-mm.c49 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "smi_mm", 11),
H A Dclk-mt8192-mm.c46 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "disp_sel", 3),
H A Dclk-mt8183-mm.c59 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 23),
H A Dclk-mt6795-mm.c51 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
H A Dclk-mt6797-mm.c52 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 19),
H A Dclk-mt6779-mm.c59 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 23),
H A Dclk-mt8173-mm.c54 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
H A Dclk-mt2712-mm.c62 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
/linux-master/include/dt-bindings/clock/
H A Dmt8167-clk.h90 #define CLK_MM_DISP_RDMA0 11 macro
H A Dmt6797-clk.h234 #define CLK_MM_DISP_RDMA0 20 macro
H A Dmt6765-clk.h261 #define CLK_MM_DISP_RDMA0 10 macro
H A Dmt8173-clk.h265 #define CLK_MM_DISP_RDMA0 18 macro
H A Dmediatek,mt6795-clk.h237 #define CLK_MM_DISP_RDMA0 18 macro
H A Dmt2712-clk.h319 #define CLK_MM_DISP_RDMA0 18 macro
H A Dmt6779-clk.h363 #define CLK_MM_DISP_RDMA0 23 macro
H A Dmt8183-clk.h331 #define CLK_MM_DISP_RDMA0 22 macro
/linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dmt8167-clk.h90 #define CLK_MM_DISP_RDMA0 11 macro
H A Dmt6797-clk.h234 #define CLK_MM_DISP_RDMA0 20 macro
H A Dmt6765-clk.h261 #define CLK_MM_DISP_RDMA0 10 macro
H A Dmt8173-clk.h265 #define CLK_MM_DISP_RDMA0 18 macro
H A Dmediatek,mt6795-clk.h237 #define CLK_MM_DISP_RDMA0 18 macro
H A Dmt2712-clk.h319 #define CLK_MM_DISP_RDMA0 18 macro
H A Dmt6779-clk.h363 #define CLK_MM_DISP_RDMA0 23 macro

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