/haiku-fatelf/src/add-ons/accelerants/via/ |
H A D | SetDisplayMode.c | 53 uint32 startadd,startadd_right; local 89 startadd = (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer; 213 startadd_right = startadd + (target.timing.h_display * (colour_depth1 >> 3)); 220 head1_set_display_start(startadd,colour_depth1); 224 head1_set_display_start(startadd,colour_depth1); 225 // head2_set_display_start(startadd,colour_depth2); 296 head1_set_display_start(startadd,colour_depth1); 338 uint32 startadd,startadd_right; local 408 startadd = v_display_start * si->fbc.bytes_per_row; 409 startadd [all...] |
/haiku-fatelf/src/add-ons/accelerants/neomagic/ |
H A D | SetDisplayMode.c | 54 uint32 startadd; local 87 startadd = (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer; 124 nm_crtc_set_display_start(startadd,colour_depth); 169 uint32 startadd; local 214 startadd = v_display_start * si->fbc.bytes_per_row; 215 startadd += h_display_start * (colour_depth >> 3); 216 startadd += (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer; 220 nm_crtc_set_display_start(startadd,colour_depth);
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/haiku-fatelf/src/add-ons/accelerants/nvidia/ |
H A D | SetDisplayMode.c | 37 uint32 startadd,startadd_right; local 74 startadd = (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer; 194 startadd_right = startadd + (target.timing.h_display * (colour_depth1 >> 3)); 201 head1_set_display_start(startadd,colour_depth1); 205 head1_set_display_start(startadd,colour_depth1); 206 head2_set_display_start(startadd,colour_depth2); 273 head1_set_display_start(startadd,colour_depth1); 352 uint32 startadd,startadd_right; local 401 startadd = v_display_start * si->fbc.bytes_per_row; 402 startadd [all...] |
/haiku-fatelf/src/add-ons/accelerants/nvidia_gpgpu/ |
H A D | SetDisplayMode.c | 37 uint32 startadd,startadd_right; local 70 startadd = (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer; 177 startadd_right = startadd + (target.timing.h_display * (colour_depth1 >> 3)); 184 // head1_set_display_start(startadd,colour_depth1); 188 // head1_set_display_start(startadd,colour_depth1); 189 // head2_set_display_start(startadd,colour_depth2); 253 // head1_set_display_start(startadd,colour_depth1); 322 uint32 startadd,startadd_right; local 371 startadd = v_display_start * si->fbc.bytes_per_row; 372 startadd [all...] |
/haiku-fatelf/src/add-ons/accelerants/matrox/ |
H A D | SetDisplayMode.c | 56 uint32 startadd,startadd_right; local 89 startadd = (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer; 158 startadd_right=startadd+(target.timing.h_display * (colour_depth1 >> 3)); 288 uint32 temp = startadd; 289 startadd = startadd_right; 298 gx00_crtc_set_display_start(startadd,colour_depth1); 302 gx00_crtc_set_display_start(startadd,colour_depth1); 303 g400_crtc2_set_display_start(startadd,colour_depth2); 365 gx00_crtc_set_display_start(startadd,colour_depth1); 442 uint32 startadd,startadd_righ local [all...] |
/haiku-fatelf/src/add-ons/accelerants/skeleton/ |
H A D | SetDisplayMode.c | 53 uint32 startadd,startadd_right; local 89 startadd = (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer; 213 startadd_right = startadd + (target.timing.h_display * (colour_depth1 >> 3)); 220 // head1_set_display_start(startadd,colour_depth1); 224 // head1_set_display_start(startadd,colour_depth1); 225 // head2_set_display_start(startadd,colour_depth2); 297 // head1_set_display_start(startadd,colour_depth1); 339 uint32 startadd,startadd_right; local 388 startadd = v_display_start * si->fbc.bytes_per_row; 389 startadd [all...] |
/haiku-fatelf/src/add-ons/accelerants/matrox/engine/ |
H A D | mga_crtc2.c | 294 status_t g400_crtc2_set_display_start(uint32 startadd,uint8 bpp) argument 298 LOG(2,("CRTC2: startadd: $%x\n",startadd)); 308 CR2W(STARTADD0, (startadd + si->fbc.bytes_per_row)); 310 CR2W(STARTADD1, startadd); 316 CR2W(STARTADD0, startadd);
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H A D | mga_crtc.c | 364 status_t gx00_crtc_set_display_start(uint32 startadd,uint8 bpp) argument 371 startadd >>= 3; 373 LOG(2,("CRTC: startadd: %x\n",startadd)); 392 VGAW_I(CRTC,0xD,startadd&0xFF); 393 VGAW_I(CRTC,0xC,(startadd&0xFF00)>>8); 397 ext0|= (startadd&0xF0000)>>16; 401 ext0|=(startadd&0x100000)>>14; 405 VGAW_I(CRTCEXT,8,((startadd&0x200000)>>21));
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H A D | mga_proto.h | 89 status_t gx00_crtc_set_display_start(uint32 startadd,uint8 bpp); 104 status_t g400_crtc2_set_display_start(uint32 startadd,uint8 bpp);
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/haiku-fatelf/src/add-ons/accelerants/skeleton/engine/ |
H A D | crtc.c | 600 status_t eng_crtc_set_display_start(uint32 startadd,uint8 bpp) argument 607 LOG(2,("CRTC: startadd: $%08x\n", startadd)); 630 CRTCW(FBSTADDL, ((startadd & 0x000003fc) >> 2)); 631 CRTCW(FBSTADDH, ((startadd & 0x0003fc00) >> 10)); 636 CRTCW(REPAINT0, (temp | ((startadd & 0x007c0000) >> 18))); 639 CRTCW(HEB, (temp | ((startadd & 0x01800000) >> 18))); 649 ENG_RG32(RG32_NV10FBSTADD32) = (startadd & 0xfffffffc); 653 ATBW(HORPIXPAN, ((startadd & 0x00000003) << 1));
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H A D | proto.h | 69 status_t eng_crtc_set_display_start(uint32 startadd,uint8 bpp); 89 status_t eng_crtc2_set_display_start(uint32 startadd,uint8 bpp);
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H A D | crtc2.c | 583 status_t eng_crtc2_set_display_start(uint32 startadd,uint8 bpp) argument 589 LOG(2,("CRTC2: startadd: $%08x\n", startadd)); 612 ENG_RG32(RG32_NV10FB2STADD32) = (startadd & 0xfffffffc); 615 ATB2W(HORPIXPAN, ((startadd & 0x00000003) << 1));
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/haiku-fatelf/src/add-ons/accelerants/neomagic/engine/ |
H A D | nm_crtc.c | 510 status_t nm_crtc_set_display_start(uint32 startadd,uint8 bpp) argument 515 LOG(2,("CRTC: relative startadd: $%06x\n",startadd)); 540 ISACRTCW(FBSTADDH, ((startadd & 0x03fc00) >> 10)); 541 ISACRTCW(FBSTADDL, ((startadd & 0x0003fc) >> 2)); 552 ISAGRPHW(FBSTADDE,(((startadd >> 18) & 0x07) | (val & 0xf8))); 555 ISAGRPHW(FBSTADDE,(((startadd >> 18) & 0x0f) | (val & 0xf0))); 562 ISAATBW(HORPIXPAN, (startadd & 0x00000003)); 566 ISAATBW(HORPIXPAN, ((startadd & 0x00000002) >> 1)); 569 ISAATBW(HORPIXPAN, ((4 - (startadd [all...] |
H A D | nm_proto.h | 42 status_t nm_crtc_set_display_start(uint32 startadd,uint8 bpp);
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/haiku-fatelf/src/add-ons/accelerants/nvidia/engine/ |
H A D | nv_crtc.c | 757 status_t nv_crtc_set_display_start(uint32 startadd,uint8 bpp) argument 764 LOG(2,("CRTC: startadd: $%08x\n", startadd)); 787 CRTCW(FBSTADDL, ((startadd & 0x000003fc) >> 2)); 788 CRTCW(FBSTADDH, ((startadd & 0x0003fc00) >> 10)); 793 CRTCW(REPAINT0, (temp | ((startadd & 0x007c0000) >> 18))); 796 CRTCW(HEB, (temp | ((startadd & 0x01800000) >> 18))); 806 NV_REG32(NV32_NV10FBSTADD32) = (startadd & 0xfffffffc); 810 ATBW(HORPIXPAN, ((startadd & 0x00000003) << 1));
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H A D | nv_proto.h | 81 status_t nv_crtc_set_display_start(uint32 startadd,uint8 bpp); 101 status_t nv_crtc2_set_display_start(uint32 startadd,uint8 bpp);
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H A D | nv_crtc2.c | 738 status_t nv_crtc2_set_display_start(uint32 startadd,uint8 bpp) argument 744 LOG(2,("CRTC2: startadd: $%08x\n", startadd)); 767 NV_REG32(NV32_NV10FB2STADD32) = (startadd & 0xfffffffc); 770 ATB2W(HORPIXPAN, ((startadd & 0x00000003) << 1));
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/haiku-fatelf/src/add-ons/accelerants/nvidia_gpgpu/engine/ |
H A D | nv_proto.h | 65 status_t nv_crtc_set_display_start(uint32 startadd,uint8 bpp); 83 status_t nv_crtc2_set_display_start(uint32 startadd,uint8 bpp);
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H A D | nv_crtc.c | 636 status_t nv_crtc_set_display_start(uint32 startadd,uint8 bpp) argument 642 LOG(2,("CRTC: startadd: $%08x\n", startadd)); 665 NV_REG32(NV32_NV10FBSTADD32) = (startadd & 0xfffffffc); 668 ATBW(HORPIXPAN, ((startadd & 0x00000003) << 1));
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H A D | nv_crtc2.c | 634 status_t nv_crtc2_set_display_start(uint32 startadd,uint8 bpp) argument 640 LOG(2,("CRTC2: startadd: $%08x\n", startadd)); 663 NV_REG32(NV32_NV10FB2STADD32) = (startadd & 0xfffffffc); 666 ATB2W(HORPIXPAN, ((startadd & 0x00000003) << 1));
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/haiku-fatelf/src/add-ons/accelerants/via/engine/ |
H A D | proto.h | 69 status_t eng_crtc_set_display_start(uint32 startadd,uint8 bpp); 89 status_t eng_crtc2_set_display_start(uint32 startadd,uint8 bpp);
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H A D | crtc.c | 591 status_t eng_crtc_set_display_start(uint32 startadd,uint8 bpp) argument 595 LOG(2,("CRTC: startadd: $%08x\n", startadd)); 603 CRTCW(FBSTADDL, ((startadd & 0x000001f8) >> 1)); 604 CRTCW(FBSTADDH, ((startadd & 0x0001fe00) >> 9)); 606 CRTCW(FBSTADDE, ((startadd & 0x01fe0000) >> 17));
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H A D | crtc2.c | 583 status_t eng_crtc2_set_display_start(uint32 startadd,uint8 bpp) argument 589 LOG(2,("CRTC2: startadd: $%08x\n", startadd)); 612 ENG_REG32(RG32_NV10FB2STADD32) = (startadd & 0xfffffffc); 615 ATB2W(HORPIXPAN, ((startadd & 0x00000003) << 1));
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