1/* CTRC functionality */ 2/* Author: 3 Rudolf Cornelissen 11/2002-6/2008 4*/ 5 6#define MODULE_BIT 0x00040000 7 8#include "nv_std.h" 9 10/* 11 Enable/Disable interrupts. Just a wrapper around the 12 ioctl() to the kernel driver. 13*/ 14status_t nv_crtc_interrupt_enable(bool flag) 15{ 16 status_t result = B_OK; 17 nv_set_vblank_int svi; 18 19 if (si->ps.int_assigned) 20 { 21 /* set the magic number so the driver knows we're for real */ 22 svi.magic = NV_PRIVATE_DATA_MAGIC; 23 svi.crtc = 0; 24 svi.do_it = flag; 25 /* contact driver and get a pointer to the registers and shared data */ 26 result = ioctl(fd, NV_RUN_INTERRUPTS, &svi, sizeof(svi)); 27 } 28 29 return result; 30} 31 32status_t nv_crtc_update_fifo() 33{ 34 return B_OK; 35} 36 37/* Adjust passed parameters to a valid mode line */ 38status_t nv_crtc_validate_timing( 39 uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht, 40 uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt 41) 42{ 43/* horizontal */ 44 /* make all parameters multiples of 8 */ 45 *hd_e &= 0xfff8; 46 *hs_s &= 0xfff8; 47 *hs_e &= 0xfff8; 48 *ht &= 0xfff8; 49 50 /* confine to required number of bits, taking logic into account */ 51 if (*hd_e > ((0x01ff - 2) << 3)) *hd_e = ((0x01ff - 2) << 3); 52 if (*hs_s > ((0x01ff - 1) << 3)) *hs_s = ((0x01ff - 1) << 3); 53 if (*hs_e > ( 0x01ff << 3)) *hs_e = ( 0x01ff << 3); 54 if (*ht > ((0x01ff + 5) << 3)) *ht = ((0x01ff + 5) << 3); 55 56 /* NOTE: keep horizontal timing at multiples of 8! */ 57 /* confine to a reasonable width */ 58 if (*hd_e < 640) *hd_e = 640; 59 if (*hd_e > 2048) *hd_e = 2048; 60 61 /* if hor. total does not leave room for a sensible sync pulse, increase it! */ 62 if (*ht < (*hd_e + 80)) *ht = (*hd_e + 80); 63 64 /* if hor. total does not adhere to max. blanking pulse width, decrease it! */ 65 if (*ht > (*hd_e + 0x3f8)) *ht = (*hd_e + 0x3f8); 66 67 /* make sure sync pulse is not during display */ 68 if (*hs_e > (*ht - 8)) *hs_e = (*ht - 8); 69 if (*hs_s < (*hd_e + 8)) *hs_s = (*hd_e + 8); 70 71 /* correct sync pulse if it is too long: 72 * there are only 5 bits available to save this in the card registers! */ 73 if (*hs_e > (*hs_s + 0xf8)) *hs_e = (*hs_s + 0xf8); 74 75/*vertical*/ 76 /* confine to required number of bits, taking logic into account */ 77 //fixme if needed: on GeForce cards there are 12 instead of 11 bits... 78 if (*vd_e > (0x7ff - 2)) *vd_e = (0x7ff - 2); 79 if (*vs_s > (0x7ff - 1)) *vs_s = (0x7ff - 1); 80 if (*vs_e > 0x7ff ) *vs_e = 0x7ff ; 81 if (*vt > (0x7ff + 2)) *vt = (0x7ff + 2); 82 83 /* confine to a reasonable height */ 84 if (*vd_e < 480) *vd_e = 480; 85 if (*vd_e > 1536) *vd_e = 1536; 86 87 /*if vertical total does not leave room for a sync pulse, increase it!*/ 88 if (*vt < (*vd_e + 3)) *vt = (*vd_e + 3); 89 90 /* if vert. total does not adhere to max. blanking pulse width, decrease it! */ 91 if (*vt > (*vd_e + 0xff)) *vt = (*vd_e + 0xff); 92 93 /* make sure sync pulse is not during display */ 94 if (*vs_e > (*vt - 1)) *vs_e = (*vt - 1); 95 if (*vs_s < (*vd_e + 1)) *vs_s = (*vd_e + 1); 96 97 /* correct sync pulse if it is too long: 98 * there are only 4 bits available to save this in the card registers! */ 99 if (*vs_e > (*vs_s + 0x0f)) *vs_e = (*vs_s + 0x0f); 100 101 return B_OK; 102} 103 104/*set a mode line - inputs are in pixels*/ 105status_t nv_crtc_set_timing(display_mode target) 106{ 107 uint8 temp; 108 109 uint32 htotal; /*total horizontal total VCLKs*/ 110 uint32 hdisp_e; /*end of horizontal display (begins at 0)*/ 111 uint32 hsync_s; /*begin of horizontal sync pulse*/ 112 uint32 hsync_e; /*end of horizontal sync pulse*/ 113 uint32 hblnk_s; /*begin horizontal blanking*/ 114 uint32 hblnk_e; /*end horizontal blanking*/ 115 116 uint32 vtotal; /*total vertical total scanlines*/ 117 uint32 vdisp_e; /*end of vertical display*/ 118 uint32 vsync_s; /*begin of vertical sync pulse*/ 119 uint32 vsync_e; /*end of vertical sync pulse*/ 120 uint32 vblnk_s; /*begin vertical blanking*/ 121 uint32 vblnk_e; /*end vertical blanking*/ 122 123 uint32 linecomp; /*split screen and vdisp_e interrupt*/ 124 125 LOG(4,("CRTC: setting timing\n")); 126 127 /* setup tuned internal modeline for flatpanel if connected and active */ 128 /* notes: 129 * - the CRTC modeline must end earlier than the panel modeline to keep correct 130 * sync going; 131 * - if the CRTC modeline ends too soon, pixelnoise will occur in 8 (or so) pixel 132 * wide horizontal stripes. This can be observed earliest on fullscreen overlay, 133 * and if it gets worse, also normal desktop output will suffer. The stripes 134 * are mainly visible at the left of the screen, over the entire screen height. */ 135 if (si->ps.tmds1_active) 136 { 137 LOG(2,("CRTC: DFP active: tuning modeline\n")); 138 139 /* horizontal timing */ 140 target.timing.h_sync_start = 141 ((uint16)((si->ps.p1_timing.h_sync_start / ((float)si->ps.p1_timing.h_display)) * 142 target.timing.h_display)) & 0xfff8; 143 144 target.timing.h_sync_end = 145 ((uint16)((si->ps.p1_timing.h_sync_end / ((float)si->ps.p1_timing.h_display)) * 146 target.timing.h_display)) & 0xfff8; 147 148 target.timing.h_total = 149 (((uint16)((si->ps.p1_timing.h_total / ((float)si->ps.p1_timing.h_display)) * 150 target.timing.h_display)) & 0xfff8) - 8; 151 152 /* in native mode the CRTC needs some extra time to keep synced correctly; 153 * OTOH the overlay unit distorts if we reserve too much time! */ 154 if (target.timing.h_display == si->ps.p1_timing.h_display) 155 { 156 /* confirmed NV34 with 1680x1050 panel */ 157 target.timing.h_total -= 32; 158 } 159 160 if (target.timing.h_sync_start == target.timing.h_display) 161 target.timing.h_sync_start += 8; 162 if (target.timing.h_sync_end == target.timing.h_total) 163 target.timing.h_sync_end -= 8; 164 165 /* vertical timing */ 166 target.timing.v_sync_start = 167 ((uint16)((si->ps.p1_timing.v_sync_start / ((float)si->ps.p1_timing.v_display)) * 168 target.timing.v_display)); 169 170 target.timing.v_sync_end = 171 ((uint16)((si->ps.p1_timing.v_sync_end / ((float)si->ps.p1_timing.v_display)) * 172 target.timing.v_display)); 173 174 target.timing.v_total = 175 ((uint16)((si->ps.p1_timing.v_total / ((float)si->ps.p1_timing.v_display)) * 176 target.timing.v_display)) - 1; 177 178 if (target.timing.v_sync_start == target.timing.v_display) 179 target.timing.v_sync_start += 1; 180 if (target.timing.v_sync_end == target.timing.v_total) 181 target.timing.v_sync_end -= 1; 182 183 /* disable GPU scaling testmode so automatic scaling will be done */ 184 DACW(FP_DEBUG1, 0); 185 } 186 187 /* Modify parameters as required by standard VGA */ 188 htotal = ((target.timing.h_total >> 3) - 5); 189 hdisp_e = ((target.timing.h_display >> 3) - 1); 190 hblnk_s = hdisp_e; 191 hblnk_e = (htotal + 4); 192 hsync_s = (target.timing.h_sync_start >> 3); 193 hsync_e = (target.timing.h_sync_end >> 3); 194 195 vtotal = target.timing.v_total - 2; 196 vdisp_e = target.timing.v_display - 1; 197 vblnk_s = vdisp_e; 198 vblnk_e = (vtotal + 1); 199 vsync_s = target.timing.v_sync_start; 200 vsync_e = target.timing.v_sync_end; 201 202 /* prevent memory adress counter from being reset (linecomp may not occur) */ 203 linecomp = target.timing.v_display; 204 205 /* enable access to primary head */ 206 set_crtc_owner(0); 207 208 /* Note for laptop and DVI flatpanels: 209 * CRTC timing has a seperate set of registers from flatpanel timing. 210 * The flatpanel timing registers have scaling registers that are used to match 211 * these two modelines. */ 212 { 213 LOG(4,("CRTC: Setting full timing...\n")); 214 215 /* log the mode that will be set */ 216 LOG(2,("CRTC:\n\tHTOT:%x\n\tHDISPEND:%x\n\tHBLNKS:%x\n\tHBLNKE:%x\n\tHSYNCS:%x\n\tHSYNCE:%x\n\t",htotal,hdisp_e,hblnk_s,hblnk_e,hsync_s,hsync_e)); 217 LOG(2,("VTOT:%x\n\tVDISPEND:%x\n\tVBLNKS:%x\n\tVBLNKE:%x\n\tVSYNCS:%x\n\tVSYNCE:%x\n",vtotal,vdisp_e,vblnk_s,vblnk_e,vsync_s,vsync_e)); 218 219 /* actually program the card! */ 220 /* unlock CRTC registers at index 0-7 */ 221 CRTCW(VSYNCE, (CRTCR(VSYNCE) & 0x7f)); 222 /* horizontal standard VGA regs */ 223 CRTCW(HTOTAL, (htotal & 0xff)); 224 CRTCW(HDISPE, (hdisp_e & 0xff)); 225 CRTCW(HBLANKS, (hblnk_s & 0xff)); 226 /* also unlock vertical retrace registers in advance */ 227 CRTCW(HBLANKE, ((hblnk_e & 0x1f) | 0x80)); 228 CRTCW(HSYNCS, (hsync_s & 0xff)); 229 CRTCW(HSYNCE, ((hsync_e & 0x1f) | ((hblnk_e & 0x20) << 2))); 230 231 /* vertical standard VGA regs */ 232 CRTCW(VTOTAL, (vtotal & 0xff)); 233 CRTCW(OVERFLOW, 234 ( 235 ((vtotal & 0x100) >> (8 - 0)) | ((vtotal & 0x200) >> (9 - 5)) | 236 ((vdisp_e & 0x100) >> (8 - 1)) | ((vdisp_e & 0x200) >> (9 - 6)) | 237 ((vsync_s & 0x100) >> (8 - 2)) | ((vsync_s & 0x200) >> (9 - 7)) | 238 ((vblnk_s & 0x100) >> (8 - 3)) | ((linecomp & 0x100) >> (8 - 4)) 239 )); 240 CRTCW(PRROWSCN, 0x00); /* not used */ 241 CRTCW(MAXSCLIN, (((vblnk_s & 0x200) >> (9 - 5)) | ((linecomp & 0x200) >> (9 - 6)))); 242 CRTCW(VSYNCS, (vsync_s & 0xff)); 243 CRTCW(VSYNCE, ((CRTCR(VSYNCE) & 0xf0) | (vsync_e & 0x0f))); 244 CRTCW(VDISPE, (vdisp_e & 0xff)); 245 CRTCW(VBLANKS, (vblnk_s & 0xff)); 246 CRTCW(VBLANKE, (vblnk_e & 0xff)); 247 CRTCW(LINECOMP, (linecomp & 0xff)); 248 249 /* horizontal extended regs */ 250 //fixme: we reset bit4. is this correct?? 251 CRTCW(HEB, (CRTCR(HEB) & 0xe0) | 252 ( 253 ((htotal & 0x100) >> (8 - 0)) | 254 ((hdisp_e & 0x100) >> (8 - 1)) | 255 ((hblnk_s & 0x100) >> (8 - 2)) | 256 ((hsync_s & 0x100) >> (8 - 3)) 257 )); 258 259 /* (mostly) vertical extended regs */ 260 CRTCW(LSR, 261 ( 262 ((vtotal & 0x400) >> (10 - 0)) | 263 ((vdisp_e & 0x400) >> (10 - 1)) | 264 ((vsync_s & 0x400) >> (10 - 2)) | 265 ((vblnk_s & 0x400) >> (10 - 3)) | 266 ((hblnk_e & 0x040) >> (6 - 4)) 267 //fixme: we still miss one linecomp bit!?! is this it?? 268 //| ((linecomp & 0x400) >> 3) 269 )); 270 271 /* more vertical extended regs */ 272 CRTCW(EXTRA, 273 ( 274 ((vtotal & 0x800) >> (11 - 0)) | 275 ((vdisp_e & 0x800) >> (11 - 2)) | 276 ((vsync_s & 0x800) >> (11 - 4)) | 277 ((vblnk_s & 0x800) >> (11 - 6)) 278 //fixme: do we miss another linecomp bit!?! 279 )); 280 281 /* setup 'large screen' mode */ 282 if (target.timing.h_display >= 1280) 283 CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0xfb)); 284 else 285 CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x04)); 286 287 /* setup HSYNC & VSYNC polarity */ 288 LOG(2,("CRTC: sync polarity: ")); 289 temp = NV_REG8(NV8_MISCR); 290 if (target.timing.flags & B_POSITIVE_HSYNC) 291 { 292 LOG(2,("H:pos ")); 293 temp &= ~0x40; 294 } 295 else 296 { 297 LOG(2,("H:neg ")); 298 temp |= 0x40; 299 } 300 if (target.timing.flags & B_POSITIVE_VSYNC) 301 { 302 LOG(2,("V:pos ")); 303 temp &= ~0x80; 304 } 305 else 306 { 307 LOG(2,("V:neg ")); 308 temp |= 0x80; 309 } 310 NV_REG8(NV8_MISCW) = temp; 311 312 LOG(2,(", MISC reg readback: $%02x\n", NV_REG8(NV8_MISCR))); 313 } 314 315 /* always disable interlaced operation */ 316 /* (interlace is supported on upto and including NV10, NV15, and NV30 and up) */ 317 CRTCW(INTERLACE, 0xff); 318 319 /* disable CRTC slaved mode unless a panel is in use */ 320 if (!si->ps.tmds1_active) CRTCW(PIXEL, (CRTCR(PIXEL) & 0x7f)); 321 322 /* setup flatpanel if connected and active */ 323 if (si->ps.tmds1_active) 324 { 325 uint32 iscale_x, iscale_y; 326 327 /* calculate inverse scaling factors used by hardware in 20.12 format */ 328 iscale_x = (((1 << 12) * target.timing.h_display) / si->ps.p1_timing.h_display); 329 iscale_y = (((1 << 12) * target.timing.v_display) / si->ps.p1_timing.v_display); 330 331 /* unblock flatpanel timing programming (or something like that..) */ 332 CRTCW(FP_HTIMING, 0); 333 CRTCW(FP_VTIMING, 0); 334 LOG(2,("CRTC: FP_HTIMING reg readback: $%02x\n", CRTCR(FP_HTIMING))); 335 LOG(2,("CRTC: FP_VTIMING reg readback: $%02x\n", CRTCR(FP_VTIMING))); 336 337 /* enable full width visibility on flatpanel */ 338 DACW(FP_HVALID_S, 0); 339 DACW(FP_HVALID_E, (si->ps.p1_timing.h_display - 1)); 340 /* enable full height visibility on flatpanel */ 341 DACW(FP_VVALID_S, 0); 342 DACW(FP_VVALID_E, (si->ps.p1_timing.v_display - 1)); 343 344 /* nVidia cards support upscaling except on ??? */ 345 /* NV11 cards can upscale after all! */ 346 if (0)//si->ps.card_type == NV11) 347 { 348 /* disable last fetched line limiting */ 349 DACW(FP_DEBUG2, 0x00000000); 350 /* inform panel to scale if needed */ 351 if ((iscale_x != (1 << 12)) || (iscale_y != (1 << 12))) 352 { 353 LOG(2,("CRTC: DFP needs to do scaling\n")); 354 DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) | 0x00000100)); 355 } 356 else 357 { 358 LOG(2,("CRTC: no scaling for DFP needed\n")); 359 DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) & 0xfffffeff)); 360 } 361 } 362 else 363 { 364 float dm_aspect; 365 366 LOG(2,("CRTC: GPU scales for DFP if needed\n")); 367 368 /* calculate display mode aspect */ 369 dm_aspect = (target.timing.h_display / ((float)target.timing.v_display)); 370 371 /* limit last fetched line if vertical scaling is done */ 372 if (iscale_y != (1 << 12)) 373 DACW(FP_DEBUG2, ((1 << 28) | ((target.timing.v_display - 1) << 16))); 374 else 375 DACW(FP_DEBUG2, 0x00000000); 376 377 /* inform panel not to scale */ 378 DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) & 0xfffffeff)); 379 380 /* GPU scaling is automatically setup by hardware, so only modify this 381 * scalingfactor for non 4:3 (1.33) aspect panels; 382 * let's consider 1280x1024 1:33 aspect (it's 1.25 aspect actually!) */ 383 384 /* correct for widescreen panels relative to mode... 385 * (so if panel is more widescreen than mode being set) */ 386 /* BTW: known widescreen panels: 387 * 1280 x 800 (1.60), 388 * 1440 x 900 (1.60), 389 * 1680 x 1050 (1.60), 390 * 1920 x 1200 (1.60). */ 391 /* known 4:3 aspect non-standard resolution panels: 392 * 1400 x 1050 (1.33). */ 393 /* NOTE: 394 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ 395 if ((iscale_x != (1 << 12)) && (si->ps.panel1_aspect > (dm_aspect + 0.10))) 396 { 397 uint16 diff; 398 399 LOG(2,("CRTC: (relative) widescreen panel: tuning horizontal scaling\n")); 400 401 /* X-scaling should be the same as Y-scaling */ 402 iscale_x = iscale_y; 403 /* enable testmode (b12) and program modified X-scaling factor */ 404 DACW(FP_DEBUG1, (((iscale_x >> 1) & 0x00000fff) | (1 << 12))); 405 /* center/cut-off left and right side of screen */ 406 diff = ((si->ps.p1_timing.h_display - 407 ((target.timing.h_display * (1 << 12)) / iscale_x)) 408 / 2); 409 DACW(FP_HVALID_S, diff); 410 DACW(FP_HVALID_E, ((si->ps.p1_timing.h_display - diff) - 1)); 411 } 412 /* correct for portrait panels... */ 413 /* NOTE: 414 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ 415 if ((iscale_y != (1 << 12)) && (si->ps.panel1_aspect < (dm_aspect - 0.10))) 416 { 417 LOG(2,("CRTC: (relative) portrait panel: should tune vertical scaling\n")); 418 /* fixme: implement if this kind of portrait panels exist on nVidia... */ 419 } 420 } 421 422 /* do some logging.. */ 423 LOG(2,("CRTC: FP_HVALID_S reg readback: $%08x\n", DACR(FP_HVALID_S))); 424 LOG(2,("CRTC: FP_HVALID_E reg readback: $%08x\n", DACR(FP_HVALID_E))); 425 LOG(2,("CRTC: FP_VVALID_S reg readback: $%08x\n", DACR(FP_VVALID_S))); 426 LOG(2,("CRTC: FP_VVALID_E reg readback: $%08x\n", DACR(FP_VVALID_E))); 427 LOG(2,("CRTC: FP_DEBUG0 reg readback: $%08x\n", DACR(FP_DEBUG0))); 428 LOG(2,("CRTC: FP_DEBUG1 reg readback: $%08x\n", DACR(FP_DEBUG1))); 429 LOG(2,("CRTC: FP_DEBUG2 reg readback: $%08x\n", DACR(FP_DEBUG2))); 430 LOG(2,("CRTC: FP_DEBUG3 reg readback: $%08x\n", DACR(FP_DEBUG3))); 431 LOG(2,("CRTC: FP_TG_CTRL reg readback: $%08x\n", DACR(FP_TG_CTRL))); 432 } 433 434 return B_OK; 435} 436 437status_t nv_crtc_depth(int mode) 438{ 439 uint8 viddelay = 0; 440 uint32 genctrl = 0; 441 442 /* set VCLK scaling */ 443 switch(mode) 444 { 445 case BPP8: 446 viddelay = 0x01; 447 /* genctrl b4 & b5 reset: 'direct mode' */ 448 genctrl = 0x00101100; 449 break; 450 case BPP15: 451 viddelay = 0x02; 452 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 453 genctrl = 0x00100130; 454 break; 455 case BPP16: 456 viddelay = 0x02; 457 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 458 genctrl = 0x00101130; 459 break; 460 case BPP24: 461 viddelay = 0x03; 462 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 463 genctrl = 0x00100130; 464 break; 465 case BPP32: 466 viddelay = 0x03; 467 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 468 genctrl = 0x00101130; 469 break; 470 } 471 /* enable access to primary head */ 472 set_crtc_owner(0); 473 474 CRTCW(PIXEL, ((CRTCR(PIXEL) & 0xfc) | viddelay)); 475 DACW(GENCTRL, genctrl); 476 477 return B_OK; 478} 479 480status_t nv_crtc_dpms(bool display, bool h, bool v, bool do_panel) 481{ 482 uint8 temp; 483 char msg[100]; 484 485 sprintf(msg, "CRTC: setting DPMS: "); 486 487 /* enable access to primary head */ 488 set_crtc_owner(0); 489 490 /* start synchronous reset: required before turning screen off! */ 491 SEQW(RESET, 0x01); 492 493 temp = SEQR(CLKMODE); 494 if (display) 495 { 496 /* turn screen on */ 497 SEQW(CLKMODE, (temp & ~0x20)); 498 499 /* end synchronous reset because display should be enabled */ 500 SEQW(RESET, 0x03); 501 502 if (do_panel && si->ps.tmds1_active) 503 { 504 if (!si->ps.laptop) 505 { 506 /* restore original panelsync and panel-enable */ 507 uint32 panelsync = 0x00000000; 508 if(si->ps.p1_timing.flags & B_POSITIVE_VSYNC) panelsync |= 0x00000001; 509 if(si->ps.p1_timing.flags & B_POSITIVE_HSYNC) panelsync |= 0x00000010; 510 /* display enable polarity (not an official flag) */ 511 if(si->ps.p1_timing.flags & B_BLANK_PEDESTAL) panelsync |= 0x10000000; 512 DACW(FP_TG_CTRL, ((DACR(FP_TG_CTRL) & 0xcfffffcc) | panelsync)); 513 514 //fixme?: looks like we don't need this after all: 515 /* powerup both LVDS (laptop panellink) and TMDS (DVI panellink) 516 * internal transmitters... */ 517 /* note: 518 * the powerbits in this register are hardwired to the DVI connectors, 519 * instead of to the DACs! (confirmed NV34) */ 520 //fixme... 521 //DACW(FP_DEBUG0, (DACR(FP_DEBUG0) & 0xcfffffff)); 522 /* ... and powerup external TMDS transmitter if it exists */ 523 /* (confirmed OK on NV28 and NV34) */ 524 //CRTCW(0x59, (CRTCR(0x59) | 0x01)); 525 526 sprintf(msg, "%s(panel-)", msg); 527 } 528 else 529 { 530 //fixme? linux only does this on dualhead cards... 531 //fixme: see if LVDS head can be determined with two panels there... 532 if (!si->ps.tmds2_active) 533 { 534 /* b2 = 0 = enable laptop panel backlight */ 535 /* note: this seems to be a write-only register. */ 536 NV_REG32(NV32_LVDS_PWR) = 0x00000003; 537 538 sprintf(msg, "%s(panel-)", msg); 539 } 540 } 541 } 542 543 sprintf(msg, "%sdisplay on, ", msg); 544 } 545 else 546 { 547 /* turn screen off */ 548 SEQW(CLKMODE, (temp | 0x20)); 549 550 if (do_panel && si->ps.tmds1_active) 551 { 552 if (!si->ps.laptop) 553 { 554 /* shutoff panelsync and disable panel */ 555 DACW(FP_TG_CTRL, ((DACR(FP_TG_CTRL) & 0xcfffffcc) | 0x20000022)); 556 557 //fixme?: looks like we don't need this after all: 558 /* powerdown both LVDS (laptop panellink) and TMDS (DVI panellink) 559 * internal transmitters... */ 560 /* note: 561 * the powerbits in this register are hardwired to the DVI connectors, 562 * instead of to the DACs! (confirmed NV34) */ 563 //fixme... 564 //DACW(FP_DEBUG0, (DACR(FP_DEBUG0) | 0x30000000)); 565 /* ... and powerdown external TMDS transmitter if it exists */ 566 /* (confirmed OK on NV28 and NV34) */ 567 //CRTCW(0x59, (CRTCR(0x59) & 0xfe)); 568 569 sprintf(msg, "%s(panel-)", msg); 570 } 571 else 572 { 573 //fixme? linux only does this on dualhead cards... 574 //fixme: see if LVDS head can be determined with two panels there... 575 if (!si->ps.tmds2_active) 576 { 577 /* b2 = 1 = disable laptop panel backlight */ 578 /* note: this seems to be a write-only register. */ 579 NV_REG32(NV32_LVDS_PWR) = 0x00000007; 580 581 sprintf(msg, "%s(panel-)", msg); 582 } 583 } 584 } 585 586 sprintf(msg, "%sdisplay off, ", msg); 587 } 588 589 if (h) 590 { 591 CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0x7f)); 592 sprintf(msg, "%shsync enabled, ", msg); 593 } 594 else 595 { 596 CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x80)); 597 sprintf(msg, "%shsync disabled, ", msg); 598 } 599 if (v) 600 { 601 CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0xbf)); 602 sprintf(msg, "%svsync enabled\n", msg); 603 } 604 else 605 { 606 CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x40)); 607 sprintf(msg, "%svsync disabled\n", msg); 608 } 609 610 LOG(4, (msg)); 611 612 return B_OK; 613} 614 615status_t nv_crtc_set_display_pitch() 616{ 617 uint32 offset; 618 619 LOG(4,("CRTC: setting card pitch (offset between lines)\n")); 620 621 /* figure out offset value hardware needs */ 622 offset = si->fbc.bytes_per_row / 8; 623 624 LOG(2,("CRTC: offset register set to: $%04x\n", offset)); 625 626 /* enable access to primary head */ 627 set_crtc_owner(0); 628 629 /* program the card */ 630 CRTCW(PITCHL, (offset & 0x00ff)); 631 CRTCW(REPAINT0, ((CRTCR(REPAINT0) & 0x1f) | ((offset & 0x0700) >> 3))); 632 633 return B_OK; 634} 635 636status_t nv_crtc_set_display_start(uint32 startadd,uint8 bpp) 637{ 638 uint32 timeout = 0; 639 640 LOG(4,("CRTC: setting card RAM to be displayed bpp %d\n", bpp)); 641 642 LOG(2,("CRTC: startadd: $%08x\n", startadd)); 643 LOG(2,("CRTC: frameRAM: $%08x\n", si->framebuffer)); 644 LOG(2,("CRTC: framebuffer: $%08x\n", si->fbc.frame_buffer)); 645 646 /* we might have no retraces during setmode! */ 647 /* wait 25mS max. for retrace to occur (refresh > 40Hz) */ 648 while (((NV_REG32(NV32_RASTER) & 0x000007ff) < si->dm.timing.v_display) && 649 (timeout < (25000/10))) 650 { 651 /* don't snooze much longer or retrace might get missed! */ 652 snooze(10); 653 timeout++; 654 } 655 656 /* enable access to primary head */ 657 set_crtc_owner(0); 658 659 /* upto 4Gb RAM adressing: must be used on NV10 and later! */ 660 /* NOTE: 661 * While this register also exists on pre-NV10 cards, it will 662 * wrap-around at 16Mb boundaries!! */ 663 664 /* 30bit adress in 32bit words */ 665 NV_REG32(NV32_NV10FBSTADD32) = (startadd & 0xfffffffc); 666 667 /* set NV4/NV10 byte adress: (b0 - 1) */ 668 ATBW(HORPIXPAN, ((startadd & 0x00000003) << 1)); 669 670 return B_OK; 671} 672 673status_t nv_crtc_cursor_init() 674{ 675 int i; 676 vuint32 * fb; 677 /* cursor bitmap will be stored at the start of the framebuffer */ 678 const uint32 curadd = 0; 679 680 /* enable access to primary head */ 681 set_crtc_owner(0); 682 683 /* set cursor bitmap adress ... */ 684 if (si->ps.laptop) 685 { 686 /* must be used this way on all 'Go' cards! */ 687 688 /* cursorbitmap must start on 2Kbyte boundary: */ 689 /* set adress bit11-16, and set 'no doublescan' (registerbit 1 = 0) */ 690 CRTCW(CURCTL0, ((curadd & 0x0001f800) >> 9)); 691 /* set adress bit17-23, and set graphics mode cursor(?) (registerbit 7 = 1) */ 692 CRTCW(CURCTL1, (((curadd & 0x00fe0000) >> 17) | 0x80)); 693 /* set adress bit24-31 */ 694 CRTCW(CURCTL2, ((curadd & 0xff000000) >> 24)); 695 } 696 else 697 { 698 /* upto 4Gb RAM adressing: 699 * can be used on NV10 and later (except for 'Go' cards)! */ 700 /* NOTE: 701 * This register does not exist on pre-NV10 and 'Go' cards. */ 702 703 /* cursorbitmap must still start on 2Kbyte boundary: */ 704 NV_REG32(NV32_NV10CURADD32) = (curadd & 0xfffff800); 705 } 706 707 /* set cursor colour: not needed because of direct nature of cursor bitmap. */ 708 709 /*clear cursor*/ 710 fb = (vuint32 *) si->framebuffer + curadd; 711 for (i=0;i<(2048/4);i++) 712 { 713 fb[i]=0; 714 } 715 716 /* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */ 717 NV_REG32(NV32_CURCONF) = 0x02000100; 718 719 /* activate hardware-sync between cursor updates and vertical retrace */ 720 DACW(NV10_CURSYNC, (DACR(NV10_CURSYNC) | 0x02000000)); 721 722 /* activate hardware cursor */ 723 nv_crtc_cursor_show(); 724 725 return B_OK; 726} 727 728status_t nv_crtc_cursor_show() 729{ 730 LOG(4,("CRTC: enabling cursor\n")); 731 732 /* enable access to CRTC1 on dualhead cards */ 733 set_crtc_owner(0); 734 735 /* b0 = 1 enables cursor */ 736 CRTCW(CURCTL0, (CRTCR(CURCTL0) | 0x01)); 737 738 /* workaround for hardware bug confirmed existing on NV43: 739 * Cursor visibility is not updated without a position update if its hardware 740 * retrace sync is enabled. */ 741 if (si->ps.card_arch == NV40A) DACW(CURPOS, (DACR(CURPOS))); 742 743 return B_OK; 744} 745 746status_t nv_crtc_cursor_hide() 747{ 748 LOG(4,("CRTC: disabling cursor\n")); 749 750 /* enable access to primary head */ 751 set_crtc_owner(0); 752 753 /* b0 = 0 disables cursor */ 754 CRTCW(CURCTL0, (CRTCR(CURCTL0) & 0xfe)); 755 756 /* workaround for hardware bug confirmed existing on NV43: 757 * Cursor visibility is not updated without a position update if its hardware 758 * retrace sync is enabled. */ 759 if (si->ps.card_arch == NV40A) DACW(CURPOS, (DACR(CURPOS))); 760 761 return B_OK; 762} 763 764/*set up cursor shape*/ 765status_t nv_crtc_cursor_define(uint8* andMask,uint8* xorMask) 766{ 767 int x, y; 768 uint8 b; 769 vuint16 *cursor; 770 uint16 pixel; 771 772 /* get a pointer to the cursor */ 773 cursor = (vuint16*) si->framebuffer; 774 775 /* draw the cursor */ 776 /* (Nvidia cards have a RGB15 direct color cursor bitmap, bit #16 is transparancy) */ 777 for (y = 0; y < 16; y++) 778 { 779 b = 0x80; 780 for (x = 0; x < 8; x++) 781 { 782 /* preset transparant */ 783 pixel = 0x0000; 784 /* set white if requested */ 785 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; 786 /* set black if requested */ 787 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; 788 /* set invert if requested */ 789 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; 790 /* place the pixel in the bitmap */ 791 cursor[x + (y * 32)] = pixel; 792 b >>= 1; 793 } 794 xorMask++; 795 andMask++; 796 b = 0x80; 797 for (; x < 16; x++) 798 { 799 /* preset transparant */ 800 pixel = 0x0000; 801 /* set white if requested */ 802 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; 803 /* set black if requested */ 804 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; 805 /* set invert if requested */ 806 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; 807 /* place the pixel in the bitmap */ 808 cursor[x + (y * 32)] = pixel; 809 b >>= 1; 810 } 811 xorMask++; 812 andMask++; 813 } 814 815 return B_OK; 816} 817 818/* position the cursor */ 819status_t nv_crtc_cursor_position(uint16 x, uint16 y) 820{ 821 /* the cursor position is updated during retrace by card hardware */ 822 /* update cursorposition */ 823 DACW(CURPOS, ((x & 0x0fff) | ((y & 0x0fff) << 16))); 824 825 return B_OK; 826} 827