Searched refs:CRTCW (Results 1 - 13 of 13) sorted by relevance
| /haiku/src/add-ons/accelerants/skeleton/engine/ |
| H A D | crtc.c | 212 CRTCW(VSYNCE, (CRTCR(VSYNCE) & 0x7f));
214 CRTCW(HTOTAL, (htotal & 0xff));
215 CRTCW(HDISPE, (hdisp_e & 0xff));
216 CRTCW(HBLANKS, (hblnk_s & 0xff));
218 CRTCW(HBLANKE, ((hblnk_e & 0x1f) | 0x80));
219 CRTCW(HSYNCS, (hsync_s & 0xff));
220 CRTCW(HSYNCE, ((hsync_e & 0x1f) | ((hblnk_e & 0x20) << 2)));
223 CRTCW(VTOTAL, (vtotal & 0xff));
224 CRTCW(OVERFLOW,
231 CRTCW(PRROWSC
[all...] |
| H A D | general.c | 278 CRTCW(OWNER, 0xff);
280 CRTCW(OWNER, 0x00);
440 // CRTCW(LOCK, 0x57);
441 // CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f));
487 // CRTCW(BUFFER, 0xff);
490 // CRTCW(BUFFER, 0xfb);
492 // CRTCW(MODECTL, 0xc3);
505 // CRTCW(REPAINT1, 0x04);
|
| H A D | info.c | 249 CRTCW(LOCK, 0x57);
250 CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f));
254 CRTCW(RMA, 0x00);
327 CRTCW(LOCK, 0x57);
328 CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f));
332 CRTCW(RMA, 0x00);
1974 CRTCW(FIFO, 0x03);
1977 CRTCW(FIFO_LWM, 0x20);
2100 CRTCW(LOCK, 0x57);
2101 CRTCW(VSYNC
[all...] |
| /haiku/src/add-ons/accelerants/nvidia/engine/ |
| H A D | nv_crtc.c | 72 CRTCW(FIFO, 0x03);
73 CRTCW(FIFO_LWM, 0x20);
81 CRTCW(FIFO, 0x01);
83 CRTCW(FIFO_LWM, 0x40);
91 CRTCW(FIFO, 0x02);
93 CRTCW(FIFO_LWM, 0x40);
99 CRTCW(FIFO, 0x03);
100 CRTCW(FIFO_LWM, 0x20);
338 CRTCW(VSYNCE, (CRTCR(VSYNCE) & 0x7f));
340 CRTCW(HTOTA
[all...] |
| H A D | nv_i2c.c | 81 CRTCW(WR_I2CBUS_0, (data | 0x20));
83 CRTCW(WR_I2CBUS_0, (data & ~0x20));
88 CRTCW(WR_I2CBUS_1, (data | 0x20));
90 CRTCW(WR_I2CBUS_1, (data & ~0x20));
95 CRTCW(WR_I2CBUS_2, (data | 0x20));
97 CRTCW(WR_I2CBUS_2, (data & ~0x20));
138 CRTCW(WR_I2CBUS_0, (data | 0x10));
140 CRTCW(WR_I2CBUS_0, (data & ~0x10));
145 CRTCW(WR_I2CBUS_1, (data | 0x10));
147 CRTCW(WR_I2CBUS_
[all...] |
| H A D | nv_general.c | 1560 CRTCW(OWNER, 0xff);
1562 CRTCW(OWNER, 0x00);
1730 CRTCW(LOCK, 0x57);
1731 CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f));
1786 CRTCW(BUFFER, 0xff);
1789 CRTCW(BUFFER, 0xfb);
1791 CRTCW(MODECTL, 0xc3);
1804 CRTCW(REPAINT1, 0x04);
|
| H A D | nv_info.c | 261 CRTCW(LOCK, 0x57);
262 CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f));
266 CRTCW(RMA, 0x00);
339 CRTCW(LOCK, 0x57);
340 CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f));
344 CRTCW(RMA, 0x00);
2105 CRTCW(FIFO, 0x03);
2108 CRTCW(FIFO_LWM, 0x20);
2238 CRTCW(LOCK, 0x57);
2239 CRTCW(VSYNC
[all...] |
| /haiku/src/add-ons/accelerants/via/engine/ |
| H A D | crtc.c | 200 CRTCW(VSYNCE, (CRTCR(VSYNCE) & 0x7f));
202 CRTCW(HTOTAL, (htotal & 0xff));
203 CRTCW(HDISPE, (hdisp_e & 0xff));
204 CRTCW(HBLANKS, (hblnk_s & 0xff));
206 CRTCW(HBLANKE, ((hblnk_e & 0x1f) | 0x80));
207 CRTCW(HSYNCS, (hsync_s & 0xff));
208 CRTCW(HSYNCE, ((hsync_e & 0x1f) | ((hblnk_e & 0x20) << 2)));
211 CRTCW(VTOTAL, (vtotal & 0xff));
212 CRTCW(OVERFLOW,
219 CRTCW(PRROWSC
[all...] |
| H A D | general.c | 302 CRTCW(OWNER, 0xff);
304 CRTCW(OWNER, 0x00);
456 CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f));
484 CRTCW(MODECTL, 0xc3);
|
| H A D | info.c | 67 CRTCW(FIFO, 0x03);
70 CRTCW(FIFO_LWM, 0x20);
162 CRTCW(LOCK, 0x57);
163 CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f));
|
| /haiku/headers/private/graphics/skeleton/ |
| H A D | macros.h | 768 #define CRTCW(A,B)(ENG_REG16(RG16_CRTCIND) = ((ENCRTCX_##A) | ((B) << 8))) macro
|
| /haiku/headers/private/graphics/via/ |
| H A D | macros.h | 837 #define CRTCW(A,B)(ENG_REG16(RG16_CRTCIND) = ((ENCRTCX_##A) | ((B) << 8))) macro
|
| /haiku/headers/private/graphics/nvidia/ |
| H A D | nv_macros.h | 915 #define CRTCW(A,B)(NV_REG16(NV16_CRTCIND) = ((NVCRTCX_##A) | ((B) << 8))) macro
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