Searched refs:CFGW (Results 1 - 11 of 11) sorted by relevance
| /haiku/src/add-ons/accelerants/matrox/engine/ |
| H A D | mga_dac.c | 1084 CFGW(OPTION, CFGR(OPTION) | 0x04);
1086 CFGW(OPTION, CFGR(OPTION) & 0xfffffffc);
1088 CFGW(OPTION, CFGR(OPTION) & 0xfffffffb);
1108 CFGW(OPTION, CFGR(OPTION) | 0x04);
1119 CFGW(OPTION, temp);
1121 CFGW(OPTION, (CFGR(OPTION) & 0xfffffffb) | 0x20);
1140 CFGW(OPTION, CFGR(OPTION) | 0x04);
1142 CFGW(OPTION, CFGR(OPTION) & 0xfffffffc);
1144 CFGW(OPTION, CFGR(OPTION) & 0xfffffffb);
1164 CFGW(OPTIO
[all...] |
| H A D | mga_general.c | 325 CFGW(OPTION,CFGR(OPTION)|0x20);
360 CFGW(OPTION,(CFGR(OPTION)&0xFFFF8FFF) | ((si->ps.v3_mem_type & 0x04) << 10));
365 CFGW(OPTION2,(CFGR(OPTION2)&0xFFFFCFFF)|((si->ps.v3_mem_type & 0x01) << 12));
367 CFGW(OPTION2,(CFGR(OPTION2)&0xFFFFFFF0) | ((si->ps.v3_mem_type & 0xf0) >> 4));
379 CFGW(OPTION,(CFGR(OPTION)&0xffe07fff) | (si->ps.option_reg & 0x001f8000));
385 CFGW(OPTION,(CFGR(OPTION)|(1<<22)|(0<<29)));
427 CFGW(OPTION,CFGR(OPTION)|0x20);
454 if (si->ps.sdram) CFGW(OPTION,(CFGR(OPTION) & 0xffffbfff));
462 CFGW(OPTION,(CFGR(OPTION)&0xFFFF83FF) | ((si->ps.v3_mem_type & 0x07) << 10));
463 if (!si->ps.sdram) CFGW(OPTIO
[all...] |
| H A D | tvp3026.c | 191 CFGW(DEVCTRL,(2|CFGR(DEVCTRL))); // enable device response (already enabled here!)
229 CFGW(OPTION, option | (nogscale << 21) | (rfhcnt << 16) | (memconfig << 12));
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| /haiku/src/add-ons/accelerants/nvidia/engine/ |
| H A D | nv_agp.c | 99 CFGW(AGPCMD, 0x00000000);
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| H A D | nv_info.c | 295 CFGW(ROMSHADOW, (CFGR(ROMSHADOW) |= 0x00000001));
401 CFGW(ROMSHADOW, (CFGR(ROMSHADOW) |= 0x00000001));
526 CFGW(ROMSHADOW, (CFGR(ROMSHADOW) & 0xfffffffe));
1472 CFGW(ROMSHADOW, (CFGR(ROMSHADOW) & 0xfffffffe));
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| /haiku/headers/private/graphics/matrox/ |
| H A D | mga_macros.h | 313 #define CFGW(A,B) (gx00_pci_access.offset=MGACFG_##A, gx00_pci_access.value = B, ioctl(fd,GX00_SET_PCI,&gx00_pci_access,sizeof(gx00_pci_access))) macro
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| /haiku/headers/private/graphics/neomagic/ |
| H A D | nm_macros.h | 312 #define CFGW(A,B) (nm_pci_access.offset=NMCFG_##A, nm_pci_access.value = B, ioctl(fd,NM_SET_PCI,&nm_pci_access,sizeof(nm_pci_access))) macro
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| /haiku/src/add-ons/accelerants/skeleton/engine/ |
| H A D | info.c | 283 CFGW(ROMSHADOW, (CFGR(ROMSHADOW) |= 0x00000001));
389 CFGW(ROMSHADOW, (CFGR(ROMSHADOW) |= 0x00000001));
514 CFGW(ROMSHADOW, (CFGR(ROMSHADOW) & 0xfffffffe));
1385 CFGW(ROMSHADOW, (CFGR(ROMSHADOW) & 0xfffffffe));
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| /haiku/headers/private/graphics/skeleton/ |
| H A D | macros.h | 747 #define CFGW(A,B) (eng_pci_access.offset=ENCFG_##A, eng_pci_access.value = B, ioctl(fd,ENG_SET_PCI,&eng_pci_access,sizeof(eng_pci_access))) macro
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| /haiku/headers/private/graphics/via/ |
| H A D | macros.h | 810 #define CFGW(A,B) (eng_pci_access.offset=ENCFG_##A, eng_pci_access.value = B, ioctl(fd,ENG_SET_PCI,&eng_pci_access,sizeof(eng_pci_access))) macro
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| /haiku/headers/private/graphics/nvidia/ |
| H A D | nv_macros.h | 894 #define CFGW(A,B) (nv_pci_access.offset=NVCFG_##A, nv_pci_access.value = B, ioctl(fd,NV_SET_PCI,&nv_pci_access,sizeof(nv_pci_access))) macro
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