Searched refs:readl (Results 1 - 25 of 38) sorted by relevance

12

/fuchsia/zircon/system/dev/lib/hi3660/
H A Dhi3660-dsi.c21 temp = readl(peri_crg + TXDPHY0_REF_OFFSET);
24 readl(peri_crg + TXDPHY0_REF_OFFSET + CLKGATE_SEPERATED_STATUS);
26 temp = readl(peri_crg + TXDPHY0_CFG_OFFSET);
29 readl(peri_crg + TXDPHY0_CFG_OFFSET + CLKGATE_SEPERATED_STATUS);
31 temp = readl(peri_crg + PCLK_GATE_DSI0_OFFSET);
34 readl(peri_crg + PCLK_GATE_DSI0_OFFSET + CLKGATE_SEPERATED_STATUS);
H A Dhi3660-usb.c24 temp = readl(pctrl + PCTRL_CTRL24);
35 temp = readl(usb3otg_bc + USB3OTG_CTRL0);
39 temp = readl(usb3otg_bc + USB3OTG_CTRL7);
44 temp = readl(usb3otg_bc + USB3OTG_CTRL2);
53 temp = readl(usb3otg_bc + USB3OTG_CTRL3);
H A Dhi3660-i2c.c24 temp = readl(iomcu + CLKGATE_SEPERATED_ENABLE);
27 readl(iomcu + CLKGATE_SEPERATED_STATUS); // need to read back status to ensure enable occurs
/fuchsia/zircon/system/dev/ethernet/intel-ethernet/
H A Die.c26 #define readl(a) (*REG32(eth->iobase + (a))) macro
33 readl(IE_STATUS), readl(IE_CTRL), readl(IE_CTRL_EXT), readl(IE_IMS));
35 readl(IE_RCTL), readl(IE_RDLEN), readl(IE_RDH), readl(IE_RDT));
37 readl(IE_RXDCT
[all...]
/fuchsia/zircon/system/dev/pci/amlogic-pcie/
H A Daml-pcie.cpp22 uint32_t val = readl(reg);
30 uint32_t val = readl(reg);
64 uint32_t val = readl(reg);
68 val = readl(reg);
79 val = readl(cfg);
83 val = readl(elb + PORT_LINK_CTRL_OFF);
87 val = readl(elb + PORT_LINK_CTRL_OFF);
91 val = readl(elb + PORT_LINK_CTRL_OFF);
95 val = readl(elb + GEN2_CTRL_OFF);
99 val = readl(el
[all...]
/fuchsia/zircon/system/dev/lib/amlogic/
H A Daml-usb-phy-v2.c64 uint32_t val = readl(reset_regs + 0x21 * 4);
69 writel(readl(reset_1) | S905D2_RESET1_USB, reset_1);
76 uint32_t temp = readl(addr);
88 writel(readl(reset_1) | (1 << (16 + 0 /*i is always zero here */)), reset_1);
94 temp = readl(addr);
97 temp = readl(addr);
/fuchsia/zircon/system/dev/block/imx-sdhci/
H A Dimx-sdhci.c153 SDHCI_ERROR(" ds_addr = 0x%x\n", readl(&dev->regs->ds_addr));
154 SDHCI_ERROR(" blk_att = 0x%x\n", readl(&dev->regs->blk_att));
155 SDHCI_ERROR(" cmd_arg = 0x%x\n", readl(&dev->regs->cmd_arg));
156 SDHCI_ERROR(" cmd_xfr_typ = 0x%x\n", readl(&dev->regs->cmd_xfr_typ));
157 SDHCI_ERROR(" cmd_rsp0 = 0x%x\n", readl(&dev->regs->cmd_rsp0));
158 SDHCI_ERROR(" cmd_rsp1 = 0x%x\n", readl(&dev->regs->cmd_rsp1));
159 SDHCI_ERROR(" cmd_rsp2 = 0x%x\n", readl(&dev->regs->cmd_rsp2));
160 SDHCI_ERROR(" cmd_rsp3 = 0x%x\n", readl(&dev->regs->cmd_rsp3));
161 SDHCI_ERROR(" data_buff_acc_port = 0x%x\n", readl(&dev->regs->data_buff_acc_port));
162 SDHCI_ERROR(" pres_state = 0x%x\n", readl(
[all...]
/fuchsia/zircon/system/dev/lib/amlogic/include/soc/aml-common/
H A Daml-gpu.h22 #define READ32_GPU_REG(offset) readl((uint32_t*)gpu->gpu_buffer.vaddr + offset)
25 #define READ32_HIU_REG(offset) readl((uint32_t*)gpu->hiu_buffer.vaddr + offset)
28 #define READ32_PRESET_REG(offset) readl((uint32_t*)gpu->preset_buffer.vaddr + offset)
/fuchsia/zircon/system/dev/board/gauss/
H A Dgauss-usb.c75 uint32_t temp = readl(addr);
84 temp = readl(addr);
92 uint32_t temp = readl(addr + USB_R1_OFFSET);
96 temp = readl(addr + USB_R5_OFFSET);
/fuchsia/zircon/system/dev/board/vim/
H A Dvim-usb.c76 uint32_t temp = readl(addr);
85 temp = readl(addr);
93 uint32_t temp = readl(addr + USB_R1_OFFSET);
97 temp = readl(addr + USB_R5_OFFSET);
/fuchsia/zircon/system/ulib/ddk/include/hw/
H A Dreg.h44 static inline uint32_t readl(const volatile void* a) { function
76 static inline uint32_t readl(const volatile void* a) { function
90 writel((readl(addr) & ~(((1 << (width)) - 1) << (startbit))) | ((val) << (startbit)), (addr))
100 #define set_bitsl(v, a) writel(readl(a) | (v), (a))
101 #define clr_bitsl(v, a) writel(readl(a) & ~(v), (a))
/fuchsia/zircon/bootloader/include/
H A Dreg.h19 #define readl(a) (*REG32(a)) macro
/fuchsia/zircon/kernel/dev/hdcp/amlogic_s912/
H A Dhdcp.c33 #define READ32_PRESET_REG(a) readl(preset_base + a)
36 #define READ32_HDMITX_REG(a) readl(hdmitx_base + a)
39 #define READ32_HHI_REG(a) readl(hiu_base + a)
/fuchsia/zircon/system/dev/display/vim-display/
H A Dhdmitx.h28 #define READ32_PRESET_REG(a) readl((uint8_t*)io_buffer_virt(&display->mmio_preset) + a)
31 #define READ32_HDMITX_REG(a) readl((uint8_t*)io_buffer_virt(&display->mmio_hdmitx) + a)
34 #define READ32_HHI_REG(a) readl((uint8_t*)io_buffer_virt(&display->mmio_hiu) + a)
37 #define READ32_VPU_REG(a) readl((uint8_t*)io_buffer_virt(&display->mmio_vpu) + a)
40 #define READ32_HDMITX_SEC_REG(a) readl((uint8_t*)io_buffer_virt(&display->mmio_hdmitx_sec) + a)
43 #define READ32_CBUS_REG(a) readl((uint8_t*)io_buffer_virt(&display->mmio_cbus) + 0x400 + a)
/fuchsia/zircon/system/dev/i2c/intel-i2c/
H A Dintel-i2c-controller.c381 uint32_t intr_stat = readl(&dev->regs->intr_stat);
383 intr_stat, readl(&dev->regs->raw_intr_stat));
387 readl(&dev->regs->clr_rx_under);
393 readl(&dev->regs->clr_rx_over);
405 readl(&dev->regs->clr_tx_over);
416 readl(&dev->regs->tx_abrt_source));
418 readl(&dev->regs->clr_tx_abort);
429 readl(&dev->regs->clr_stop_det);
432 readl(&dev->regs->clr_start_det);
528 *data = readl(
[all...]
H A Dintel-i2c-slave.c51 uint32_t i2c_sta = readl(&controller->regs->i2c_sta);
57 return (readl(&controller->regs->raw_intr_stat) &
62 return !(readl(&controller->regs->i2c_sta) & (0x1 << I2C_STA_RFNE));
134 if (!(readl(&controller->regs->i2c_sta) &
243 readl(&controller->regs->data_cmd), 0)) {
/fuchsia/zircon/kernel/dev/power/hisi/
H A Dpower.c27 uint32_t temp = readl(pmu + PMU_HRST_OFFSET);
/fuchsia/zircon/kernel/include/
H A Dreg.h26 #define readl(a) (*REG32(a)) macro
/fuchsia/zircon/system/dev/board/imx8mevk/
H A Dimx8mevk-usb.c122 reg = readl(regs + USB_PHY_CTRL1);
127 reg = readl(regs + USB_PHY_CTRL0);
131 reg = readl(regs + USB_PHY_CTRL2);
135 reg = readl(regs + USB_PHY_CTRL1);
/fuchsia/zircon/system/dev/audio/gauss-pdm-input/
H A Da113-audio-device.c52 return readl((uint32_t*)audio_device->pdm_mmio.vaddr + reg);
68 return readl((uint32_t*)audio_device->ee_audio_mmio.vaddr + reg);
/fuchsia/zircon/system/dev/pci/designware/
H A Ddw-pcie.cpp43 return readl(dbi + offset);
117 uint32_t val = readl(reg);
/fuchsia/zircon/system/dev/display/aml-canvas/
H A Daml-canvas.h24 #define READ32_DMC_REG(a) readl(canvas->dmc_regs.vaddr + a)
/fuchsia/zircon/system/dev/ethernet/realtek-8111/
H A Drtl8111.c25 #define readl(a) (*REG(edev->iobase + (a), 32)) macro
125 uint32_t tcr = readl(RTL_TCR) & ~(RTL_TCR_IFG_MASK | RTL_TCR_MXDMA_MASK);
137 uint32_t rcr = readl(RTL_RCR) & ~(RTL_RCR_MXDMA_MASK | RTL_RCR_ACCEPT_MASK);
143 uint32_t n = readl(RTL_MAC0);
145 n = readl(RTL_MAC1);
398 uint32_t mac_version = readl(RTL_TCR) & 0x7cf00000;
/fuchsia/zircon/system/dev/nand/aml-rawnand/
H A Daml-rawnand.h55 writel(((readl(_reg) & ~(((1L << (_len)) - 1) << (_start))) | ((uint32_t)((_value) & ((1L << (_len)) - 1)) << (_start))), _reg);
/fuchsia/zircon/system/dev/clk/hisi-lib/
H A Dhisi-clk.c71 readl(base + SEP_STATUS);
76 uint32_t val = readl(reg);

Completed in 252 milliseconds

12