Lines Matching refs:readl

153     SDHCI_ERROR("    ds_addr = 0x%x\n", readl(&dev->regs->ds_addr));
154 SDHCI_ERROR(" blk_att = 0x%x\n", readl(&dev->regs->blk_att));
155 SDHCI_ERROR(" cmd_arg = 0x%x\n", readl(&dev->regs->cmd_arg));
156 SDHCI_ERROR(" cmd_xfr_typ = 0x%x\n", readl(&dev->regs->cmd_xfr_typ));
157 SDHCI_ERROR(" cmd_rsp0 = 0x%x\n", readl(&dev->regs->cmd_rsp0));
158 SDHCI_ERROR(" cmd_rsp1 = 0x%x\n", readl(&dev->regs->cmd_rsp1));
159 SDHCI_ERROR(" cmd_rsp2 = 0x%x\n", readl(&dev->regs->cmd_rsp2));
160 SDHCI_ERROR(" cmd_rsp3 = 0x%x\n", readl(&dev->regs->cmd_rsp3));
161 SDHCI_ERROR(" data_buff_acc_port = 0x%x\n", readl(&dev->regs->data_buff_acc_port));
162 SDHCI_ERROR(" pres_state = 0x%x\n", readl(&dev->regs->pres_state));
163 SDHCI_ERROR(" prot_ctrl = 0x%x\n", readl(&dev->regs->prot_ctrl));
164 SDHCI_ERROR(" sys_ctrl = 0x%x\n", readl(&dev->regs->sys_ctrl));
165 SDHCI_ERROR(" int_status = 0x%x\n", readl(&dev->regs->int_status));
166 SDHCI_ERROR(" int_status_en = 0x%x\n", readl(&dev->regs->int_status_en));
167 SDHCI_ERROR(" int_signal_en = 0x%x\n", readl(&dev->regs->int_signal_en));
168 SDHCI_ERROR(" autocmd12_err_status = 0x%x\n", readl(&dev->regs->autocmd12_err_status));
169 SDHCI_ERROR(" host_ctrl_cap = 0x%x\n", readl(&dev->regs->host_ctrl_cap));
170 SDHCI_ERROR(" wtmk_lvl = 0x%x\n", readl(&dev->regs->wtmk_lvl));
171 SDHCI_ERROR(" mix_ctrl = 0x%x\n", readl(&dev->regs->mix_ctrl));
172 SDHCI_ERROR(" force_event = 0x%x\n", readl(&dev->regs->force_event));
173 SDHCI_ERROR(" adma_err_status = 0x%x\n", readl(&dev->regs->adma_err_status));
174 SDHCI_ERROR(" adma_sys_addr = 0x%x\n", readl(&dev->regs->adma_sys_addr));
175 SDHCI_ERROR(" dll_ctrl = 0x%x\n", readl(&dev->regs->dll_ctrl));
176 SDHCI_ERROR(" dll_status = 0x%x\n", readl(&dev->regs->dll_status));
177 SDHCI_ERROR(" clk_tune_ctrl_status = 0x%x\n", readl(&dev->regs->clk_tune_ctrl_status));
178 SDHCI_ERROR(" strobe_dll_ctrl = 0x%x\n", readl(&dev->regs->strobe_dll_ctrl));
179 SDHCI_ERROR(" strobe_dll_status = 0x%x\n", readl(&dev->regs->strobe_dll_status));
180 SDHCI_ERROR(" vend_spec = 0x%x\n", readl(&dev->regs->vend_spec));
181 SDHCI_ERROR(" mmc_boot = 0x%x\n", readl(&dev->regs->mmc_boot));
182 SDHCI_ERROR(" vend_spec2 = 0x%x\n", readl(&dev->regs->vend_spec2));
183 SDHCI_ERROR(" tuning_ctrl = 0x%x\n", readl(&dev->regs->tuning_ctrl));
282 if (!(readl(&dev->regs->sys_ctrl) & mask)) {
360 *wrd = readl(&dev->regs->data_buff_acc_port); //TODO: Can't read this if DMA is enabled!
626 while(readl(&regs->pres_state) & inhibit_mask) {
692 while((readl(&regs->int_status) & readl(&regs->int_status_en)) == 0) {
697 const uint32_t irq = readl(&regs->int_status);
699 readl(&regs->int_status), irq, readl(&regs->int_status_en), readl(&regs->int_signal_en),
711 readl(&regs->adma_err_status), readl(&regs->adma_sys_addr));
840 while (readl(&regs->pres_state) & (IMX_SDHC_PRES_STATE_CIHB | IMX_SDHC_PRES_STATE_CDIHB)) {
884 if(!(readl(&dev->regs->dll_status) & IMX_SDHC_DLLSTS_REF_LOCK)) {
887 if(!(readl(&dev->regs->dll_status) & IMX_SDHC_DLLSTS_SLV_LOCK)) {
905 uint32_t regVal = readl(&dev->regs->mix_ctrl);
959 SDHCI_ERROR("Did not recover from reset 0x%x\n", readl(&dev->regs->sys_ctrl));
976 uint32_t regVal = readl(&dev->regs->tuning_ctrl);
1042 .blocksize = (readl(&dev->regs->prot_ctrl) & IMX_SDHC_PROT_CTRL_DTW_8) ? 128 : 64,
1046 regVal = readl(&dev->regs->autocmd12_err_status);
1051 regVal = readl(&dev->regs->mix_ctrl);
1066 } while (((readl(&dev->regs->autocmd12_err_status) & IMX_SDHC_AUTOCMD12_ERRSTS_EXE_TUNING)) &&
1069 bool fail = (readl(&dev->regs->autocmd12_err_status) & IMX_SDHC_AUTOCMD12_ERRSTS_EXE_TUNING) ||
1070 !(readl(&dev->regs->autocmd12_err_status) & IMX_SDHC_AUTOCMD12_ERRSTS_SMP_CLK_SEL);
1172 uint32_t caps0 = readl(&dev->regs->host_ctrl_cap);