1// Copyright 2018 The Fuchsia Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5#pragma once
6
7#include <ddk/mmio-buffer.h>
8#include <ddk/protocol/gpio.h>
9#include <ddk/protocol/scpi.h>
10#include <ddk/debug.h>
11#include <ddk/device.h>
12#include <ddk/protocol/platform-bus.h>
13#include <ddk/protocol/platform-defs.h>
14#include <ddk/protocol/platform-device.h>
15#include <threads.h>
16
17#define GPU_ERROR(fmt, ...) zxlogf(ERROR, "[%s %d]" fmt, __func__, __LINE__, ##__VA_ARGS__)
18#define GPU_INFO(fmt, ...)  zxlogf(INFO, "[%s %d]" fmt, __func__, __LINE__, ##__VA_ARGS__)
19#define PWR_KEY         0x14
20#define PWR_OVERRIDE1   0x16
21
22#define READ32_GPU_REG(offset)          readl((uint32_t*)gpu->gpu_buffer.vaddr + offset)
23#define WRITE32_GPU_REG(offset, value)  writel(value, (uint32_t*)gpu->gpu_buffer.vaddr + offset)
24
25#define READ32_HIU_REG(offset)          readl((uint32_t*)gpu->hiu_buffer.vaddr + offset)
26#define WRITE32_HIU_REG(offset, value)  writel(value, (uint32_t*)gpu->hiu_buffer.vaddr + offset)
27
28#define READ32_PRESET_REG(offset)         readl((uint32_t*)gpu->preset_buffer.vaddr + offset)
29#define WRITE32_PRESET_REG(offset, value) writel(value, (uint32_t*)gpu->preset_buffer.vaddr + offset)
30
31#define CLK_ENABLED_BIT_SHIFT             8
32#define CALCULATE_CLOCK_MUX(enabled, base, divisor) \
33        ((!!(enabled) << CLK_ENABLED_BIT_SHIFT) | (base << 9) | (divisor - 1))
34
35#define CLOCK_MUX_MASK                  0xFFF
36
37#define MAX_GPU_CLK_FREQ                6
38#define FINAL_MUX_BIT_SHIFT             31
39
40enum {
41    MMIO_GPU,
42    MMIO_HIU,
43    MMIO_PRESET,
44};
45
46typedef struct {
47    uint32_t reset0_level_offset;
48    uint32_t reset0_mask_offset;
49    uint32_t reset2_level_offset;
50    uint32_t reset2_mask_offset;
51    uint32_t hhi_clock_cntl_offset;
52    uint32_t gpu_clk_freq[MAX_GPU_CLK_FREQ];
53}aml_gpu_block_t;
54
55typedef struct aml_hiu_dev aml_hiu_dev_t;
56typedef struct aml_pll_dev aml_pll_dev_t;
57
58typedef struct {
59    platform_device_protocol_t  pdev;
60
61    zx_device_t*                zxdev;
62
63    zx_handle_t                 bti;
64
65    mmio_buffer_t               hiu_buffer;
66    mmio_buffer_t               preset_buffer;
67    mmio_buffer_t               gpu_buffer;
68
69    aml_gpu_block_t*            gpu_block;
70    aml_hiu_dev_t*              hiu_dev;
71    aml_pll_dev_t*              gp0_pll_dev;
72} aml_gpu_t;
73