| /freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ResourcePriorityQueue.cpp | 95 && (TLI->getRegClassFor(VT)->getID() == RCId)) {
133 && (TLI->getRegClassFor(VT)->getID() == RCId)) {
328 && TLI->getRegClassFor(VT)
329 && TLI->getRegClassFor(VT)->getID() == RCId)
339 if (TLI->isTypeLegal(VT) && TLI->getRegClassFor(VT)
340 && TLI->getRegClassFor(VT)->getID() == RCId)
477 const TargetRegisterClass *RC = TLI->getRegClassFor(VT);
488 const TargetRegisterClass *RC = TLI->getRegClassFor(VT);
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| H A D | InstrEmitter.cpp | 107 UseRC = TLI->getRegClassFor(VT, Node->isDivergent());
212 const TargetRegisterClass *VTRC = TLI->getRegClassFor(
275 const TargetRegisterClass *RC = TLI->getRegClassFor(
392 ? TLI->getRegClassFor(OpVT,
465 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx);
500 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
571 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
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| H A D | FastISel.cpp | 321 Reg = createResultReg(TLI.getRegClassFor(VT));
793 CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64));
1528 const TargetRegisterClass *TyRegClass = TLI.getRegClassFor(Ty);
2190 Register ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
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| H A D | FunctionLoweringInfo.cpp | 365 return RegInfo->createVirtualRegister(TLI->getRegClassFor(VT, isDivergent));
|
| /freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | SwiftErrorValueTracking.cpp | 36 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
58 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
126 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
240 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
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| H A D | CallingConvLower.cpp | 253 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT);
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 394 Register MoveReg = createResultReg(TLI.getRegClassFor(VT));
404 Register MoveReg = createResultReg(TLI.getRegClassFor(VT));
430 Register DestReg = createResultReg(TLI.getRegClassFor(VT));
442 Register DestReg = createResultReg(TLI.getRegClassFor(VT));
502 ResultReg = createResultReg(TLI.getRegClassFor(VT));
591 Register NewDestReg = createResultReg(TLI.getRegClassFor(VT));
606 Register NewDestReg = createResultReg(TLI.getRegClassFor(VT));
657 const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
966 RC = TLI.getRegClassFor(VT);
978 RC = TLI.getRegClassFor(V
[all...] |
| H A D | ARMISelLowering.h | 578 /// getRegClassFor - Return the register class that should be used for the
581 getRegClassFor(MVT VT, bool isDivergent = false) const override;
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 464 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
2033 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
2193 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
2336 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
2363 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
2433 const TargetRegisterClass *RC = TLI.getRegClassFor(DstVT);
2492 return X86SelectFPExtOrFPTrunc(I, Opc, TLI.getRegClassFor(MVT::f64));
2506 return X86SelectFPExtOrFPTrunc(I, Opc, TLI.getRegClassFor(MVT::f32));
2608 const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::v8i16);
2646 ResultReg = createResultReg(TLI.getRegClassFor(MV
[all...] |
| H A D | X86ISelLoweringCall.cpp | 1650 TargLowering.getRegClassFor(FR.VT));
1842 MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
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| H A D | X86ISelDAGToDAG.cpp | 4913 unsigned RegClass = TLI->getRegClassFor(MaskVT)->getID();
4951 unsigned RegClass = TLI->getRegClassFor(ResVT)->getID();
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 1646 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1665 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1668 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1861 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1913 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1916 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
2544 Register Reg = MF.addLiveIn(RA, getRegClassFor(VT));
3692 const TargetRegisterClass *RC = getRegClassFor(RegVT);
3762 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32));
4100 RC = getRegClassFor(V
[all...] |
| H A D | MipsSEISelDAGToDAG.cpp | 1293 TLI->getRegClassFor(ViaVecTy.getSimpleVT());
1362 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
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| H A D | MipsFastISel.cpp | 1291 Register ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 514 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
1073 Register Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32));
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.h | 545 const TargetRegisterClass *getRegClassFor(MVT VT,
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 407 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm);
420 Register ResultReg = createResultReg(TLI.getRegClassFor(VT));
438 Register ResultReg = createResultReg(TLI.getRegClassFor(VT));
574 return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg);
2892 Register ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg);
3600 Register ResultReg = createResultReg(TLI.getRegClassFor(VT));
3759 ResultReg1 = createResultReg(TLI.getRegClassFor(VT));
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 1520 const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT);
1525 ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 712 const TargetRegisterClass *RC = getRegClassFor(MVT::i64);
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 999 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
1036 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
3401 auto *ARClass = getRegClassFor(SPTy);
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 1253 unsigned Reg = MF.addLiveIn(RI.getRARegister(), getRegClassFor(MVT::i32));
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 712 getRegClassFor(MVT::i16));
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 649 getRegClassFor(VA.getLocVT()));
2909 Register RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT));
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 842 const TargetRegisterClass *RC = getRegClassFor(RegVT);
1188 Register Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32));
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 630 getRegClassFor(GRLenVT));
3754 const TargetRegisterClass *RC = TLI.getRegClassFor(LocVT.getSimpleVT());
|