1//===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9/// \file 10/// SI DAG Lowering interface definition 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 15#define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 16 17#include "AMDGPUISelLowering.h" 18#include "AMDGPUArgumentUsageInfo.h" 19#include "llvm/CodeGen/MachineFunction.h" 20 21namespace llvm { 22 23class GCNSubtarget; 24class SIMachineFunctionInfo; 25class SIRegisterInfo; 26 27namespace AMDGPU { 28struct ImageDimIntrinsicInfo; 29} 30 31class SITargetLowering final : public AMDGPUTargetLowering { 32private: 33 const GCNSubtarget *Subtarget; 34 35public: 36 MVT getRegisterTypeForCallingConv(LLVMContext &Context, 37 CallingConv::ID CC, 38 EVT VT) const override; 39 unsigned getNumRegistersForCallingConv(LLVMContext &Context, 40 CallingConv::ID CC, 41 EVT VT) const override; 42 43 unsigned getVectorTypeBreakdownForCallingConv( 44 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, 45 unsigned &NumIntermediates, MVT &RegisterVT) const override; 46 47private: 48 SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL, 49 SDValue Chain, uint64_t Offset) const; 50 SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const; 51 SDValue getLDSKernelId(SelectionDAG &DAG, const SDLoc &SL) const; 52 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, 53 const SDLoc &SL, SDValue Chain, 54 uint64_t Offset, Align Alignment, 55 bool Signed, 56 const ISD::InputArg *Arg = nullptr) const; 57 SDValue loadImplicitKernelArgument(SelectionDAG &DAG, MVT VT, const SDLoc &DL, 58 Align Alignment, 59 ImplicitParameter Param) const; 60 61 SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA, 62 const SDLoc &SL, SDValue Chain, 63 const ISD::InputArg &Arg) const; 64 SDValue getPreloadedValue(SelectionDAG &DAG, 65 const SIMachineFunctionInfo &MFI, 66 EVT VT, 67 AMDGPUFunctionArgInfo::PreloadedValue) const; 68 69 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, 70 SelectionDAG &DAG) const override; 71 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op, 72 MVT VT, unsigned Offset) const; 73 SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr, 74 SelectionDAG &DAG, bool WithChain) const; 75 SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset, 76 SDValue CachePolicy, SelectionDAG &DAG) const; 77 78 SDValue lowerRawBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG, 79 unsigned NewOpcode) const; 80 SDValue lowerStructBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG, 81 unsigned NewOpcode) const; 82 83 SDValue lowerWaveID(SelectionDAG &DAG, SDValue Op) const; 84 SDValue lowerWorkitemID(SelectionDAG &DAG, SDValue Op, unsigned Dim, 85 const ArgDescriptor &ArgDesc) const; 86 87 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 88 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 89 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 90 91 // The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset 92 // (the offset that is included in bounds checking and swizzling, to be split 93 // between the instruction's voffset and immoffset fields) and soffset (the 94 // offset that is excluded from bounds checking and swizzling, to go in the 95 // instruction's soffset field). This function takes the first kind of 96 // offset and figures out how to split it between voffset and immoffset. 97 std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset, 98 SelectionDAG &DAG) const; 99 100 SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const; 101 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 102 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 103 SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const; 104 SDValue lowerFastUnsafeFDIV64(SDValue Op, SelectionDAG &DAG) const; 105 SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const; 106 SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const; 107 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const; 108 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const; 109 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const; 110 SDValue LowerFFREXP(SDValue Op, SelectionDAG &DAG) const; 111 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 112 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const; 113 SDValue lowerFSQRTF16(SDValue Op, SelectionDAG &DAG) const; 114 SDValue lowerFSQRTF32(SDValue Op, SelectionDAG &DAG) const; 115 SDValue lowerFSQRTF64(SDValue Op, SelectionDAG &DAG) const; 116 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 117 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 118 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 119 SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M, 120 SelectionDAG &DAG, ArrayRef<SDValue> Ops, 121 bool IsIntrinsic = false) const; 122 123 SDValue lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG, 124 ArrayRef<SDValue> Ops) const; 125 126 // Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to 127 // dwordx4 if on SI. 128 SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, 129 ArrayRef<SDValue> Ops, EVT MemVT, 130 MachineMemOperand *MMO, SelectionDAG &DAG) const; 131 132 SDValue handleD16VData(SDValue VData, SelectionDAG &DAG, 133 bool ImageStore = false) const; 134 135 /// Converts \p Op, which must be of floating point type, to the 136 /// floating point type \p VT, by either extending or truncating it. 137 SDValue getFPExtOrFPRound(SelectionDAG &DAG, 138 SDValue Op, 139 const SDLoc &DL, 140 EVT VT) const; 141 142 SDValue convertArgType( 143 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val, 144 bool Signed, const ISD::InputArg *Arg = nullptr) const; 145 146 /// Custom lowering for ISD::FP_ROUND for MVT::f16. 147 SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 148 SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const; 149 SDValue lowerFLDEXP(SDValue Op, SelectionDAG &DAG) const; 150 SDValue lowerMUL(SDValue Op, SelectionDAG &DAG) const; 151 SDValue lowerXMULO(SDValue Op, SelectionDAG &DAG) const; 152 SDValue lowerXMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 153 154 SDValue getSegmentAperture(unsigned AS, const SDLoc &DL, 155 SelectionDAG &DAG) const; 156 157 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const; 158 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 159 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 160 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 161 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 162 SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 163 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 164 165 SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const; 166 SDValue lowerTrapEndpgm(SDValue Op, SelectionDAG &DAG) const; 167 SDValue lowerTrapHsaQueuePtr(SDValue Op, SelectionDAG &DAG) const; 168 SDValue lowerTrapHsa(SDValue Op, SelectionDAG &DAG) const; 169 SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const; 170 171 SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const; 172 173 SDValue performUCharToFloatCombine(SDNode *N, 174 DAGCombinerInfo &DCI) const; 175 SDValue performFCopySignCombine(SDNode *N, DAGCombinerInfo &DCI) const; 176 177 SDValue performSHLPtrCombine(SDNode *N, 178 unsigned AS, 179 EVT MemVT, 180 DAGCombinerInfo &DCI) const; 181 182 SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const; 183 184 SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL, 185 unsigned Opc, SDValue LHS, 186 const ConstantSDNode *CRHS) const; 187 188 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const; 189 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const; 190 SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const; 191 SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const; 192 SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const; 193 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const; 194 SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT, 195 const APFloat &C) const; 196 SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const; 197 198 SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, 199 SDValue Op0, SDValue Op1) const; 200 SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, 201 SDValue Src, SDValue MinVal, SDValue MaxVal, 202 bool Signed) const; 203 SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const; 204 SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const; 205 SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const; 206 SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const; 207 SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const; 208 SDValue performFPRoundCombine(SDNode *N, DAGCombinerInfo &DCI) const; 209 210 SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const; 211 unsigned getFusedOpcode(const SelectionDAG &DAG, 212 const SDNode *N0, const SDNode *N1) const; 213 SDValue tryFoldToMad64_32(SDNode *N, DAGCombinerInfo &DCI) const; 214 SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; 215 SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const; 216 SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; 217 SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; 218 SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; 219 SDValue performFDivCombine(SDNode *N, DAGCombinerInfo &DCI) const; 220 SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const; 221 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const; 222 SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const; 223 SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const; 224 SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const; 225 226 bool isLegalFlatAddressingMode(const AddrMode &AM, unsigned AddrSpace, 227 uint64_t FlatVariant) const; 228 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const; 229 230 unsigned isCFIntrinsic(const SDNode *Intr) const; 231 232public: 233 /// \returns True if fixup needs to be emitted for given global value \p GV, 234 /// false otherwise. 235 bool shouldEmitFixup(const GlobalValue *GV) const; 236 237 /// \returns True if GOT relocation needs to be emitted for given global value 238 /// \p GV, false otherwise. 239 bool shouldEmitGOTReloc(const GlobalValue *GV) const; 240 241 /// \returns True if PC-relative relocation needs to be emitted for given 242 /// global value \p GV, false otherwise. 243 bool shouldEmitPCReloc(const GlobalValue *GV) const; 244 245 /// \returns true if this should use a literal constant for an LDS address, 246 /// and not emit a relocation for an LDS global. 247 bool shouldUseLDSConstAddress(const GlobalValue *GV) const; 248 249 /// Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be 250 /// expanded into a set of cmp/select instructions. 251 static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem, 252 bool IsDivergentIdx, 253 const GCNSubtarget *Subtarget); 254 255 bool shouldExpandVectorDynExt(SDNode *N) const; 256 257private: 258 // Analyze a combined offset from an amdgcn_buffer_ intrinsic and store the 259 // three offsets (voffset, soffset and instoffset) into the SDValue[3] array 260 // pointed to by Offsets. 261 void setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG, 262 SDValue *Offsets, Align Alignment = Align(4)) const; 263 264 // Convert the i128 that an addrspace(8) pointer is natively represented as 265 // into the v4i32 that all the buffer intrinsics expect to receive. We can't 266 // add register classes for i128 on pain of the promotion logic going haywire, 267 // so this slightly ugly hack is what we've got. If passed a non-pointer 268 // argument (as would be seen in older buffer intrinsics), does nothing. 269 SDValue bufferRsrcPtrToVector(SDValue MaybePointer, SelectionDAG &DAG) const; 270 271 // Wrap a 64-bit pointer into a v4i32 (which is how all SelectionDAG code 272 // represents ptr addrspace(8)) using the flags specified in the intrinsic. 273 SDValue lowerPointerAsRsrcIntrin(SDNode *Op, SelectionDAG &DAG) const; 274 275 // Handle 8 bit and 16 bit buffer loads 276 SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL, 277 ArrayRef<SDValue> Ops, 278 MachineMemOperand *MMO) const; 279 280 // Handle 8 bit and 16 bit buffer stores 281 SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType, 282 SDLoc DL, SDValue Ops[], 283 MemSDNode *M) const; 284 285public: 286 SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI); 287 288 const GCNSubtarget *getSubtarget() const; 289 290 bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, 291 EVT SrcVT) const override; 292 293 bool isFPExtFoldable(const MachineInstr &MI, unsigned Opcode, LLT DestTy, 294 LLT SrcTy) const override; 295 296 bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override; 297 298 // While address space 7 should never make it to codegen, it still needs to 299 // have a MVT to prevent some analyses that query this function from breaking, 300 // so, to work around the lack of i160, map it to v5i32. 301 MVT getPointerTy(const DataLayout &DL, unsigned AS) const override; 302 MVT getPointerMemTy(const DataLayout &DL, unsigned AS) const override; 303 304 bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, 305 MachineFunction &MF, 306 unsigned IntrinsicID) const override; 307 308 bool getAddrModeArguments(IntrinsicInst * /*I*/, 309 SmallVectorImpl<Value*> &/*Ops*/, 310 Type *&/*AccessTy*/) const override; 311 312 bool isLegalGlobalAddressingMode(const AddrMode &AM) const; 313 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 314 unsigned AS, 315 Instruction *I = nullptr) const override; 316 317 bool canMergeStoresTo(unsigned AS, EVT MemVT, 318 const MachineFunction &MF) const override; 319 320 bool allowsMisalignedMemoryAccessesImpl( 321 unsigned Size, unsigned AddrSpace, Align Alignment, 322 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 323 unsigned *IsFast = nullptr) const; 324 325 bool allowsMisalignedMemoryAccesses( 326 LLT Ty, unsigned AddrSpace, Align Alignment, 327 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 328 unsigned *IsFast = nullptr) const override { 329 if (IsFast) 330 *IsFast = 0; 331 return allowsMisalignedMemoryAccessesImpl(Ty.getSizeInBits(), AddrSpace, 332 Alignment, Flags, IsFast); 333 } 334 335 bool allowsMisalignedMemoryAccesses( 336 EVT VT, unsigned AS, Align Alignment, 337 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 338 unsigned *IsFast = nullptr) const override; 339 340 EVT getOptimalMemOpType(const MemOp &Op, 341 const AttributeList &FuncAttributes) const override; 342 343 bool isMemOpUniform(const SDNode *N) const; 344 bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const; 345 346 static bool isNonGlobalAddrSpace(unsigned AS); 347 348 bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 349 350 TargetLoweringBase::LegalizeTypeAction 351 getPreferredVectorAction(MVT VT) const override; 352 353 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 354 Type *Ty) const override; 355 356 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, 357 unsigned Index) const override; 358 359 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override; 360 361 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 362 363 unsigned combineRepeatedFPDivisors() const override { 364 // Combine multiple FDIVs with the same divisor into multiple FMULs by the 365 // reciprocal. 366 return 2; 367 } 368 369 bool supportSplitCSR(MachineFunction *MF) const override; 370 void initializeSplitCSR(MachineBasicBlock *Entry) const override; 371 void insertCopiesSplitCSR( 372 MachineBasicBlock *Entry, 373 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 374 375 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 376 bool isVarArg, 377 const SmallVectorImpl<ISD::InputArg> &Ins, 378 const SDLoc &DL, SelectionDAG &DAG, 379 SmallVectorImpl<SDValue> &InVals) const override; 380 381 bool CanLowerReturn(CallingConv::ID CallConv, 382 MachineFunction &MF, bool isVarArg, 383 const SmallVectorImpl<ISD::OutputArg> &Outs, 384 LLVMContext &Context) const override; 385 386 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 387 const SmallVectorImpl<ISD::OutputArg> &Outs, 388 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 389 SelectionDAG &DAG) const override; 390 391 void passSpecialInputs( 392 CallLoweringInfo &CLI, 393 CCState &CCInfo, 394 const SIMachineFunctionInfo &Info, 395 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass, 396 SmallVectorImpl<SDValue> &MemOpChains, 397 SDValue Chain) const; 398 399 SDValue LowerCallResult(SDValue Chain, SDValue InGlue, 400 CallingConv::ID CallConv, bool isVarArg, 401 const SmallVectorImpl<ISD::InputArg> &Ins, 402 const SDLoc &DL, SelectionDAG &DAG, 403 SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 404 SDValue ThisVal) const; 405 406 bool mayBeEmittedAsTailCall(const CallInst *) const override; 407 408 bool isEligibleForTailCallOptimization( 409 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, 410 const SmallVectorImpl<ISD::OutputArg> &Outs, 411 const SmallVectorImpl<SDValue> &OutVals, 412 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const; 413 414 SDValue LowerCall(CallLoweringInfo &CLI, 415 SmallVectorImpl<SDValue> &InVals) const override; 416 417 SDValue lowerDYNAMIC_STACKALLOCImpl(SDValue Op, SelectionDAG &DAG) const; 418 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 419 SDValue LowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const; 420 SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 421 422 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const; 423 SDValue lowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; 424 425 Register getRegisterByName(const char* RegName, LLT VT, 426 const MachineFunction &MF) const override; 427 428 MachineBasicBlock *splitKillBlock(MachineInstr &MI, 429 MachineBasicBlock *BB) const; 430 431 void bundleInstWithWaitcnt(MachineInstr &MI) const; 432 MachineBasicBlock *emitGWSMemViolTestLoop(MachineInstr &MI, 433 MachineBasicBlock *BB) const; 434 435 MachineBasicBlock * 436 EmitInstrWithCustomInserter(MachineInstr &MI, 437 MachineBasicBlock *BB) const override; 438 439 bool hasAtomicFaddRtnForTy(SDValue &Op) const; 440 bool enableAggressiveFMAFusion(EVT VT) const override; 441 bool enableAggressiveFMAFusion(LLT Ty) const override; 442 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 443 EVT VT) const override; 444 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override; 445 LLT getPreferredShiftAmountTy(LLT Ty) const override; 446 447 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 448 EVT VT) const override; 449 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 450 const LLT Ty) const override; 451 bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override; 452 bool isFMADLegal(const MachineInstr &MI, const LLT Ty) const override; 453 454 SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 455 SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 456 SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 457 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 458 459 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 460 SelectionDAG &DAG) const override; 461 462 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 463 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override; 464 void AddIMGInit(MachineInstr &MI) const; 465 void AdjustInstrPostInstrSelection(MachineInstr &MI, 466 SDNode *Node) const override; 467 468 SDNode *legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const; 469 470 MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, 471 SDValue Ptr) const; 472 MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, 473 uint32_t RsrcDword1, uint64_t RsrcDword2And3) const; 474 std::pair<unsigned, const TargetRegisterClass *> 475 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 476 StringRef Constraint, MVT VT) const override; 477 ConstraintType getConstraintType(StringRef Constraint) const override; 478 void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, 479 std::vector<SDValue> &Ops, 480 SelectionDAG &DAG) const override; 481 bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const; 482 bool checkAsmConstraintVal(SDValue Op, StringRef Constraint, 483 uint64_t Val) const; 484 bool checkAsmConstraintValA(SDValue Op, 485 uint64_t Val, 486 unsigned MaxSize = 64) const; 487 SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, 488 SDValue V) const; 489 490 void finalizeLowering(MachineFunction &MF) const override; 491 492 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, 493 const APInt &DemandedElts, 494 const SelectionDAG &DAG, 495 unsigned Depth = 0) const override; 496 void computeKnownBitsForFrameIndex(int FrameIdx, 497 KnownBits &Known, 498 const MachineFunction &MF) const override; 499 void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, Register R, 500 KnownBits &Known, 501 const APInt &DemandedElts, 502 const MachineRegisterInfo &MRI, 503 unsigned Depth = 0) const override; 504 505 Align computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R, 506 const MachineRegisterInfo &MRI, 507 unsigned Depth = 0) const override; 508 bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, 509 UniformityInfo *UA) const override; 510 511 bool hasMemSDNodeUser(SDNode *N) const; 512 513 bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, 514 SDValue N1) const override; 515 516 bool isReassocProfitable(MachineRegisterInfo &MRI, Register N0, 517 Register N1) const override; 518 519 bool isCanonicalized(SelectionDAG &DAG, SDValue Op, 520 unsigned MaxDepth = 5) const; 521 bool isCanonicalized(Register Reg, MachineFunction &MF, 522 unsigned MaxDepth = 5) const; 523 bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const; 524 bool denormalsEnabledForType(LLT Ty, MachineFunction &MF) const; 525 526 bool checkForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, 527 const TargetRegisterInfo *TRI, 528 const TargetInstrInfo *TII, unsigned &PhysReg, 529 int &Cost) const override; 530 531 bool isKnownNeverNaNForTargetNode(SDValue Op, 532 const SelectionDAG &DAG, 533 bool SNaN = false, 534 unsigned Depth = 0) const override; 535 AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override; 536 AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override; 537 AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override; 538 AtomicExpansionKind 539 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override; 540 void emitExpandAtomicRMW(AtomicRMWInst *AI) const override; 541 542 LoadInst * 543 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override; 544 545 const TargetRegisterClass *getRegClassFor(MVT VT, 546 bool isDivergent) const override; 547 bool requiresUniformRegister(MachineFunction &MF, 548 const Value *V) const override; 549 Align getPrefLoopAlignment(MachineLoop *ML) const override; 550 551 void allocateHSAUserSGPRs(CCState &CCInfo, 552 MachineFunction &MF, 553 const SIRegisterInfo &TRI, 554 SIMachineFunctionInfo &Info) const; 555 556 void allocatePreloadKernArgSGPRs(CCState &CCInfo, 557 SmallVectorImpl<CCValAssign> &ArgLocs, 558 const SmallVectorImpl<ISD::InputArg> &Ins, 559 MachineFunction &MF, 560 const SIRegisterInfo &TRI, 561 SIMachineFunctionInfo &Info) const; 562 563 void allocateLDSKernelId(CCState &CCInfo, MachineFunction &MF, 564 const SIRegisterInfo &TRI, 565 SIMachineFunctionInfo &Info) const; 566 567 void allocateSystemSGPRs(CCState &CCInfo, 568 MachineFunction &MF, 569 SIMachineFunctionInfo &Info, 570 CallingConv::ID CallConv, 571 bool IsShader) const; 572 573 void allocateSpecialEntryInputVGPRs(CCState &CCInfo, 574 MachineFunction &MF, 575 const SIRegisterInfo &TRI, 576 SIMachineFunctionInfo &Info) const; 577 void allocateSpecialInputSGPRs( 578 CCState &CCInfo, 579 MachineFunction &MF, 580 const SIRegisterInfo &TRI, 581 SIMachineFunctionInfo &Info) const; 582 583 void allocateSpecialInputVGPRs(CCState &CCInfo, 584 MachineFunction &MF, 585 const SIRegisterInfo &TRI, 586 SIMachineFunctionInfo &Info) const; 587 void allocateSpecialInputVGPRsFixed(CCState &CCInfo, 588 MachineFunction &MF, 589 const SIRegisterInfo &TRI, 590 SIMachineFunctionInfo &Info) const; 591 592 MachineMemOperand::Flags 593 getTargetMMOFlags(const Instruction &I) const override; 594}; 595 596// Returns true if argument is a boolean value which is not serialized into 597// memory or argument and does not require v_cndmask_b32 to be deserialized. 598bool isBoolSGPR(SDValue V); 599 600} // End namespace llvm 601 602#endif 603