Searched refs:csr (Results 1 - 25 of 56) sorted by relevance

123

/freebsd-current/sys/powerpc/booke/
H A Dmachdep_e500.c56 uint32_t csr; local
59 csr = mfspr(SPR_L1CSR0);
60 if ((csr & L1CSR0_DCE) == 0) {
65 csr = mfspr(SPR_L1CSR0);
66 if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR0_DCE) == 0)
68 (csr & L1CSR0_DCE) ? "en" : "dis");
71 csr = mfspr(SPR_L1CSR1);
72 if ((csr & L1CSR1_ICE) == 0) {
77 csr = mfspr(SPR_L1CSR1);
78 if ((boothowto & RB_VERBOSE) != 0 || (csr
86 uint32_t csr; local
117 uint32_t csr; local
[all...]
H A Dmp_cpudep.c53 uint32_t msr, csr; local
57 csr = mfspr(SPR_L1CSR0);
58 if ((csr & L1CSR0_DCE) == 0) {
63 csr = mfspr(SPR_L1CSR1);
64 if ((csr & L1CSR1_ICE) == 0) {
/freebsd-current/sys/dev/qat/qat_api/firmware/include/
H A Dicp_qat_hw_20_comp.h28 * Definition of the hw config csr. This representation has to be further
59 ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(icp_qat_hw_comp_20_config_csr_lower_t csr) argument
64 csr.algo,
69 csr.sd,
75 csr.edmm,
80 csr.hbs,
85 csr.mmctrl,
90 csr.hash_col,
95 csr.hash_update,
100 csr
150 ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER(icp_qat_hw_comp_20_config_csr_upper_t csr) argument
236 ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER( icp_qat_hw_decomp_20_config_csr_lower_t csr) argument
294 ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_UPPER( icp_qat_hw_decomp_20_config_csr_upper_t csr) argument
[all...]
/freebsd-current/sys/riscv/include/
H A Driscvreg.h191 #define csr_swap(csr, val) \
193 __asm __volatile("csrrwi %0, " #csr ", %1" \
196 __asm __volatile("csrrw %0, " #csr ", %1" \
201 #define csr_write(csr, val) \
203 __asm __volatile("csrwi " #csr ", %0" :: "i" (val)); \
205 __asm __volatile("csrw " #csr ", %0" :: "r" (val)); \
208 #define csr_set(csr, val) \
210 __asm __volatile("csrsi " #csr ", %0" :: "i" (val)); \
212 __asm __volatile("csrs " #csr ", %0" :: "r" (val)); \
215 #define csr_clear(csr, va
[all...]
/freebsd-current/sys/dev/qat/include/common/
H A Dicp_qat_hal.h144 #define CAP_CSR_ADDR(csr) (csr + handle->hal_cap_g_ctl_csr_addr_v)
145 #define SET_CAP_CSR(handle, csr, val) \
146 ADF_CSR_WR(handle->hal_misc_addr_v, CAP_CSR_ADDR(csr), val)
147 #define GET_CAP_CSR(handle, csr) \
148 ADF_CSR_RD(handle->hal_misc_addr_v, CAP_CSR_ADDR(csr))
149 #define SET_GLB_CSR(handle, csr, val) \
153 SET_CAP_CSR((handle), (csr), (val)) : \
154 SET_CAP_CSR((handle), (csr) + GLOBAL_CSR, val); \
156 #define GET_GLB_CSR(handle, csr) \
[all...]
/freebsd-current/sys/dev/qat/qat_hw/qat_200xx/
H A Dadf_200xx_hw_data.c178 adf_enable_error_interrupts(struct resource *csr) argument
180 ADF_CSR_WR(csr, ADF_ERRMSK0, ADF_200XX_ERRMSK0_CERR); /* ME0-ME3 */
181 ADF_CSR_WR(csr, ADF_ERRMSK1, ADF_200XX_ERRMSK1_CERR); /* ME4-ME5 */
182 ADF_CSR_WR(csr, ADF_ERRMSK5, ADF_200XX_ERRMSK5_CERR); /* SSM2 */
185 adf_csr_fetch_and_and(csr, ADF_ERRMSK3, ADF_200XX_VF2PF1_16);
188 ADF_CSR_WR(csr, ADF_200XX_RICPPINTCTL, ADF_200XX_RICPP_EN);
191 ADF_CSR_WR(csr, ADF_200XX_TICPPINTCTL, ADF_200XX_TICPP_EN);
194 ADF_CSR_WR(csr, ADF_200XX_CPP_CFC_ERR_CTRL, ADF_200XX_CPP_CFC_UE);
201 struct resource *csr = misc_bar->virt_addr; local
204 ADF_CSR_WR(csr,
221 struct resource *csr = misc_bar->virt_addr; local
232 adf_enable_mmp_error_correction(struct resource *csr, struct adf_hw_device_data *hw_data) argument
301 struct resource *csr = misc_bar->virt_addr; local
[all...]
/freebsd-current/sys/dev/qat/qat_common/
H A Dadf_hw_arbiter.c53 struct resource *csr = accel_dev->transport->banks[0].csr_addr; local
63 WRITE_CSR_ARB_SARCONFIG(csr, info.arbiter_offset, arb, arb_cfg);
73 struct resource *csr = accel_dev->transport->banks[0].csr_addr; local
88 WRITE_CSR_ARB_WRK_2_SER_MAP(csr,
162 struct resource *csr = csr_addr; local
169 arbenable = csr_ops->read_csr_ring_srv_arb_en(csr, bank_nr);
171 csr_ops->write_csr_ring_srv_arb_en(csr, bank_nr, arbenable);
181 struct resource *csr; local
187 csr = accel_dev->transport->banks[0].csr_addr;
193 WRITE_CSR_ARB_SARCONFIG(csr, inf
214 struct resource *csr; local
[all...]
H A Dadf_dev_err.c178 struct resource *csr = misc_bar->virt_addr; local
184 val = ADF_CSR_RD(csr, adf_err_regs[i].offs);
196 val = adf_accel_err_regs[i].read(csr, accel);
224 struct resource *csr,
227 u32 slice_hang = ADF_CSR_RD(csr, slice_hang_offset);
264 ADF_CSR_WR(csr, slice_hang_offset, slice_hang);
280 struct resource *csr = misc_bar->virt_addr; local
281 u32 errsou3 = ADF_CSR_RD(csr, ADF_ERRSOU3);
282 u32 errsou5 = ADF_CSR_RD(csr, ADF_ERRSOU5);
306 if (ADF_CSR_RD(csr, ADF_INTSTATSS
222 adf_handle_slice_hang(struct adf_accel_dev *accel_dev, u8 accel_num, struct resource *csr, u32 slice_hang_offset) argument
[all...]
H A Dadf_freebsd_transport_debug.c23 struct resource *csr = ring->bank->csr_addr; local
32 head = csr_ops->read_csr_ring_head(csr,
35 tail = csr_ops->read_csr_ring_tail(csr,
38 empty = csr_ops->read_csr_e_stat(csr, bank->bank_number);
139 struct resource *csr = bank->csr_addr; local
145 head = csr_ops->read_csr_ring_head(csr,
148 tail = csr_ops->read_csr_ring_tail(csr,
151 empty = csr_ops->read_csr_e_stat(csr, bank->bank_number);
H A Dadf_gen4_hw_data.c154 reset_ring_pair(struct resource *csr, u32 bank_number) argument
166 ADF_CSR_WR(csr,
172 val = ADF_CSR_RD(csr, ADF_WQM_CSR_RPRESETSTS(bank_number));
182 ADF_CSR_WR(csr,
193 struct resource *csr; local
199 csr = (&GET_BARS(accel_dev)[etr_bar_id])->virt_addr;
201 ret = reset_ring_pair(csr, bank_number);
H A Dqat_hal.c112 unsigned int csr,
118 *value = GET_AE_CSR(handle, ae, csr);
130 unsigned int csr,
136 SET_AE_CSR(handle, ae, csr, value);
166 unsigned int csr = (1 << ACS_ABO_BITPOS); local
174 qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS, &csr);
184 if (elapsed_cycles >= 8 && !(csr & (1 << ACS_ABO_BITPOS)))
208 unsigned int csr, new_csr; local
216 qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &csr);
217 csr
110 qat_hal_rd_ae_csr(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned int csr, unsigned int *value) argument
128 qat_hal_wr_ae_csr(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned int csr, unsigned int value) argument
229 unsigned int csr, new_csr; local
254 unsigned int csr, new_csr; local
290 unsigned int csr, new_csr; local
305 unsigned int csr, new_csr; local
[all...]
/freebsd-current/crypto/openssl/test/certs/
H A Dmkcert.sh113 csr=$(req "$key" "CN = $cn") || return 1
114 echo "$csr" |
154 csr=$(req "$key" "CN = $cn") || return 1
155 echo "$csr" |
175 csr=$(req "$key" "CN = $cn") || return 1
176 echo "$csr" |
183 # Note: takes csr on stdin, so must be used with $0 req like this:
222 # Note: takes csr on stdin, so must be used with $0 req like this:
264 csr=$(req "$key" "CN = $cn") || return 1
265 echo "$csr" |
[all...]
/freebsd-current/sys/dev/qat/qat_hw/qat_c4xxx/
H A Dadf_c4xxx_res_part.c64 struct resource *csr = accel_dev->transport->banks[0].csr_addr; local
73 WRITE_CSR_WQM(csr,
82 struct resource *csr = accel_dev->transport->banks[0].csr_addr; local
93 WRITE_CSR_WQM(csr,
102 struct resource *csr = accel_dev->transport->banks[0].csr_addr; local
111 WRITE_CSR_WQM(csr,
125 struct resource *csr = accel_dev->transport->banks[0].csr_addr; local
136 WRITE_CSR_WQM(csr,
170 struct resource *csr; local
176 csr
[all...]
H A Dadf_c4xxx_hw_data.c209 struct resource *csr = misc_bar->virt_addr; local
228 ADF_CSR_WR(csr, ADF_C4XXX_SSMWDTL_OFFSET(accel), ssm_wdt_low);
229 ADF_CSR_WR(csr, ADF_C4XXX_SSMWDTH_OFFSET(accel), ssm_wdt_high);
230 ADF_CSR_WR(csr,
233 ADF_CSR_WR(csr,
252 struct resource *csr = misc_bar->virt_addr; local
259 u32 errsou10 = ADF_CSR_RD(csr, ADF_C4XXX_ERRSOU10);
269 fw_irq_source = ADF_CSR_RD(csr, ADF_INTSTATSSM(accel_num));
271 ADF_CSR_RD(csr, ADF_C4XXX_IAINTSTATSSM(accel_num));
284 adf_csr_fetch_and_and(csr, slice_hang_offse
317 struct resource *csr = local
424 struct resource *csr; local
444 struct resource *csr; local
470 struct resource *csr, *aram_csr; local
559 adf_enable_mmp_error_correction(struct resource *csr, struct adf_hw_device_data *hw_data) argument
638 struct resource *csr = misc_bar->virt_addr; local
1959 struct resource *csr = local
[all...]
/freebsd-current/crypto/openssl/test/testutil/
H A Dload.c94 X509_REQ *csr = NULL; local
100 csr = X509_REQ_new_ex(libctx, NULL);
101 if (TEST_ptr(csr))
102 (void)TEST_ptr(d2i_X509_REQ_bio(bio, &csr));
104 return csr;
/freebsd-current/sys/dev/usb/controller/
H A Dmusb_otg.c403 uint8_t csr; local
421 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
423 DPRINTFN(4, "csr=0x%02x\n", csr);
429 if (csr & MUSB2_MASK_CSR0L_DATAEND) {
437 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) {
441 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
445 if (csr & MUSB2_MASK_CSR0L_SETUPEND) {
450 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
458 if (!(csr
529 uint8_t csr, csrh; local
638 uint8_t csr; local
779 uint8_t csr; local
895 uint8_t csr; local
1073 uint8_t csr, csrh; local
1243 uint8_t csr; local
1279 uint8_t csr, csrh; local
1365 uint8_t csr; local
1433 uint8_t csr; local
1581 uint8_t csr; local
1708 uint8_t csr, csrh; local
1930 uint8_t csr, csrh; local
2866 uint8_t csr; local
[all...]
/freebsd-current/sys/dev/mii/
H A Dlxtphy.c194 int bmcr, bmsr, csr; local
204 csr = PHY_READ(sc, MII_LXTPHY_CSR);
205 if (csr & CSR_LINK)
225 if (csr & CSR_SPEED)
229 if (csr & CSR_DUPLEX)
/freebsd-current/sys/dev/qat/qat_hw/qat_dh895xcc/
H A Dadf_dh895xcc_hw_data.c198 struct resource *csr = misc_bar->virt_addr; local
207 val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_CTX_ENABLES(i));
209 ADF_CSR_WR(csr, ADF_DH895XCC_AE_CTX_ENABLES(i), val);
210 val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_MISC_CONTROL(i));
212 ADF_CSR_WR(csr, ADF_DH895XCC_AE_MISC_CONTROL(i), val);
220 val = ADF_CSR_RD(csr, ADF_DH895XCC_UERRSSMSH(i));
222 ADF_CSR_WR(csr, ADF_DH895XCC_UERRSSMSH(i), val);
223 val = ADF_CSR_RD(csr, ADF_DH895XCC_CERRSSMSH(i));
225 ADF_CSR_WR(csr, ADF_DH895XCC_CERRSSMSH(i), val);
/freebsd-current/sys/dev/wpi/
H A Dif_wpi_debug.h101 static const char *wpi_get_csr_string(size_t csr) argument
103 switch (csr) {
120 KASSERT(0, ("Unknown CSR: %d\n", csr));
/freebsd-current/sys/powerpc/mpc85xx/
H A Dmpc85xx.c294 uint32_t csr, size, ver; local
300 csr = ccsr_read4(OCP85XX_CPC_CSR0);
301 if ((csr & OCP85XX_CPC_CSR0_CE) == 0) {
306 csr = ccsr_read4(OCP85XX_CPC_CSR0);
308 (csr & OCP85XX_CPC_CSR0_CE) == 0) {
311 size, (csr & OCP85XX_CPC_CSR0_CE) == 0 ?
/freebsd-current/sys/dev/iicbus/rtc/
H A Dnxprtc.c441 struct csr { struct
446 } csr; local
451 if ((err = nxprtc_readfrom(sc->dev, PCF85xx_R_CS1, &csr,
452 sizeof(csr), WAITFLAGS)) != 0){
463 if ((csr.cs3 & PCF8523_M_CS3_PM) == PCF8523_B_CS3_PM_NOBAT ||
464 (csr.cs1 & PCF85xx_B_CS1_STOP) || (csr.sec & PCF85xx_B_SECOND_OS)) {
529 if (csr.cs1 & PCF2129_B_CS1_12HR)
547 if (csr.cs1 & PCF8523_B_CS1_12HR)
615 struct csr { struct
619 } csr; local
[all...]
/freebsd-current/sys/dev/qat/qat_hw/qat_c62x/
H A Dadf_c62x_hw_data.c185 struct resource *csr = misc_bar->virt_addr; local
194 val = ADF_CSR_RD(csr, ADF_C62X_AE_CTX_ENABLES(i));
196 ADF_CSR_WR(csr, ADF_C62X_AE_CTX_ENABLES(i), val);
197 val = ADF_CSR_RD(csr, ADF_C62X_AE_MISC_CONTROL(i));
199 ADF_CSR_WR(csr, ADF_C62X_AE_MISC_CONTROL(i), val);
207 val = ADF_CSR_RD(csr, ADF_C62X_UERRSSMSH(i));
209 ADF_CSR_WR(csr, ADF_C62X_UERRSSMSH(i), val);
210 val = ADF_CSR_RD(csr, ADF_C62X_CERRSSMSH(i));
212 ADF_CSR_WR(csr, ADF_C62X_CERRSSMSH(i), val);
/freebsd-current/sys/dev/qat/qat_hw/qat_c3xxx/
H A Dadf_c3xxx_hw_data.c181 struct resource *csr = misc_bar->virt_addr; local
190 val = ADF_CSR_RD(csr, ADF_C3XXX_AE_CTX_ENABLES(i));
192 ADF_CSR_WR(csr, ADF_C3XXX_AE_CTX_ENABLES(i), val);
193 val = ADF_CSR_RD(csr, ADF_C3XXX_AE_MISC_CONTROL(i));
195 ADF_CSR_WR(csr, ADF_C3XXX_AE_MISC_CONTROL(i), val);
203 val = ADF_CSR_RD(csr, ADF_C3XXX_UERRSSMSH(i));
205 ADF_CSR_WR(csr, ADF_C3XXX_UERRSSMSH(i), val);
206 val = ADF_CSR_RD(csr, ADF_C3XXX_CERRSSMSH(i));
208 ADF_CSR_WR(csr, ADF_C3XXX_CERRSSMSH(i), val);
/freebsd-current/sys/arm/ti/
H A Dti_sdma.c217 uint32_t csr; local
236 csr = ti_sdma_read_4(sc, DMA4_CSR(ch));
237 if (csr == 0) {
251 if (csr & DMA4_CSR_DROP)
255 if (csr & DMA4_CSR_SECURE_ERR)
258 if (csr & DMA4_CSR_MISALIGNED_ADRS_ERR)
261 if (csr & DMA4_CSR_TRANS_ERR) {
278 channel->callback(ch, csr, channel->callback_data);
582 uint32_t csr; local
597 csr
[all...]
/freebsd-current/sys/dev/ppc/
H A Dppc.c704 int csr = SMC66x_CSR; /* initial value is 0x3F0 */ local
708 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */
714 outb(csr, SMC665_iCODE);
715 outb(csr, SMC665_iCODE);
718 outb(csr, 0xd);
726 outb(csr, SMC666_iCODE);
727 outb(csr, SMC666_iCODE);
730 outb(csr, 0xd);
737 csr = SMC666_CSR;
745 outb(csr,
[all...]

Completed in 276 milliseconds

123