1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2011-2012 Semihalf.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30
31#include <sys/types.h>
32#include <sys/param.h>
33#include <sys/proc.h>
34#include <sys/reboot.h>
35
36#include <vm/vm.h>
37#include <vm/pmap.h>
38
39#include <machine/machdep.h>
40
41#include <dev/fdt/fdt_common.h>
42
43#include <powerpc/mpc85xx/mpc85xx.h>
44
45extern void dcache_enable(void);
46extern void dcache_inval(void);
47extern void icache_enable(void);
48extern void icache_inval(void);
49extern void l2cache_enable(void);
50extern void l2cache_inval(void);
51extern void bpred_enable(void);
52
53void
54booke_enable_l1_cache(void)
55{
56	uint32_t csr;
57
58	/* Enable D-cache if applicable */
59	csr = mfspr(SPR_L1CSR0);
60	if ((csr & L1CSR0_DCE) == 0) {
61		dcache_inval();
62		dcache_enable();
63	}
64
65	csr = mfspr(SPR_L1CSR0);
66	if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR0_DCE) == 0)
67		printf("L1 D-cache %sabled\n",
68		    (csr & L1CSR0_DCE) ? "en" : "dis");
69
70	/* Enable L1 I-cache if applicable. */
71	csr = mfspr(SPR_L1CSR1);
72	if ((csr & L1CSR1_ICE) == 0) {
73		icache_inval();
74		icache_enable();
75	}
76
77	csr = mfspr(SPR_L1CSR1);
78	if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR1_ICE) == 0)
79		printf("L1 I-cache %sabled\n",
80		    (csr & L1CSR1_ICE) ? "en" : "dis");
81}
82
83void
84booke_enable_l2_cache(void)
85{
86	uint32_t csr;
87
88	/* Enable L2 cache on E500mc */
89	if ((((mfpvr() >> 16) & 0xFFFF) == FSL_E500mc) ||
90	    (((mfpvr() >> 16) & 0xFFFF) == FSL_E5500)) {
91		csr = mfspr(SPR_L2CSR0);
92		/*
93		 * Don't actually attempt to manipulate the L2 cache if
94		 * L2CFG0 is zero.
95		 *
96		 * Any chip with a working L2 cache will have a nonzero
97		 * L2CFG0, as it will have a nonzero L2CSIZE field.
98		 *
99		 * This fixes waiting forever for cache enable in qemu,
100		 * which does not implement the L2 cache.
101		 */
102		if (mfspr(SPR_L2CFG0) != 0 && (csr & L2CSR0_L2E) == 0) {
103			l2cache_inval();
104			l2cache_enable();
105		}
106
107		csr = mfspr(SPR_L2CSR0);
108		if ((boothowto & RB_VERBOSE) != 0 || (csr & L2CSR0_L2E) == 0)
109			printf("L2 cache %sabled\n",
110			    (csr & L2CSR0_L2E) ? "en" : "dis");
111	}
112}
113
114void
115booke_enable_bpred(void)
116{
117	uint32_t csr;
118
119	bpred_enable();
120	csr = mfspr(SPR_BUCSR);
121	if ((boothowto & RB_VERBOSE) != 0 || (csr & BUCSR_BPEN) == 0)
122		printf("Branch Predictor %sabled\n",
123		    (csr & BUCSR_BPEN) ? "en" : "dis");
124}
125
126void
127booke_disable_l2_cache(void)
128{
129}
130
131/* Return 0 on handled success, otherwise signal number. */
132int
133cpu_machine_check(struct thread *td, struct trapframe *frame, int *ucode)
134{
135
136	*ucode = BUS_OBJERR;
137	return (SIGBUS);
138}
139