1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Thanks to Mentor Graphics for providing a reference driver for this USB chip 30 * at their homepage. 31 */ 32 33/* 34 * This file contains the driver for the Mentor Graphics Inventra USB 35 * 2.0 High Speed Dual-Role controller. 36 * 37 */ 38 39#ifdef USB_GLOBAL_INCLUDE_FILE 40#include USB_GLOBAL_INCLUDE_FILE 41#else 42#include <sys/stdint.h> 43#include <sys/stddef.h> 44#include <sys/param.h> 45#include <sys/queue.h> 46#include <sys/types.h> 47#include <sys/systm.h> 48#include <sys/kernel.h> 49#include <sys/bus.h> 50#include <sys/module.h> 51#include <sys/lock.h> 52#include <sys/mutex.h> 53#include <sys/condvar.h> 54#include <sys/sysctl.h> 55#include <sys/sx.h> 56#include <sys/unistd.h> 57#include <sys/callout.h> 58#include <sys/malloc.h> 59#include <sys/priv.h> 60 61#include <dev/usb/usb.h> 62#include <dev/usb/usbdi.h> 63 64#define USB_DEBUG_VAR musbotgdebug 65 66#include <dev/usb/usb_core.h> 67#include <dev/usb/usb_debug.h> 68#include <dev/usb/usb_busdma.h> 69#include <dev/usb/usb_process.h> 70#include <dev/usb/usb_transfer.h> 71#include <dev/usb/usb_device.h> 72#include <dev/usb/usb_hub.h> 73#include <dev/usb/usb_util.h> 74 75#include <dev/usb/usb_controller.h> 76#include <dev/usb/usb_bus.h> 77#endif /* USB_GLOBAL_INCLUDE_FILE */ 78 79#include <dev/usb/controller/musb_otg.h> 80 81#define MUSBOTG_INTR_ENDPT 1 82 83#define MUSBOTG_BUS2SC(bus) \ 84 __containerof(bus, struct musbotg_softc, sc_bus) 85 86#define MUSBOTG_PC2SC(pc) \ 87 MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 88 89#ifdef USB_DEBUG 90static int musbotgdebug = 0; 91 92static SYSCTL_NODE(_hw_usb, OID_AUTO, musbotg, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 93 "USB musbotg"); 94SYSCTL_INT(_hw_usb_musbotg, OID_AUTO, debug, CTLFLAG_RWTUN, 95 &musbotgdebug, 0, "Debug level"); 96#endif 97 98#define MAX_NAK_TO 16 99 100/* prototypes */ 101 102static const struct usb_bus_methods musbotg_bus_methods; 103static const struct usb_pipe_methods musbotg_device_bulk_methods; 104static const struct usb_pipe_methods musbotg_device_ctrl_methods; 105static const struct usb_pipe_methods musbotg_device_intr_methods; 106static const struct usb_pipe_methods musbotg_device_isoc_methods; 107 108/* Control transfers: Device mode */ 109static musbotg_cmd_t musbotg_dev_ctrl_setup_rx; 110static musbotg_cmd_t musbotg_dev_ctrl_data_rx; 111static musbotg_cmd_t musbotg_dev_ctrl_data_tx; 112static musbotg_cmd_t musbotg_dev_ctrl_status; 113 114/* Control transfers: Host mode */ 115static musbotg_cmd_t musbotg_host_ctrl_setup_tx; 116static musbotg_cmd_t musbotg_host_ctrl_data_rx; 117static musbotg_cmd_t musbotg_host_ctrl_data_tx; 118static musbotg_cmd_t musbotg_host_ctrl_status_rx; 119static musbotg_cmd_t musbotg_host_ctrl_status_tx; 120 121/* Bulk, Interrupt, Isochronous: Device mode */ 122static musbotg_cmd_t musbotg_dev_data_rx; 123static musbotg_cmd_t musbotg_dev_data_tx; 124 125/* Bulk, Interrupt, Isochronous: Host mode */ 126static musbotg_cmd_t musbotg_host_data_rx; 127static musbotg_cmd_t musbotg_host_data_tx; 128 129static void musbotg_device_done(struct usb_xfer *, usb_error_t); 130static void musbotg_do_poll(struct usb_bus *); 131static void musbotg_standard_done(struct usb_xfer *); 132static void musbotg_interrupt_poll(struct musbotg_softc *); 133static void musbotg_root_intr(struct musbotg_softc *); 134static int musbotg_channel_alloc(struct musbotg_softc *, struct musbotg_td *td, uint8_t); 135static void musbotg_channel_free(struct musbotg_softc *, struct musbotg_td *td); 136static void musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on); 137 138/* 139 * Here is a configuration that the chip supports. 140 */ 141static const struct usb_hw_ep_profile musbotg_ep_profile[1] = { 142 [0] = { 143 .max_in_frame_size = 64,/* fixed */ 144 .max_out_frame_size = 64, /* fixed */ 145 .is_simplex = 1, 146 .support_control = 1, 147 } 148}; 149 150static const struct musb_otg_ep_cfg musbotg_ep_default[] = { 151 { 152 .ep_end = 1, 153 .ep_fifosz_shift = 12, 154 .ep_fifosz_reg = MUSB2_VAL_FIFOSZ_4096 | MUSB2_MASK_FIFODB, 155 }, 156 { 157 .ep_end = 7, 158 .ep_fifosz_shift = 10, 159 .ep_fifosz_reg = MUSB2_VAL_FIFOSZ_512 | MUSB2_MASK_FIFODB, 160 }, 161 { 162 .ep_end = 15, 163 .ep_fifosz_shift = 7, 164 .ep_fifosz_reg = MUSB2_VAL_FIFOSZ_128, 165 }, 166 { 167 .ep_end = -1, 168 }, 169}; 170 171static int 172musbotg_channel_alloc(struct musbotg_softc *sc, struct musbotg_td *td, uint8_t is_tx) 173{ 174 int ch; 175 int ep; 176 177 ep = td->ep_no; 178 179 /* In device mode each EP got its own channel */ 180 if (sc->sc_mode == MUSB2_DEVICE_MODE) { 181 musbotg_ep_int_set(sc, ep, 1); 182 return (ep); 183 } 184 185 /* 186 * All control transactions go through EP0 187 */ 188 if (ep == 0) { 189 if (sc->sc_channel_mask & (1 << 0)) 190 return (-1); 191 sc->sc_channel_mask |= (1 << 0); 192 musbotg_ep_int_set(sc, ep, 1); 193 return (0); 194 } 195 196 for (ch = sc->sc_ep_max; ch != 0; ch--) { 197 if (sc->sc_channel_mask & (1 << ch)) 198 continue; 199 200 /* check FIFO size requirement */ 201 if (is_tx) { 202 if (td->max_frame_size > 203 sc->sc_hw_ep_profile[ch].max_in_frame_size) 204 continue; 205 } else { 206 if (td->max_frame_size > 207 sc->sc_hw_ep_profile[ch].max_out_frame_size) 208 continue; 209 } 210 sc->sc_channel_mask |= (1 << ch); 211 musbotg_ep_int_set(sc, ch, 1); 212 return (ch); 213 } 214 215 DPRINTFN(-1, "No available channels. Mask: %04x\n", sc->sc_channel_mask); 216 217 return (-1); 218} 219 220static void 221musbotg_channel_free(struct musbotg_softc *sc, struct musbotg_td *td) 222{ 223 224 DPRINTFN(1, "ep_no=%d\n", td->channel); 225 226 if (sc->sc_mode == MUSB2_DEVICE_MODE) 227 return; 228 229 if (td == NULL) 230 return; 231 if (td->channel == -1) 232 return; 233 234 musbotg_ep_int_set(sc, td->channel, 0); 235 sc->sc_channel_mask &= ~(1 << td->channel); 236 237 td->channel = -1; 238} 239 240static void 241musbotg_get_hw_ep_profile(struct usb_device *udev, 242 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 243{ 244 struct musbotg_softc *sc; 245 246 sc = MUSBOTG_BUS2SC(udev->bus); 247 248 if (ep_addr == 0) { 249 /* control endpoint */ 250 *ppf = musbotg_ep_profile; 251 } else if (ep_addr <= sc->sc_ep_max) { 252 /* other endpoints */ 253 *ppf = sc->sc_hw_ep_profile + ep_addr; 254 } else { 255 *ppf = NULL; 256 } 257} 258 259static void 260musbotg_clocks_on(struct musbotg_softc *sc) 261{ 262 if (sc->sc_flags.clocks_off && 263 sc->sc_flags.port_powered) { 264 DPRINTFN(4, "\n"); 265 266 if (sc->sc_clocks_on) { 267 (sc->sc_clocks_on) (sc->sc_clocks_arg); 268 } 269 sc->sc_flags.clocks_off = 0; 270 271 /* XXX enable Transceiver */ 272 } 273} 274 275static void 276musbotg_clocks_off(struct musbotg_softc *sc) 277{ 278 if (!sc->sc_flags.clocks_off) { 279 DPRINTFN(4, "\n"); 280 281 /* XXX disable Transceiver */ 282 283 if (sc->sc_clocks_off) { 284 (sc->sc_clocks_off) (sc->sc_clocks_arg); 285 } 286 sc->sc_flags.clocks_off = 1; 287 } 288} 289 290static void 291musbotg_pull_common(struct musbotg_softc *sc, uint8_t on) 292{ 293 uint8_t temp; 294 295 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 296 if (on) 297 temp |= MUSB2_MASK_SOFTC; 298 else 299 temp &= ~MUSB2_MASK_SOFTC; 300 301 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 302} 303 304static void 305musbotg_pull_up(struct musbotg_softc *sc) 306{ 307 /* pullup D+, if possible */ 308 309 if (!sc->sc_flags.d_pulled_up && 310 sc->sc_flags.port_powered) { 311 sc->sc_flags.d_pulled_up = 1; 312 musbotg_pull_common(sc, 1); 313 } 314} 315 316static void 317musbotg_pull_down(struct musbotg_softc *sc) 318{ 319 /* pulldown D+, if possible */ 320 321 if (sc->sc_flags.d_pulled_up) { 322 sc->sc_flags.d_pulled_up = 0; 323 musbotg_pull_common(sc, 0); 324 } 325} 326 327static void 328musbotg_suspend_host(struct musbotg_softc *sc) 329{ 330 uint8_t temp; 331 332 if (sc->sc_flags.status_suspend) { 333 return; 334 } 335 336 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 337 temp |= MUSB2_MASK_SUSPMODE; 338 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 339 sc->sc_flags.status_suspend = 1; 340} 341 342static void 343musbotg_wakeup_host(struct musbotg_softc *sc) 344{ 345 uint8_t temp; 346 347 if (!(sc->sc_flags.status_suspend)) { 348 return; 349 } 350 351 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 352 temp &= ~MUSB2_MASK_SUSPMODE; 353 temp |= MUSB2_MASK_RESUME; 354 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 355 356 /* wait 20 milliseconds */ 357 /* Wait for reset to complete. */ 358 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 359 360 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 361 temp &= ~MUSB2_MASK_RESUME; 362 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 363 364 sc->sc_flags.status_suspend = 0; 365} 366 367static void 368musbotg_wakeup_peer(struct musbotg_softc *sc) 369{ 370 uint8_t temp; 371 372 if (!(sc->sc_flags.status_suspend)) { 373 return; 374 } 375 376 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 377 temp |= MUSB2_MASK_RESUME; 378 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 379 380 /* wait 8 milliseconds */ 381 /* Wait for reset to complete. */ 382 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 383 384 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 385 temp &= ~MUSB2_MASK_RESUME; 386 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 387} 388 389static void 390musbotg_set_address(struct musbotg_softc *sc, uint8_t addr) 391{ 392 DPRINTFN(4, "addr=%d\n", addr); 393 addr &= 0x7F; 394 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr); 395} 396 397static uint8_t 398musbotg_dev_ctrl_setup_rx(struct musbotg_td *td) 399{ 400 struct musbotg_softc *sc; 401 struct usb_device_request req; 402 uint16_t count; 403 uint8_t csr; 404 405 /* get pointer to softc */ 406 sc = MUSBOTG_PC2SC(td->pc); 407 408 if (td->channel == -1) 409 td->channel = musbotg_channel_alloc(sc, td, 0); 410 411 /* EP0 is busy, wait */ 412 if (td->channel == -1) 413 return (1); 414 415 DPRINTFN(1, "ep_no=%d\n", td->channel); 416 417 /* select endpoint 0 */ 418 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 419 420 /* read out FIFO status */ 421 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 422 423 DPRINTFN(4, "csr=0x%02x\n", csr); 424 425 /* 426 * NOTE: If DATAEND is set we should not call the 427 * callback, hence the status stage is not complete. 428 */ 429 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 430 /* do not stall at this point */ 431 td->did_stall = 1; 432 /* wait for interrupt */ 433 DPRINTFN(1, "CSR0 DATAEND\n"); 434 goto not_complete; 435 } 436 437 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) { 438 /* clear SENTSTALL */ 439 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 440 /* get latest status */ 441 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 442 /* update EP0 state */ 443 sc->sc_ep0_busy = 0; 444 } 445 if (csr & MUSB2_MASK_CSR0L_SETUPEND) { 446 /* clear SETUPEND */ 447 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 448 MUSB2_MASK_CSR0L_SETUPEND_CLR); 449 /* get latest status */ 450 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 451 /* update EP0 state */ 452 sc->sc_ep0_busy = 0; 453 } 454 if (sc->sc_ep0_busy) { 455 DPRINTFN(1, "EP0 BUSY\n"); 456 goto not_complete; 457 } 458 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 459 goto not_complete; 460 } 461 /* get the packet byte count */ 462 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 463 464 /* verify data length */ 465 if (count != td->remainder) { 466 DPRINTFN(1, "Invalid SETUP packet " 467 "length, %d bytes\n", count); 468 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 469 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 470 /* don't clear stall */ 471 td->did_stall = 1; 472 goto not_complete; 473 } 474 if (count != sizeof(req)) { 475 DPRINTFN(1, "Unsupported SETUP packet " 476 "length, %d bytes\n", count); 477 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 478 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 479 /* don't clear stall */ 480 td->did_stall = 1; 481 goto not_complete; 482 } 483 /* clear did stall flag */ 484 td->did_stall = 0; 485 486 /* receive data */ 487 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 488 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); 489 490 /* copy data into real buffer */ 491 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 492 493 td->offset = sizeof(req); 494 td->remainder = 0; 495 496 /* set pending command */ 497 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 498 499 /* we need set stall or dataend after this */ 500 sc->sc_ep0_busy = 1; 501 502 /* sneak peek the set address */ 503 if ((req.bmRequestType == UT_WRITE_DEVICE) && 504 (req.bRequest == UR_SET_ADDRESS)) { 505 sc->sc_dv_addr = req.wValue[0] & 0x7F; 506 } else { 507 sc->sc_dv_addr = 0xFF; 508 } 509 510 musbotg_channel_free(sc, td); 511 return (0); /* complete */ 512 513not_complete: 514 /* abort any ongoing transfer */ 515 if (!td->did_stall) { 516 DPRINTFN(4, "stalling\n"); 517 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 518 MUSB2_MASK_CSR0L_SENDSTALL); 519 td->did_stall = 1; 520 } 521 return (1); /* not complete */ 522} 523 524static uint8_t 525musbotg_host_ctrl_setup_tx(struct musbotg_td *td) 526{ 527 struct musbotg_softc *sc; 528 struct usb_device_request req; 529 uint8_t csr, csrh; 530 531 /* get pointer to softc */ 532 sc = MUSBOTG_PC2SC(td->pc); 533 534 if (td->channel == -1) 535 td->channel = musbotg_channel_alloc(sc, td, 1); 536 537 /* EP0 is busy, wait */ 538 if (td->channel == -1) 539 return (1); 540 541 DPRINTFN(1, "ep_no=%d\n", td->channel); 542 543 /* select endpoint 0 */ 544 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 545 546 /* read out FIFO status */ 547 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 548 DPRINTFN(4, "csr=0x%02x\n", csr); 549 550 /* Not ready yet yet */ 551 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 552 return (1); 553 554 /* Failed */ 555 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 556 MUSB2_MASK_CSR0L_ERROR)) 557 { 558 /* Clear status bit */ 559 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 560 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 561 td->error = 1; 562 } 563 564 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 565 DPRINTFN(1, "NAK timeout\n"); 566 567 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 568 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 569 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 570 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 571 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 572 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 573 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 574 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 575 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 576 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 577 } 578 } 579 580 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 581 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 582 583 td->error = 1; 584 } 585 586 if (td->error) { 587 musbotg_channel_free(sc, td); 588 return (0); 589 } 590 591 /* Fifo is not empty and there is no NAK timeout */ 592 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 593 return (1); 594 595 /* check if we are complete */ 596 if (td->remainder == 0) { 597 /* we are complete */ 598 musbotg_channel_free(sc, td); 599 return (0); 600 } 601 602 /* copy data into real buffer */ 603 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 604 605 /* send data */ 606 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 607 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); 608 609 /* update offset and remainder */ 610 td->offset += sizeof(req); 611 td->remainder -= sizeof(req); 612 613 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 614 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr); 615 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr); 616 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport); 617 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 618 619 /* write command */ 620 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 621 MUSB2_MASK_CSR0L_TXPKTRDY | 622 MUSB2_MASK_CSR0L_SETUPPKT); 623 624 /* Just to be consistent, not used above */ 625 td->transaction_started = 1; 626 627 return (1); /* in progress */ 628} 629 630/* Control endpoint only data handling functions (RX/TX/SYNC) */ 631 632static uint8_t 633musbotg_dev_ctrl_data_rx(struct musbotg_td *td) 634{ 635 struct usb_page_search buf_res; 636 struct musbotg_softc *sc; 637 uint16_t count; 638 uint8_t csr; 639 uint8_t got_short; 640 641 /* get pointer to softc */ 642 sc = MUSBOTG_PC2SC(td->pc); 643 644 /* select endpoint 0 */ 645 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 646 647 /* check if a command is pending */ 648 if (sc->sc_ep0_cmd) { 649 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 650 sc->sc_ep0_cmd = 0; 651 } 652 /* read out FIFO status */ 653 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 654 655 DPRINTFN(4, "csr=0x%02x\n", csr); 656 657 got_short = 0; 658 659 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 660 MUSB2_MASK_CSR0L_SENTSTALL)) { 661 if (td->remainder == 0) { 662 /* 663 * We are actually complete and have 664 * received the next SETUP 665 */ 666 DPRINTFN(4, "faking complete\n"); 667 return (0); /* complete */ 668 } 669 /* 670 * USB Host Aborted the transfer. 671 */ 672 td->error = 1; 673 return (0); /* complete */ 674 } 675 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 676 return (1); /* not complete */ 677 } 678 /* get the packet byte count */ 679 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 680 681 /* verify the packet byte count */ 682 if (count != td->max_frame_size) { 683 if (count < td->max_frame_size) { 684 /* we have a short packet */ 685 td->short_pkt = 1; 686 got_short = 1; 687 } else { 688 /* invalid USB packet */ 689 td->error = 1; 690 return (0); /* we are complete */ 691 } 692 } 693 /* verify the packet byte count */ 694 if (count > td->remainder) { 695 /* invalid USB packet */ 696 td->error = 1; 697 return (0); /* we are complete */ 698 } 699 while (count > 0) { 700 uint32_t temp; 701 702 usbd_get_page(td->pc, td->offset, &buf_res); 703 704 /* get correct length */ 705 if (buf_res.length > count) { 706 buf_res.length = count; 707 } 708 /* check for unaligned memory address */ 709 if (USB_P2U(buf_res.buffer) & 3) { 710 temp = count & ~3; 711 712 if (temp) { 713 /* receive data 4 bytes at a time */ 714 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 715 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 716 temp / 4); 717 } 718 temp = count & 3; 719 if (temp) { 720 /* receive data 1 byte at a time */ 721 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 722 MUSB2_REG_EPFIFO(0), 723 (void *)(&sc->sc_bounce_buf[count / 4]), temp); 724 } 725 usbd_copy_in(td->pc, td->offset, 726 sc->sc_bounce_buf, count); 727 728 /* update offset and remainder */ 729 td->offset += count; 730 td->remainder -= count; 731 break; 732 } 733 /* check if we can optimise */ 734 if (buf_res.length >= 4) { 735 /* receive data 4 bytes at a time */ 736 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 737 MUSB2_REG_EPFIFO(0), buf_res.buffer, 738 buf_res.length / 4); 739 740 temp = buf_res.length & ~3; 741 742 /* update counters */ 743 count -= temp; 744 td->offset += temp; 745 td->remainder -= temp; 746 continue; 747 } 748 /* receive data */ 749 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 750 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 751 752 /* update counters */ 753 count -= buf_res.length; 754 td->offset += buf_res.length; 755 td->remainder -= buf_res.length; 756 } 757 758 /* check if we are complete */ 759 if ((td->remainder == 0) || got_short) { 760 if (td->short_pkt) { 761 /* we are complete */ 762 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 763 return (0); 764 } 765 /* else need to receive a zero length packet */ 766 } 767 /* write command - need more data */ 768 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 769 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 770 return (1); /* not complete */ 771} 772 773static uint8_t 774musbotg_dev_ctrl_data_tx(struct musbotg_td *td) 775{ 776 struct usb_page_search buf_res; 777 struct musbotg_softc *sc; 778 uint16_t count; 779 uint8_t csr; 780 781 /* get pointer to softc */ 782 sc = MUSBOTG_PC2SC(td->pc); 783 784 /* select endpoint 0 */ 785 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 786 787 /* check if a command is pending */ 788 if (sc->sc_ep0_cmd) { 789 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 790 sc->sc_ep0_cmd = 0; 791 } 792 /* read out FIFO status */ 793 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 794 795 DPRINTFN(4, "csr=0x%02x\n", csr); 796 797 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 798 MUSB2_MASK_CSR0L_SENTSTALL)) { 799 /* 800 * The current transfer was aborted 801 * by the USB Host 802 */ 803 td->error = 1; 804 return (0); /* complete */ 805 } 806 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) { 807 return (1); /* not complete */ 808 } 809 count = td->max_frame_size; 810 if (td->remainder < count) { 811 /* we have a short packet */ 812 td->short_pkt = 1; 813 count = td->remainder; 814 } 815 while (count > 0) { 816 uint32_t temp; 817 818 usbd_get_page(td->pc, td->offset, &buf_res); 819 820 /* get correct length */ 821 if (buf_res.length > count) { 822 buf_res.length = count; 823 } 824 /* check for unaligned memory address */ 825 if (USB_P2U(buf_res.buffer) & 3) { 826 usbd_copy_out(td->pc, td->offset, 827 sc->sc_bounce_buf, count); 828 829 temp = count & ~3; 830 831 if (temp) { 832 /* transmit data 4 bytes at a time */ 833 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 834 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 835 temp / 4); 836 } 837 temp = count & 3; 838 if (temp) { 839 /* receive data 1 byte at a time */ 840 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 841 MUSB2_REG_EPFIFO(0), 842 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 843 } 844 /* update offset and remainder */ 845 td->offset += count; 846 td->remainder -= count; 847 break; 848 } 849 /* check if we can optimise */ 850 if (buf_res.length >= 4) { 851 /* transmit data 4 bytes at a time */ 852 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 853 MUSB2_REG_EPFIFO(0), buf_res.buffer, 854 buf_res.length / 4); 855 856 temp = buf_res.length & ~3; 857 858 /* update counters */ 859 count -= temp; 860 td->offset += temp; 861 td->remainder -= temp; 862 continue; 863 } 864 /* transmit data */ 865 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 866 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 867 868 /* update counters */ 869 count -= buf_res.length; 870 td->offset += buf_res.length; 871 td->remainder -= buf_res.length; 872 } 873 874 /* check remainder */ 875 if (td->remainder == 0) { 876 if (td->short_pkt) { 877 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY; 878 return (0); /* complete */ 879 } 880 /* else we need to transmit a short packet */ 881 } 882 /* write command */ 883 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 884 MUSB2_MASK_CSR0L_TXPKTRDY); 885 886 return (1); /* not complete */ 887} 888 889static uint8_t 890musbotg_host_ctrl_data_rx(struct musbotg_td *td) 891{ 892 struct usb_page_search buf_res; 893 struct musbotg_softc *sc; 894 uint16_t count; 895 uint8_t csr; 896 uint8_t got_short; 897 898 /* get pointer to softc */ 899 sc = MUSBOTG_PC2SC(td->pc); 900 901 if (td->channel == -1) 902 td->channel = musbotg_channel_alloc(sc, td, 0); 903 904 /* EP0 is busy, wait */ 905 if (td->channel == -1) 906 return (1); 907 908 DPRINTFN(1, "ep_no=%d\n", td->channel); 909 910 /* select endpoint 0 */ 911 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 912 913 /* read out FIFO status */ 914 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 915 916 DPRINTFN(4, "csr=0x%02x\n", csr); 917 918 got_short = 0; 919 if (!td->transaction_started) { 920 td->transaction_started = 1; 921 922 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO); 923 924 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0), 925 td->dev_addr); 926 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr); 927 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport); 928 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type); 929 930 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 931 MUSB2_MASK_CSR0L_REQPKT); 932 933 return (1); 934 } 935 936 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 937 csr &= ~MUSB2_MASK_CSR0L_REQPKT; 938 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 939 940 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 941 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 942 943 td->error = 1; 944 } 945 946 /* Failed */ 947 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 948 MUSB2_MASK_CSR0L_ERROR)) 949 { 950 /* Clear status bit */ 951 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 952 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 953 td->error = 1; 954 } 955 956 if (td->error) { 957 musbotg_channel_free(sc, td); 958 return (0); /* we are complete */ 959 } 960 961 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) 962 return (1); /* not yet */ 963 964 /* get the packet byte count */ 965 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 966 967 /* verify the packet byte count */ 968 if (count != td->max_frame_size) { 969 if (count < td->max_frame_size) { 970 /* we have a short packet */ 971 td->short_pkt = 1; 972 got_short = 1; 973 } else { 974 /* invalid USB packet */ 975 td->error = 1; 976 musbotg_channel_free(sc, td); 977 return (0); /* we are complete */ 978 } 979 } 980 /* verify the packet byte count */ 981 if (count > td->remainder) { 982 /* invalid USB packet */ 983 td->error = 1; 984 musbotg_channel_free(sc, td); 985 return (0); /* we are complete */ 986 } 987 while (count > 0) { 988 uint32_t temp; 989 990 usbd_get_page(td->pc, td->offset, &buf_res); 991 992 /* get correct length */ 993 if (buf_res.length > count) { 994 buf_res.length = count; 995 } 996 /* check for unaligned memory address */ 997 if (USB_P2U(buf_res.buffer) & 3) { 998 temp = count & ~3; 999 1000 if (temp) { 1001 /* receive data 4 bytes at a time */ 1002 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1003 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 1004 temp / 4); 1005 } 1006 temp = count & 3; 1007 if (temp) { 1008 /* receive data 1 byte at a time */ 1009 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1010 MUSB2_REG_EPFIFO(0), 1011 (void *)(&sc->sc_bounce_buf[count / 4]), temp); 1012 } 1013 usbd_copy_in(td->pc, td->offset, 1014 sc->sc_bounce_buf, count); 1015 1016 /* update offset and remainder */ 1017 td->offset += count; 1018 td->remainder -= count; 1019 break; 1020 } 1021 /* check if we can optimise */ 1022 if (buf_res.length >= 4) { 1023 /* receive data 4 bytes at a time */ 1024 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1025 MUSB2_REG_EPFIFO(0), buf_res.buffer, 1026 buf_res.length / 4); 1027 1028 temp = buf_res.length & ~3; 1029 1030 /* update counters */ 1031 count -= temp; 1032 td->offset += temp; 1033 td->remainder -= temp; 1034 continue; 1035 } 1036 /* receive data */ 1037 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1038 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 1039 1040 /* update counters */ 1041 count -= buf_res.length; 1042 td->offset += buf_res.length; 1043 td->remainder -= buf_res.length; 1044 } 1045 1046 csr &= ~MUSB2_MASK_CSR0L_RXPKTRDY; 1047 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1048 1049 /* check if we are complete */ 1050 if ((td->remainder == 0) || got_short) { 1051 if (td->short_pkt) { 1052 /* we are complete */ 1053 1054 musbotg_channel_free(sc, td); 1055 return (0); 1056 } 1057 /* else need to receive a zero length packet */ 1058 } 1059 1060 td->transaction_started = 1; 1061 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1062 MUSB2_MASK_CSR0L_REQPKT); 1063 1064 return (1); /* not complete */ 1065} 1066 1067static uint8_t 1068musbotg_host_ctrl_data_tx(struct musbotg_td *td) 1069{ 1070 struct usb_page_search buf_res; 1071 struct musbotg_softc *sc; 1072 uint16_t count; 1073 uint8_t csr, csrh; 1074 1075 /* get pointer to softc */ 1076 sc = MUSBOTG_PC2SC(td->pc); 1077 1078 if (td->channel == -1) 1079 td->channel = musbotg_channel_alloc(sc, td, 1); 1080 1081 /* No free EPs */ 1082 if (td->channel == -1) 1083 return (1); 1084 1085 DPRINTFN(1, "ep_no=%d\n", td->channel); 1086 1087 /* select endpoint */ 1088 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1089 1090 /* read out FIFO status */ 1091 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1092 DPRINTFN(4, "csr=0x%02x\n", csr); 1093 1094 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 1095 MUSB2_MASK_CSR0L_ERROR)) { 1096 /* clear status bits */ 1097 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1098 td->error = 1; 1099 } 1100 1101 if (csr & MUSB2_MASK_CSR0L_NAKTIMO ) { 1102 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1103 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 1104 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 1105 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 1106 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1107 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1108 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 1109 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 1110 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 1111 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1112 } 1113 } 1114 1115 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1116 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1117 1118 td->error = 1; 1119 } 1120 1121 if (td->error) { 1122 musbotg_channel_free(sc, td); 1123 return (0); /* complete */ 1124 } 1125 1126 /* 1127 * Wait while FIFO is empty. 1128 * Do not flush it because it will cause transactions 1129 * with size more then packet size. It might upset 1130 * some devices 1131 */ 1132 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) 1133 return (1); 1134 1135 /* Packet still being processed */ 1136 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 1137 return (1); 1138 1139 if (td->transaction_started) { 1140 /* check remainder */ 1141 if (td->remainder == 0) { 1142 if (td->short_pkt) { 1143 musbotg_channel_free(sc, td); 1144 return (0); /* complete */ 1145 } 1146 /* else we need to transmit a short packet */ 1147 } 1148 1149 /* We're not complete - more transactions required */ 1150 td->transaction_started = 0; 1151 } 1152 1153 /* check for short packet */ 1154 count = td->max_frame_size; 1155 if (td->remainder < count) { 1156 /* we have a short packet */ 1157 td->short_pkt = 1; 1158 count = td->remainder; 1159 } 1160 1161 while (count > 0) { 1162 uint32_t temp; 1163 1164 usbd_get_page(td->pc, td->offset, &buf_res); 1165 1166 /* get correct length */ 1167 if (buf_res.length > count) { 1168 buf_res.length = count; 1169 } 1170 /* check for unaligned memory address */ 1171 if (USB_P2U(buf_res.buffer) & 3) { 1172 usbd_copy_out(td->pc, td->offset, 1173 sc->sc_bounce_buf, count); 1174 1175 temp = count & ~3; 1176 1177 if (temp) { 1178 /* transmit data 4 bytes at a time */ 1179 bus_space_write_multi_4(sc->sc_io_tag, 1180 sc->sc_io_hdl, MUSB2_REG_EPFIFO(0), 1181 sc->sc_bounce_buf, temp / 4); 1182 } 1183 temp = count & 3; 1184 if (temp) { 1185 /* receive data 1 byte at a time */ 1186 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1187 MUSB2_REG_EPFIFO(0), 1188 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1189 } 1190 /* update offset and remainder */ 1191 td->offset += count; 1192 td->remainder -= count; 1193 break; 1194 } 1195 /* check if we can optimise */ 1196 if (buf_res.length >= 4) { 1197 /* transmit data 4 bytes at a time */ 1198 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1199 MUSB2_REG_EPFIFO(0), buf_res.buffer, 1200 buf_res.length / 4); 1201 1202 temp = buf_res.length & ~3; 1203 1204 /* update counters */ 1205 count -= temp; 1206 td->offset += temp; 1207 td->remainder -= temp; 1208 continue; 1209 } 1210 /* transmit data */ 1211 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1212 MUSB2_REG_EPFIFO(0), buf_res.buffer, 1213 buf_res.length); 1214 1215 /* update counters */ 1216 count -= buf_res.length; 1217 td->offset += buf_res.length; 1218 td->remainder -= buf_res.length; 1219 } 1220 1221 /* Function address */ 1222 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr); 1223 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr); 1224 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport); 1225 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 1226 1227 /* TX NAK timeout */ 1228 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 1229 1230 /* write command */ 1231 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1232 MUSB2_MASK_CSR0L_TXPKTRDY); 1233 1234 td->transaction_started = 1; 1235 1236 return (1); /* not complete */ 1237} 1238 1239static uint8_t 1240musbotg_dev_ctrl_status(struct musbotg_td *td) 1241{ 1242 struct musbotg_softc *sc; 1243 uint8_t csr; 1244 1245 /* get pointer to softc */ 1246 sc = MUSBOTG_PC2SC(td->pc); 1247 1248 /* select endpoint 0 */ 1249 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1250 1251 if (sc->sc_ep0_busy) { 1252 sc->sc_ep0_busy = 0; 1253 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND; 1254 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 1255 sc->sc_ep0_cmd = 0; 1256 } 1257 /* read out FIFO status */ 1258 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1259 1260 DPRINTFN(4, "csr=0x%02x\n", csr); 1261 1262 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 1263 /* wait for interrupt */ 1264 return (1); /* not complete */ 1265 } 1266 if (sc->sc_dv_addr != 0xFF) { 1267 /* write function address */ 1268 musbotg_set_address(sc, sc->sc_dv_addr); 1269 } 1270 1271 musbotg_channel_free(sc, td); 1272 return (0); /* complete */ 1273} 1274 1275static uint8_t 1276musbotg_host_ctrl_status_rx(struct musbotg_td *td) 1277{ 1278 struct musbotg_softc *sc; 1279 uint8_t csr, csrh; 1280 1281 /* get pointer to softc */ 1282 sc = MUSBOTG_PC2SC(td->pc); 1283 1284 if (td->channel == -1) 1285 td->channel = musbotg_channel_alloc(sc, td, 0); 1286 1287 /* EP0 is busy, wait */ 1288 if (td->channel == -1) 1289 return (1); 1290 1291 DPRINTFN(1, "ep_no=%d\n", td->channel); 1292 1293 /* select endpoint 0 */ 1294 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1295 1296 if (!td->transaction_started) { 1297 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0), 1298 td->dev_addr); 1299 1300 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr); 1301 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport); 1302 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type); 1303 1304 /* RX NAK timeout */ 1305 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO); 1306 1307 td->transaction_started = 1; 1308 1309 /* Disable PING */ 1310 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH); 1311 csrh |= MUSB2_MASK_CSR0H_PING_DIS; 1312 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh); 1313 1314 /* write command */ 1315 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1316 MUSB2_MASK_CSR0L_STATUSPKT | 1317 MUSB2_MASK_CSR0L_REQPKT); 1318 1319 return (1); /* Just started */ 1320 } 1321 1322 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1323 1324 DPRINTFN(4, "IN STATUS csr=0x%02x\n", csr); 1325 1326 if (csr & MUSB2_MASK_CSR0L_RXPKTRDY) { 1327 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1328 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 1329 musbotg_channel_free(sc, td); 1330 return (0); /* complete */ 1331 } 1332 1333 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1334 csr &= ~ (MUSB2_MASK_CSR0L_STATUSPKT | 1335 MUSB2_MASK_CSR0L_REQPKT); 1336 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1337 1338 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1339 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1340 td->error = 1; 1341 } 1342 1343 /* Failed */ 1344 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 1345 MUSB2_MASK_CSR0L_ERROR)) 1346 { 1347 /* Clear status bit */ 1348 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1349 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 1350 td->error = 1; 1351 } 1352 1353 if (td->error) { 1354 musbotg_channel_free(sc, td); 1355 return (0); 1356 } 1357 1358 return (1); /* Not ready yet */ 1359} 1360 1361static uint8_t 1362musbotg_host_ctrl_status_tx(struct musbotg_td *td) 1363{ 1364 struct musbotg_softc *sc; 1365 uint8_t csr; 1366 1367 /* get pointer to softc */ 1368 sc = MUSBOTG_PC2SC(td->pc); 1369 1370 if (td->channel == -1) 1371 td->channel = musbotg_channel_alloc(sc, td, 1); 1372 1373 /* EP0 is busy, wait */ 1374 if (td->channel == -1) 1375 return (1); 1376 1377 DPRINTFN(1, "ep_no=%d/%d [%d@%d.%d/%02x]\n", td->channel, td->transaction_started, 1378 td->dev_addr,td->haddr,td->hport, td->transfer_type); 1379 1380 /* select endpoint 0 */ 1381 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1382 1383 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1384 DPRINTFN(4, "csr=0x%02x\n", csr); 1385 1386 /* Not yet */ 1387 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 1388 return (1); 1389 1390 /* Failed */ 1391 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 1392 MUSB2_MASK_CSR0L_ERROR)) 1393 { 1394 /* Clear status bit */ 1395 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1396 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 1397 td->error = 1; 1398 musbotg_channel_free(sc, td); 1399 return (0); /* complete */ 1400 } 1401 1402 if (td->transaction_started) { 1403 musbotg_channel_free(sc, td); 1404 return (0); /* complete */ 1405 } 1406 1407 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, MUSB2_MASK_CSR0H_PING_DIS); 1408 1409 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr); 1410 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr); 1411 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport); 1412 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 1413 1414 /* TX NAK timeout */ 1415 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 1416 1417 td->transaction_started = 1; 1418 1419 /* write command */ 1420 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1421 MUSB2_MASK_CSR0L_STATUSPKT | 1422 MUSB2_MASK_CSR0L_TXPKTRDY); 1423 1424 return (1); /* wait for interrupt */ 1425} 1426 1427static uint8_t 1428musbotg_dev_data_rx(struct musbotg_td *td) 1429{ 1430 struct usb_page_search buf_res; 1431 struct musbotg_softc *sc; 1432 uint16_t count; 1433 uint8_t csr; 1434 uint8_t to; 1435 uint8_t got_short; 1436 1437 to = 8; /* don't loop forever! */ 1438 got_short = 0; 1439 1440 /* get pointer to softc */ 1441 sc = MUSBOTG_PC2SC(td->pc); 1442 1443 if (td->channel == -1) 1444 td->channel = musbotg_channel_alloc(sc, td, 0); 1445 1446 /* EP0 is busy, wait */ 1447 if (td->channel == -1) 1448 return (1); 1449 1450 /* select endpoint */ 1451 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1452 1453repeat: 1454 /* read out FIFO status */ 1455 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1456 1457 DPRINTFN(4, "csr=0x%02x\n", csr); 1458 1459 /* clear overrun */ 1460 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) { 1461 /* make sure we don't clear "RXPKTRDY" */ 1462 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1463 MUSB2_MASK_CSRL_RXPKTRDY); 1464 } 1465 1466 /* check status */ 1467 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) 1468 return (1); /* not complete */ 1469 1470 /* get the packet byte count */ 1471 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 1472 1473 DPRINTFN(4, "count=0x%04x\n", count); 1474 1475 /* 1476 * Check for short or invalid packet: 1477 */ 1478 if (count != td->max_frame_size) { 1479 if (count < td->max_frame_size) { 1480 /* we have a short packet */ 1481 td->short_pkt = 1; 1482 got_short = 1; 1483 } else { 1484 /* invalid USB packet */ 1485 td->error = 1; 1486 musbotg_channel_free(sc, td); 1487 return (0); /* we are complete */ 1488 } 1489 } 1490 /* verify the packet byte count */ 1491 if (count > td->remainder) { 1492 /* invalid USB packet */ 1493 td->error = 1; 1494 musbotg_channel_free(sc, td); 1495 return (0); /* we are complete */ 1496 } 1497 while (count > 0) { 1498 uint32_t temp; 1499 1500 usbd_get_page(td->pc, td->offset, &buf_res); 1501 1502 /* get correct length */ 1503 if (buf_res.length > count) { 1504 buf_res.length = count; 1505 } 1506 /* check for unaligned memory address */ 1507 if (USB_P2U(buf_res.buffer) & 3) { 1508 temp = count & ~3; 1509 1510 if (temp) { 1511 /* receive data 4 bytes at a time */ 1512 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1513 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf, 1514 temp / 4); 1515 } 1516 temp = count & 3; 1517 if (temp) { 1518 /* receive data 1 byte at a time */ 1519 bus_space_read_multi_1(sc->sc_io_tag, 1520 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 1521 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1522 } 1523 usbd_copy_in(td->pc, td->offset, 1524 sc->sc_bounce_buf, count); 1525 1526 /* update offset and remainder */ 1527 td->offset += count; 1528 td->remainder -= count; 1529 break; 1530 } 1531 /* check if we can optimise */ 1532 if (buf_res.length >= 4) { 1533 /* receive data 4 bytes at a time */ 1534 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1535 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1536 buf_res.length / 4); 1537 1538 temp = buf_res.length & ~3; 1539 1540 /* update counters */ 1541 count -= temp; 1542 td->offset += temp; 1543 td->remainder -= temp; 1544 continue; 1545 } 1546 /* receive data */ 1547 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1548 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1549 buf_res.length); 1550 1551 /* update counters */ 1552 count -= buf_res.length; 1553 td->offset += buf_res.length; 1554 td->remainder -= buf_res.length; 1555 } 1556 1557 /* clear status bits */ 1558 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1559 1560 /* check if we are complete */ 1561 if ((td->remainder == 0) || got_short) { 1562 if (td->short_pkt) { 1563 /* we are complete */ 1564 musbotg_channel_free(sc, td); 1565 return (0); 1566 } 1567 /* else need to receive a zero length packet */ 1568 } 1569 if (--to) { 1570 goto repeat; 1571 } 1572 return (1); /* not complete */ 1573} 1574 1575static uint8_t 1576musbotg_dev_data_tx(struct musbotg_td *td) 1577{ 1578 struct usb_page_search buf_res; 1579 struct musbotg_softc *sc; 1580 uint16_t count; 1581 uint8_t csr; 1582 uint8_t to; 1583 1584 to = 8; /* don't loop forever! */ 1585 1586 /* get pointer to softc */ 1587 sc = MUSBOTG_PC2SC(td->pc); 1588 1589 if (td->channel == -1) 1590 td->channel = musbotg_channel_alloc(sc, td, 1); 1591 1592 /* EP0 is busy, wait */ 1593 if (td->channel == -1) 1594 return (1); 1595 1596 /* select endpoint */ 1597 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1598 1599repeat: 1600 1601 /* read out FIFO status */ 1602 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1603 1604 DPRINTFN(4, "csr=0x%02x\n", csr); 1605 1606 if (csr & (MUSB2_MASK_CSRL_TXINCOMP | 1607 MUSB2_MASK_CSRL_TXUNDERRUN)) { 1608 /* clear status bits */ 1609 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1610 } 1611 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) { 1612 return (1); /* not complete */ 1613 } 1614 /* check for short packet */ 1615 count = td->max_frame_size; 1616 if (td->remainder < count) { 1617 /* we have a short packet */ 1618 td->short_pkt = 1; 1619 count = td->remainder; 1620 } 1621 while (count > 0) { 1622 uint32_t temp; 1623 1624 usbd_get_page(td->pc, td->offset, &buf_res); 1625 1626 /* get correct length */ 1627 if (buf_res.length > count) { 1628 buf_res.length = count; 1629 } 1630 /* check for unaligned memory address */ 1631 if (USB_P2U(buf_res.buffer) & 3) { 1632 usbd_copy_out(td->pc, td->offset, 1633 sc->sc_bounce_buf, count); 1634 1635 temp = count & ~3; 1636 1637 if (temp) { 1638 /* transmit data 4 bytes at a time */ 1639 bus_space_write_multi_4(sc->sc_io_tag, 1640 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 1641 sc->sc_bounce_buf, temp / 4); 1642 } 1643 temp = count & 3; 1644 if (temp) { 1645 /* receive data 1 byte at a time */ 1646 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1647 MUSB2_REG_EPFIFO(td->channel), 1648 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1649 } 1650 /* update offset and remainder */ 1651 td->offset += count; 1652 td->remainder -= count; 1653 break; 1654 } 1655 /* check if we can optimise */ 1656 if (buf_res.length >= 4) { 1657 /* transmit data 4 bytes at a time */ 1658 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1659 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1660 buf_res.length / 4); 1661 1662 temp = buf_res.length & ~3; 1663 1664 /* update counters */ 1665 count -= temp; 1666 td->offset += temp; 1667 td->remainder -= temp; 1668 continue; 1669 } 1670 /* transmit data */ 1671 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1672 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1673 buf_res.length); 1674 1675 /* update counters */ 1676 count -= buf_res.length; 1677 td->offset += buf_res.length; 1678 td->remainder -= buf_res.length; 1679 } 1680 1681 /* Max packet size */ 1682 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet); 1683 1684 /* write command */ 1685 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1686 MUSB2_MASK_CSRL_TXPKTRDY); 1687 1688 /* check remainder */ 1689 if (td->remainder == 0) { 1690 if (td->short_pkt) { 1691 musbotg_channel_free(sc, td); 1692 return (0); /* complete */ 1693 } 1694 /* else we need to transmit a short packet */ 1695 } 1696 if (--to) { 1697 goto repeat; 1698 } 1699 return (1); /* not complete */ 1700} 1701 1702static uint8_t 1703musbotg_host_data_rx(struct musbotg_td *td) 1704{ 1705 struct usb_page_search buf_res; 1706 struct musbotg_softc *sc; 1707 uint16_t count; 1708 uint8_t csr, csrh; 1709 uint8_t to; 1710 uint8_t got_short; 1711 1712 /* get pointer to softc */ 1713 sc = MUSBOTG_PC2SC(td->pc); 1714 1715 if (td->channel == -1) 1716 td->channel = musbotg_channel_alloc(sc, td, 0); 1717 1718 /* No free EPs */ 1719 if (td->channel == -1) 1720 return (1); 1721 1722 DPRINTFN(1, "ep_no=%d\n", td->channel); 1723 1724 to = 8; /* don't loop forever! */ 1725 got_short = 0; 1726 1727 /* select endpoint */ 1728 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1729 1730repeat: 1731 /* read out FIFO status */ 1732 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1733 DPRINTFN(4, "csr=0x%02x\n", csr); 1734 1735 if (!td->transaction_started) { 1736 /* Function address */ 1737 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(td->channel), 1738 td->dev_addr); 1739 1740 /* SPLIT transaction */ 1741 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(td->channel), 1742 td->haddr); 1743 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(td->channel), 1744 td->hport); 1745 1746 /* RX NAK timeout */ 1747 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC) 1748 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, 0); 1749 else 1750 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO); 1751 1752 /* Protocol, speed, device endpoint */ 1753 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type); 1754 1755 /* Max packet size */ 1756 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, td->reg_max_packet); 1757 1758 /* Data Toggle */ 1759 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH); 1760 DPRINTFN(4, "csrh=0x%02x\n", csrh); 1761 1762 csrh |= MUSB2_MASK_CSRH_RXDT_WREN; 1763 if (td->toggle) 1764 csrh |= MUSB2_MASK_CSRH_RXDT_VAL; 1765 else 1766 csrh &= ~MUSB2_MASK_CSRH_RXDT_VAL; 1767 1768 /* Set data toggle */ 1769 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh); 1770 1771 /* write command */ 1772 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1773 MUSB2_MASK_CSRL_RXREQPKT); 1774 1775 td->transaction_started = 1; 1776 return (1); 1777 } 1778 1779 /* clear NAK timeout */ 1780 if (csr & MUSB2_MASK_CSRL_RXNAKTO) { 1781 DPRINTFN(4, "NAK Timeout\n"); 1782 if (csr & MUSB2_MASK_CSRL_RXREQPKT) { 1783 csr &= ~MUSB2_MASK_CSRL_RXREQPKT; 1784 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr); 1785 1786 csr &= ~MUSB2_MASK_CSRL_RXNAKTO; 1787 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr); 1788 } 1789 1790 td->error = 1; 1791 } 1792 1793 if (csr & MUSB2_MASK_CSRL_RXERROR) { 1794 DPRINTFN(4, "RXERROR\n"); 1795 td->error = 1; 1796 } 1797 1798 if (csr & MUSB2_MASK_CSRL_RXSTALL) { 1799 DPRINTFN(4, "RXSTALL\n"); 1800 td->error = 1; 1801 } 1802 1803 if (td->error) { 1804 musbotg_channel_free(sc, td); 1805 return (0); /* we are complete */ 1806 } 1807 1808 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) { 1809 /* No data available yet */ 1810 return (1); 1811 } 1812 1813 td->toggle ^= 1; 1814 /* get the packet byte count */ 1815 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 1816 DPRINTFN(4, "count=0x%04x\n", count); 1817 1818 /* 1819 * Check for short or invalid packet: 1820 */ 1821 if (count != td->max_frame_size) { 1822 if (count < td->max_frame_size) { 1823 /* we have a short packet */ 1824 td->short_pkt = 1; 1825 got_short = 1; 1826 } else { 1827 /* invalid USB packet */ 1828 td->error = 1; 1829 musbotg_channel_free(sc, td); 1830 return (0); /* we are complete */ 1831 } 1832 } 1833 1834 /* verify the packet byte count */ 1835 if (count > td->remainder) { 1836 /* invalid USB packet */ 1837 td->error = 1; 1838 musbotg_channel_free(sc, td); 1839 return (0); /* we are complete */ 1840 } 1841 1842 while (count > 0) { 1843 uint32_t temp; 1844 1845 usbd_get_page(td->pc, td->offset, &buf_res); 1846 1847 /* get correct length */ 1848 if (buf_res.length > count) { 1849 buf_res.length = count; 1850 } 1851 /* check for unaligned memory address */ 1852 if (USB_P2U(buf_res.buffer) & 3) { 1853 temp = count & ~3; 1854 1855 if (temp) { 1856 /* receive data 4 bytes at a time */ 1857 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1858 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf, 1859 temp / 4); 1860 } 1861 temp = count & 3; 1862 if (temp) { 1863 /* receive data 1 byte at a time */ 1864 bus_space_read_multi_1(sc->sc_io_tag, 1865 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 1866 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1867 } 1868 usbd_copy_in(td->pc, td->offset, 1869 sc->sc_bounce_buf, count); 1870 1871 /* update offset and remainder */ 1872 td->offset += count; 1873 td->remainder -= count; 1874 break; 1875 } 1876 /* check if we can optimise */ 1877 if (buf_res.length >= 4) { 1878 /* receive data 4 bytes at a time */ 1879 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1880 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1881 buf_res.length / 4); 1882 1883 temp = buf_res.length & ~3; 1884 1885 /* update counters */ 1886 count -= temp; 1887 td->offset += temp; 1888 td->remainder -= temp; 1889 continue; 1890 } 1891 /* receive data */ 1892 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1893 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1894 buf_res.length); 1895 1896 /* update counters */ 1897 count -= buf_res.length; 1898 td->offset += buf_res.length; 1899 td->remainder -= buf_res.length; 1900 } 1901 1902 /* clear status bits */ 1903 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1904 1905 /* check if we are complete */ 1906 if ((td->remainder == 0) || got_short) { 1907 if (td->short_pkt) { 1908 /* we are complete */ 1909 musbotg_channel_free(sc, td); 1910 return (0); 1911 } 1912 /* else need to receive a zero length packet */ 1913 } 1914 1915 /* Reset transaction state and restart */ 1916 td->transaction_started = 0; 1917 1918 if (--to) 1919 goto repeat; 1920 1921 return (1); /* not complete */ 1922} 1923 1924static uint8_t 1925musbotg_host_data_tx(struct musbotg_td *td) 1926{ 1927 struct usb_page_search buf_res; 1928 struct musbotg_softc *sc; 1929 uint16_t count; 1930 uint8_t csr, csrh; 1931 1932 /* get pointer to softc */ 1933 sc = MUSBOTG_PC2SC(td->pc); 1934 1935 if (td->channel == -1) 1936 td->channel = musbotg_channel_alloc(sc, td, 1); 1937 1938 /* No free EPs */ 1939 if (td->channel == -1) 1940 return (1); 1941 1942 DPRINTFN(1, "ep_no=%d\n", td->channel); 1943 1944 /* select endpoint */ 1945 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1946 1947 /* read out FIFO status */ 1948 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1949 DPRINTFN(4, "csr=0x%02x\n", csr); 1950 1951 if (csr & (MUSB2_MASK_CSRL_TXSTALLED | 1952 MUSB2_MASK_CSRL_TXERROR)) { 1953 /* clear status bits */ 1954 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1955 td->error = 1; 1956 musbotg_channel_free(sc, td); 1957 return (0); /* complete */ 1958 } 1959 1960 if (csr & MUSB2_MASK_CSRL_TXNAKTO) { 1961 /* 1962 * Flush TX FIFO before clearing NAK TO 1963 */ 1964 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1965 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 1966 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1967 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1968 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1969 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 1970 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1971 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1972 } 1973 } 1974 1975 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 1976 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1977 1978 td->error = 1; 1979 musbotg_channel_free(sc, td); 1980 return (0); /* complete */ 1981 } 1982 1983 /* 1984 * Wait while FIFO is empty. 1985 * Do not flush it because it will cause transactions 1986 * with size more then packet size. It might upset 1987 * some devices 1988 */ 1989 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) 1990 return (1); 1991 1992 /* Packet still being processed */ 1993 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) 1994 return (1); 1995 1996 if (td->transaction_started) { 1997 /* check remainder */ 1998 if (td->remainder == 0) { 1999 if (td->short_pkt) { 2000 musbotg_channel_free(sc, td); 2001 return (0); /* complete */ 2002 } 2003 /* else we need to transmit a short packet */ 2004 } 2005 2006 /* We're not complete - more transactions required */ 2007 td->transaction_started = 0; 2008 } 2009 2010 /* check for short packet */ 2011 count = td->max_frame_size; 2012 if (td->remainder < count) { 2013 /* we have a short packet */ 2014 td->short_pkt = 1; 2015 count = td->remainder; 2016 } 2017 2018 while (count > 0) { 2019 uint32_t temp; 2020 2021 usbd_get_page(td->pc, td->offset, &buf_res); 2022 2023 /* get correct length */ 2024 if (buf_res.length > count) { 2025 buf_res.length = count; 2026 } 2027 /* check for unaligned memory address */ 2028 if (USB_P2U(buf_res.buffer) & 3) { 2029 usbd_copy_out(td->pc, td->offset, 2030 sc->sc_bounce_buf, count); 2031 2032 temp = count & ~3; 2033 2034 if (temp) { 2035 /* transmit data 4 bytes at a time */ 2036 bus_space_write_multi_4(sc->sc_io_tag, 2037 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 2038 sc->sc_bounce_buf, temp / 4); 2039 } 2040 temp = count & 3; 2041 if (temp) { 2042 /* receive data 1 byte at a time */ 2043 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 2044 MUSB2_REG_EPFIFO(td->channel), 2045 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 2046 } 2047 /* update offset and remainder */ 2048 td->offset += count; 2049 td->remainder -= count; 2050 break; 2051 } 2052 /* check if we can optimise */ 2053 if (buf_res.length >= 4) { 2054 /* transmit data 4 bytes at a time */ 2055 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 2056 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 2057 buf_res.length / 4); 2058 2059 temp = buf_res.length & ~3; 2060 2061 /* update counters */ 2062 count -= temp; 2063 td->offset += temp; 2064 td->remainder -= temp; 2065 continue; 2066 } 2067 /* transmit data */ 2068 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 2069 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 2070 buf_res.length); 2071 2072 /* update counters */ 2073 count -= buf_res.length; 2074 td->offset += buf_res.length; 2075 td->remainder -= buf_res.length; 2076 } 2077 2078 /* Function address */ 2079 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(td->channel), 2080 td->dev_addr); 2081 2082 /* SPLIT transaction */ 2083 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(td->channel), 2084 td->haddr); 2085 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(td->channel), 2086 td->hport); 2087 2088 /* TX NAK timeout */ 2089 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC) 2090 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, 0); 2091 else 2092 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 2093 2094 /* Protocol, speed, device endpoint */ 2095 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 2096 2097 /* Max packet size */ 2098 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet); 2099 2100 if (!td->transaction_started) { 2101 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 2102 DPRINTFN(4, "csrh=0x%02x\n", csrh); 2103 2104 csrh |= MUSB2_MASK_CSRH_TXDT_WREN; 2105 if (td->toggle) 2106 csrh |= MUSB2_MASK_CSRH_TXDT_VAL; 2107 else 2108 csrh &= ~MUSB2_MASK_CSRH_TXDT_VAL; 2109 2110 /* Set data toggle */ 2111 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 2112 } 2113 2114 /* write command */ 2115 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2116 MUSB2_MASK_CSRL_TXPKTRDY); 2117 2118 /* Update Data Toggle */ 2119 td->toggle ^= 1; 2120 td->transaction_started = 1; 2121 2122 return (1); /* not complete */ 2123} 2124 2125static uint8_t 2126musbotg_xfer_do_fifo(struct usb_xfer *xfer) 2127{ 2128 struct musbotg_td *td; 2129 2130 DPRINTFN(8, "\n"); 2131 td = xfer->td_transfer_cache; 2132 while (1) { 2133 if ((td->func) (td)) { 2134 /* operation in progress */ 2135 break; 2136 } 2137 2138 if (((void *)td) == xfer->td_transfer_last) { 2139 goto done; 2140 } 2141 if (td->error) { 2142 goto done; 2143 } else if (td->remainder > 0) { 2144 /* 2145 * We had a short transfer. If there is no alternate 2146 * next, stop processing ! 2147 */ 2148 if (!td->alt_next) { 2149 goto done; 2150 } 2151 } 2152 /* 2153 * Fetch the next transfer descriptor and transfer 2154 * some flags to the next transfer descriptor 2155 */ 2156 td = td->obj_next; 2157 xfer->td_transfer_cache = td; 2158 } 2159 2160 return (1); /* not complete */ 2161done: 2162 /* compute all actual lengths */ 2163 musbotg_standard_done(xfer); 2164 2165 return (0); /* complete */ 2166} 2167 2168static void 2169musbotg_interrupt_poll(struct musbotg_softc *sc) 2170{ 2171 struct usb_xfer *xfer; 2172 2173repeat: 2174 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2175 if (!musbotg_xfer_do_fifo(xfer)) { 2176 /* queue has been modified */ 2177 goto repeat; 2178 } 2179 } 2180} 2181 2182void 2183musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on) 2184{ 2185 DPRINTFN(4, "vbus = %u\n", is_on); 2186 2187 USB_BUS_LOCK(&sc->sc_bus); 2188 if (is_on) { 2189 if (!sc->sc_flags.status_vbus) { 2190 sc->sc_flags.status_vbus = 1; 2191 2192 /* complete root HUB interrupt endpoint */ 2193 musbotg_root_intr(sc); 2194 } 2195 } else { 2196 if (sc->sc_flags.status_vbus) { 2197 sc->sc_flags.status_vbus = 0; 2198 sc->sc_flags.status_bus_reset = 0; 2199 sc->sc_flags.status_suspend = 0; 2200 sc->sc_flags.change_suspend = 0; 2201 sc->sc_flags.change_connect = 1; 2202 2203 /* complete root HUB interrupt endpoint */ 2204 musbotg_root_intr(sc); 2205 } 2206 } 2207 2208 USB_BUS_UNLOCK(&sc->sc_bus); 2209} 2210 2211void 2212musbotg_connect_interrupt(struct musbotg_softc *sc) 2213{ 2214 USB_BUS_LOCK(&sc->sc_bus); 2215 sc->sc_flags.change_connect = 1; 2216 2217 /* complete root HUB interrupt endpoint */ 2218 musbotg_root_intr(sc); 2219 USB_BUS_UNLOCK(&sc->sc_bus); 2220} 2221 2222void 2223musbotg_interrupt(struct musbotg_softc *sc, 2224 uint16_t rxstat, uint16_t txstat, uint8_t stat) 2225{ 2226 uint16_t rx_status; 2227 uint16_t tx_status; 2228 uint8_t usb_status; 2229 uint8_t temp; 2230 uint8_t to = 2; 2231 2232 USB_BUS_LOCK(&sc->sc_bus); 2233 2234repeat: 2235 2236 /* read all interrupt registers */ 2237 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB); 2238 2239 /* read all FIFO interrupts */ 2240 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX); 2241 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX); 2242 rx_status |= rxstat; 2243 tx_status |= txstat; 2244 usb_status |= stat; 2245 2246 /* Clear platform flags after first time */ 2247 rxstat = 0; 2248 txstat = 0; 2249 stat = 0; 2250 2251 /* check for any bus state change interrupts */ 2252 2253 if (usb_status & (MUSB2_MASK_IRESET | 2254 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP | 2255 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC | 2256 MUSB2_MASK_IVBUSERR)) { 2257 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status); 2258 2259 if (usb_status & MUSB2_MASK_IRESET) { 2260 /* set correct state */ 2261 sc->sc_flags.status_bus_reset = 1; 2262 sc->sc_flags.status_suspend = 0; 2263 sc->sc_flags.change_suspend = 0; 2264 sc->sc_flags.change_connect = 1; 2265 2266 /* determine line speed */ 2267 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 2268 if (temp & MUSB2_MASK_HSMODE) 2269 sc->sc_flags.status_high_speed = 1; 2270 else 2271 sc->sc_flags.status_high_speed = 0; 2272 2273 /* 2274 * After reset all interrupts are on and we need to 2275 * turn them off! 2276 */ 2277 temp = MUSB2_MASK_IRESET; 2278 /* disable resume interrupt */ 2279 temp &= ~MUSB2_MASK_IRESUME; 2280 /* enable suspend interrupt */ 2281 temp |= MUSB2_MASK_ISUSP; 2282 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 2283 /* disable TX and RX interrupts */ 2284 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 2285 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 2286 } 2287 /* 2288 * If RXRSM and RXSUSP is set at the same time we interpret 2289 * that like RESUME. Resume is set when there is at least 3 2290 * milliseconds of inactivity on the USB BUS. 2291 */ 2292 if (usb_status & MUSB2_MASK_IRESUME) { 2293 if (sc->sc_flags.status_suspend) { 2294 sc->sc_flags.status_suspend = 0; 2295 sc->sc_flags.change_suspend = 1; 2296 2297 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 2298 /* disable resume interrupt */ 2299 temp &= ~MUSB2_MASK_IRESUME; 2300 /* enable suspend interrupt */ 2301 temp |= MUSB2_MASK_ISUSP; 2302 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 2303 } 2304 } else if (usb_status & MUSB2_MASK_ISUSP) { 2305 if (!sc->sc_flags.status_suspend) { 2306 sc->sc_flags.status_suspend = 1; 2307 sc->sc_flags.change_suspend = 1; 2308 2309 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 2310 /* disable suspend interrupt */ 2311 temp &= ~MUSB2_MASK_ISUSP; 2312 /* enable resume interrupt */ 2313 temp |= MUSB2_MASK_IRESUME; 2314 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 2315 } 2316 } 2317 if (usb_status & 2318 (MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) 2319 sc->sc_flags.change_connect = 1; 2320 2321 /* 2322 * Host Mode: There is no IRESET so assume bus is 2323 * always in reset state once device is connected. 2324 */ 2325 if (sc->sc_mode == MUSB2_HOST_MODE) { 2326 /* check for VBUS error in USB host mode */ 2327 if (usb_status & MUSB2_MASK_IVBUSERR) { 2328 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 2329 temp |= MUSB2_MASK_SESS; 2330 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 2331 } 2332 if (usb_status & MUSB2_MASK_ICONN) 2333 sc->sc_flags.status_bus_reset = 1; 2334 if (usb_status & MUSB2_MASK_IDISC) 2335 sc->sc_flags.status_bus_reset = 0; 2336 } 2337 2338 /* complete root HUB interrupt endpoint */ 2339 musbotg_root_intr(sc); 2340 } 2341 /* check for any endpoint interrupts */ 2342 2343 if (rx_status || tx_status) { 2344 DPRINTFN(4, "real endpoint interrupt " 2345 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status); 2346 } 2347 /* poll one time regardless of FIFO status */ 2348 2349 musbotg_interrupt_poll(sc); 2350 2351 if (--to) 2352 goto repeat; 2353 2354 USB_BUS_UNLOCK(&sc->sc_bus); 2355} 2356 2357static void 2358musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp) 2359{ 2360 struct musbotg_td *td; 2361 2362 /* get current Transfer Descriptor */ 2363 td = temp->td_next; 2364 temp->td = td; 2365 2366 /* prepare for next TD */ 2367 temp->td_next = td->obj_next; 2368 2369 /* fill out the Transfer Descriptor */ 2370 td->func = temp->func; 2371 td->pc = temp->pc; 2372 td->offset = temp->offset; 2373 td->remainder = temp->len; 2374 td->error = 0; 2375 td->transaction_started = 0; 2376 td->did_stall = temp->did_stall; 2377 td->short_pkt = temp->short_pkt; 2378 td->alt_next = temp->setup_alt_next; 2379 td->channel = temp->channel; 2380 td->dev_addr = temp->dev_addr; 2381 td->haddr = temp->haddr; 2382 td->hport = temp->hport; 2383 td->transfer_type = temp->transfer_type; 2384} 2385 2386static void 2387musbotg_setup_standard_chain(struct usb_xfer *xfer) 2388{ 2389 struct musbotg_std_temp temp; 2390 struct musbotg_softc *sc; 2391 struct musbotg_td *td; 2392 uint32_t x; 2393 uint8_t ep_no; 2394 uint8_t xfer_type; 2395 enum usb_dev_speed speed; 2396 int tx; 2397 int dev_addr; 2398 2399 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n", 2400 xfer->address, UE_GET_ADDR(xfer->endpointno), 2401 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 2402 2403 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2404 ep_no = (xfer->endpointno & UE_ADDR); 2405 2406 temp.max_frame_size = xfer->max_frame_size; 2407 2408 td = xfer->td_start[0]; 2409 xfer->td_transfer_first = td; 2410 xfer->td_transfer_cache = td; 2411 2412 /* setup temp */ 2413 dev_addr = xfer->address; 2414 2415 xfer_type = xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE; 2416 2417 temp.pc = NULL; 2418 temp.td = NULL; 2419 temp.td_next = xfer->td_start[0]; 2420 temp.offset = 0; 2421 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 2422 xfer->flags_int.isochronous_xfr; 2423 temp.did_stall = !xfer->flags_int.control_stall; 2424 temp.channel = -1; 2425 temp.dev_addr = dev_addr; 2426 temp.haddr = xfer->xroot->udev->hs_hub_addr; 2427 temp.hport = xfer->xroot->udev->hs_port_no; 2428 2429 if (xfer->flags_int.usb_mode == USB_MODE_HOST) { 2430 speed = usbd_get_speed(xfer->xroot->udev); 2431 2432 switch (speed) { 2433 case USB_SPEED_LOW: 2434 temp.transfer_type = MUSB2_MASK_TI_SPEED_LO; 2435 break; 2436 case USB_SPEED_FULL: 2437 temp.transfer_type = MUSB2_MASK_TI_SPEED_FS; 2438 break; 2439 case USB_SPEED_HIGH: 2440 temp.transfer_type = MUSB2_MASK_TI_SPEED_HS; 2441 break; 2442 default: 2443 temp.transfer_type = 0; 2444 DPRINTFN(-1, "Invalid USB speed: %d\n", speed); 2445 break; 2446 } 2447 2448 switch (xfer_type) { 2449 case UE_CONTROL: 2450 temp.transfer_type |= MUSB2_MASK_TI_PROTO_CTRL; 2451 break; 2452 case UE_ISOCHRONOUS: 2453 temp.transfer_type |= MUSB2_MASK_TI_PROTO_ISOC; 2454 break; 2455 case UE_BULK: 2456 temp.transfer_type |= MUSB2_MASK_TI_PROTO_BULK; 2457 break; 2458 case UE_INTERRUPT: 2459 temp.transfer_type |= MUSB2_MASK_TI_PROTO_INTR; 2460 break; 2461 default: 2462 DPRINTFN(-1, "Invalid USB transfer type: %d\n", 2463 xfer_type); 2464 break; 2465 } 2466 2467 temp.transfer_type |= ep_no; 2468 td->toggle = xfer->endpoint->toggle_next; 2469 } 2470 2471 /* check if we should prepend a setup message */ 2472 2473 if (xfer->flags_int.control_xfr) { 2474 if (xfer->flags_int.control_hdr) { 2475 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) 2476 temp.func = &musbotg_dev_ctrl_setup_rx; 2477 else 2478 temp.func = &musbotg_host_ctrl_setup_tx; 2479 2480 temp.len = xfer->frlengths[0]; 2481 temp.pc = xfer->frbuffers + 0; 2482 temp.short_pkt = temp.len ? 1 : 0; 2483 2484 musbotg_setup_standard_chain_sub(&temp); 2485 } 2486 x = 1; 2487 } else { 2488 x = 0; 2489 } 2490 2491 tx = 0; 2492 2493 if (x != xfer->nframes) { 2494 if (xfer->endpointno & UE_DIR_IN) 2495 tx = 1; 2496 2497 if (xfer->flags_int.usb_mode == USB_MODE_HOST) { 2498 tx = !tx; 2499 2500 if (tx) { 2501 if (xfer->flags_int.control_xfr) 2502 temp.func = &musbotg_host_ctrl_data_tx; 2503 else 2504 temp.func = &musbotg_host_data_tx; 2505 } else { 2506 if (xfer->flags_int.control_xfr) 2507 temp.func = &musbotg_host_ctrl_data_rx; 2508 else 2509 temp.func = &musbotg_host_data_rx; 2510 } 2511 2512 } else { 2513 if (tx) { 2514 if (xfer->flags_int.control_xfr) 2515 temp.func = &musbotg_dev_ctrl_data_tx; 2516 else 2517 temp.func = &musbotg_dev_data_tx; 2518 } else { 2519 if (xfer->flags_int.control_xfr) 2520 temp.func = &musbotg_dev_ctrl_data_rx; 2521 else 2522 temp.func = &musbotg_dev_data_rx; 2523 } 2524 } 2525 2526 /* setup "pc" pointer */ 2527 temp.pc = xfer->frbuffers + x; 2528 } 2529 while (x != xfer->nframes) { 2530 /* DATA0 / DATA1 message */ 2531 2532 temp.len = xfer->frlengths[x]; 2533 2534 x++; 2535 2536 if (x == xfer->nframes) { 2537 if (xfer->flags_int.control_xfr) { 2538 if (xfer->flags_int.control_act) { 2539 temp.setup_alt_next = 0; 2540 } 2541 } else { 2542 temp.setup_alt_next = 0; 2543 } 2544 } 2545 if (temp.len == 0) { 2546 /* make sure that we send an USB packet */ 2547 2548 temp.short_pkt = 0; 2549 2550 } else { 2551 if (xfer->flags_int.isochronous_xfr) { 2552 /* isochronous data transfer */ 2553 /* don't force short */ 2554 temp.short_pkt = 1; 2555 } else { 2556 /* regular data transfer */ 2557 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 2558 } 2559 } 2560 2561 musbotg_setup_standard_chain_sub(&temp); 2562 2563 if (xfer->flags_int.isochronous_xfr) { 2564 temp.offset += temp.len; 2565 } else { 2566 /* get next Page Cache pointer */ 2567 temp.pc = xfer->frbuffers + x; 2568 } 2569 } 2570 2571 /* check for control transfer */ 2572 if (xfer->flags_int.control_xfr) { 2573 /* always setup a valid "pc" pointer for status and sync */ 2574 temp.pc = xfer->frbuffers + 0; 2575 temp.len = 0; 2576 temp.short_pkt = 0; 2577 temp.setup_alt_next = 0; 2578 2579 /* check if we should append a status stage */ 2580 if (!xfer->flags_int.control_act) { 2581 /* 2582 * Send a DATA1 message and invert the current 2583 * endpoint direction. 2584 */ 2585 if (sc->sc_mode == MUSB2_DEVICE_MODE) 2586 temp.func = &musbotg_dev_ctrl_status; 2587 else { 2588 if (xfer->endpointno & UE_DIR_IN) 2589 temp.func = musbotg_host_ctrl_status_tx; 2590 else 2591 temp.func = musbotg_host_ctrl_status_rx; 2592 } 2593 musbotg_setup_standard_chain_sub(&temp); 2594 } 2595 } 2596 /* must have at least one frame! */ 2597 td = temp.td; 2598 xfer->td_transfer_last = td; 2599} 2600 2601static void 2602musbotg_timeout(void *arg) 2603{ 2604 struct usb_xfer *xfer = arg; 2605 2606 DPRINTFN(1, "xfer=%p\n", xfer); 2607 2608 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 2609 2610 /* transfer is transferred */ 2611 musbotg_device_done(xfer, USB_ERR_TIMEOUT); 2612} 2613 2614static void 2615musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on) 2616{ 2617 uint16_t temp; 2618 2619 /* 2620 * Only enable the endpoint interrupt when we are 2621 * actually waiting for data, hence we are dealing 2622 * with level triggered interrupts ! 2623 */ 2624 DPRINTFN(1, "ep_no=%d, on=%d\n", channel, on); 2625 2626 if (channel == -1) 2627 return; 2628 2629 if (channel == 0) { 2630 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 2631 if (on) 2632 temp |= MUSB2_MASK_EPINT(0); 2633 else 2634 temp &= ~MUSB2_MASK_EPINT(0); 2635 2636 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 2637 } else { 2638 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE); 2639 if (on) 2640 temp |= MUSB2_MASK_EPINT(channel); 2641 else 2642 temp &= ~MUSB2_MASK_EPINT(channel); 2643 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp); 2644 2645 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 2646 if (on) 2647 temp |= MUSB2_MASK_EPINT(channel); 2648 else 2649 temp &= ~MUSB2_MASK_EPINT(channel); 2650 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 2651 } 2652 2653 if (sc->sc_ep_int_set) 2654 sc->sc_ep_int_set(sc, channel, on); 2655} 2656 2657static void 2658musbotg_start_standard_chain(struct usb_xfer *xfer) 2659{ 2660 DPRINTFN(8, "\n"); 2661 2662 /* poll one time */ 2663 if (musbotg_xfer_do_fifo(xfer)) { 2664 DPRINTFN(14, "enabled interrupts on endpoint\n"); 2665 2666 /* put transfer on interrupt queue */ 2667 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 2668 2669 /* start timeout, if any */ 2670 if (xfer->timeout != 0) { 2671 usbd_transfer_timeout_ms(xfer, 2672 &musbotg_timeout, xfer->timeout); 2673 } 2674 } 2675} 2676 2677static void 2678musbotg_root_intr(struct musbotg_softc *sc) 2679{ 2680 DPRINTFN(8, "\n"); 2681 2682 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2683 2684 /* set port bit */ 2685 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 2686 2687 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2688 sizeof(sc->sc_hub_idata)); 2689} 2690 2691static usb_error_t 2692musbotg_standard_done_sub(struct usb_xfer *xfer) 2693{ 2694 struct musbotg_td *td; 2695 uint32_t len; 2696 uint8_t error; 2697 2698 DPRINTFN(8, "\n"); 2699 2700 td = xfer->td_transfer_cache; 2701 2702 do { 2703 len = td->remainder; 2704 2705 xfer->endpoint->toggle_next = td->toggle; 2706 2707 if (xfer->aframes != xfer->nframes) { 2708 /* 2709 * Verify the length and subtract 2710 * the remainder from "frlengths[]": 2711 */ 2712 if (len > xfer->frlengths[xfer->aframes]) { 2713 td->error = 1; 2714 } else { 2715 xfer->frlengths[xfer->aframes] -= len; 2716 } 2717 } 2718 /* Check for transfer error */ 2719 if (td->error) { 2720 /* the transfer is finished */ 2721 error = 1; 2722 td = NULL; 2723 break; 2724 } 2725 /* Check for short transfer */ 2726 if (len > 0) { 2727 if (xfer->flags_int.short_frames_ok || 2728 xfer->flags_int.isochronous_xfr) { 2729 /* follow alt next */ 2730 if (td->alt_next) { 2731 td = td->obj_next; 2732 } else { 2733 td = NULL; 2734 } 2735 } else { 2736 /* the transfer is finished */ 2737 td = NULL; 2738 } 2739 error = 0; 2740 break; 2741 } 2742 td = td->obj_next; 2743 2744 /* this USB frame is complete */ 2745 error = 0; 2746 break; 2747 2748 } while (0); 2749 2750 /* update transfer cache */ 2751 2752 xfer->td_transfer_cache = td; 2753 2754 return (error ? 2755 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 2756} 2757 2758static void 2759musbotg_standard_done(struct usb_xfer *xfer) 2760{ 2761 usb_error_t err = 0; 2762 2763 DPRINTFN(12, "xfer=%p endpoint=%p transfer done\n", 2764 xfer, xfer->endpoint); 2765 2766 /* reset scanner */ 2767 2768 xfer->td_transfer_cache = xfer->td_transfer_first; 2769 2770 if (xfer->flags_int.control_xfr) { 2771 if (xfer->flags_int.control_hdr) { 2772 err = musbotg_standard_done_sub(xfer); 2773 } 2774 xfer->aframes = 1; 2775 2776 if (xfer->td_transfer_cache == NULL) { 2777 goto done; 2778 } 2779 } 2780 while (xfer->aframes != xfer->nframes) { 2781 err = musbotg_standard_done_sub(xfer); 2782 xfer->aframes++; 2783 2784 if (xfer->td_transfer_cache == NULL) { 2785 goto done; 2786 } 2787 } 2788 2789 if (xfer->flags_int.control_xfr && 2790 !xfer->flags_int.control_act) { 2791 err = musbotg_standard_done_sub(xfer); 2792 } 2793done: 2794 musbotg_device_done(xfer, err); 2795} 2796 2797/*------------------------------------------------------------------------* 2798 * musbotg_device_done 2799 * 2800 * NOTE: this function can be called more than one time on the 2801 * same USB transfer! 2802 *------------------------------------------------------------------------*/ 2803static void 2804musbotg_device_done(struct usb_xfer *xfer, usb_error_t error) 2805{ 2806 struct musbotg_td *td; 2807 struct musbotg_softc *sc; 2808 2809 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 2810 2811 DPRINTFN(1, "xfer=%p, endpoint=%p, error=%d\n", 2812 xfer, xfer->endpoint, error); 2813 2814 DPRINTFN(14, "disabled interrupts on endpoint\n"); 2815 2816 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2817 td = xfer->td_transfer_cache; 2818 2819 if (td && (td->channel != -1)) 2820 musbotg_channel_free(sc, td); 2821 2822 /* dequeue transfer and start next transfer */ 2823 usbd_transfer_done(xfer, error); 2824} 2825 2826static void 2827musbotg_xfer_stall(struct usb_xfer *xfer) 2828{ 2829 musbotg_device_done(xfer, USB_ERR_STALLED); 2830} 2831 2832static void 2833musbotg_set_stall(struct usb_device *udev, 2834 struct usb_endpoint *ep, uint8_t *did_stall) 2835{ 2836 struct musbotg_softc *sc; 2837 uint8_t ep_no; 2838 2839 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 2840 2841 DPRINTFN(4, "endpoint=%p\n", ep); 2842 2843 /* set FORCESTALL */ 2844 sc = MUSBOTG_BUS2SC(udev->bus); 2845 2846 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR); 2847 2848 /* select endpoint */ 2849 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 2850 2851 if (ep->edesc->bEndpointAddress & UE_DIR_IN) { 2852 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2853 MUSB2_MASK_CSRL_TXSENDSTALL); 2854 } else { 2855 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2856 MUSB2_MASK_CSRL_RXSENDSTALL); 2857 } 2858} 2859 2860static void 2861musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket, 2862 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 2863{ 2864 uint16_t mps; 2865 uint16_t temp; 2866 uint8_t csr; 2867 2868 if (ep_type == UE_CONTROL) { 2869 /* clearing stall is not needed */ 2870 return; 2871 } 2872 /* select endpoint */ 2873 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 2874 2875 /* compute max frame size */ 2876 mps = wMaxPacket & 0x7FF; 2877 switch ((wMaxPacket >> 11) & 3) { 2878 case 1: 2879 mps *= 2; 2880 break; 2881 case 2: 2882 mps *= 3; 2883 break; 2884 default: 2885 break; 2886 } 2887 2888 if (ep_dir == UE_DIR_IN) { 2889 temp = 0; 2890 2891 /* Configure endpoint */ 2892 switch (ep_type) { 2893 case UE_INTERRUPT: 2894 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 2895 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 2896 MUSB2_MASK_CSRH_TXMODE | temp); 2897 break; 2898 case UE_ISOCHRONOUS: 2899 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 2900 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 2901 MUSB2_MASK_CSRH_TXMODE | 2902 MUSB2_MASK_CSRH_TXISO | temp); 2903 break; 2904 case UE_BULK: 2905 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 2906 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 2907 MUSB2_MASK_CSRH_TXMODE | temp); 2908 break; 2909 default: 2910 break; 2911 } 2912 2913 /* Need to flush twice in case of double bufring */ 2914 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2915 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2916 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2917 MUSB2_MASK_CSRL_TXFFLUSH); 2918 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2919 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2920 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2921 MUSB2_MASK_CSRL_TXFFLUSH); 2922 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2923 } 2924 } 2925 /* reset data toggle */ 2926 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2927 MUSB2_MASK_CSRL_TXDT_CLR); 2928 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 2929 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2930 2931 /* set double/single buffering */ 2932 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS); 2933 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 2934 max_in_frame_size / 2)) { 2935 /* double buffer */ 2936 temp &= ~(1 << ep_no); 2937 } else { 2938 /* single buffer */ 2939 temp |= (1 << ep_no); 2940 } 2941 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp); 2942 2943 /* clear sent stall */ 2944 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) { 2945 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 2946 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2947 } 2948 } else { 2949 temp = 0; 2950 2951 /* Configure endpoint */ 2952 switch (ep_type) { 2953 case UE_INTERRUPT: 2954 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 2955 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 2956 MUSB2_MASK_CSRH_RXNYET | temp); 2957 break; 2958 case UE_ISOCHRONOUS: 2959 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 2960 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 2961 MUSB2_MASK_CSRH_RXNYET | 2962 MUSB2_MASK_CSRH_RXISO | temp); 2963 break; 2964 case UE_BULK: 2965 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 2966 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp); 2967 break; 2968 default: 2969 break; 2970 } 2971 2972 /* Need to flush twice in case of double bufring */ 2973 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 2974 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2975 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2976 MUSB2_MASK_CSRL_RXFFLUSH); 2977 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 2978 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2979 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2980 MUSB2_MASK_CSRL_RXFFLUSH); 2981 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 2982 } 2983 } 2984 /* reset data toggle */ 2985 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2986 MUSB2_MASK_CSRL_RXDT_CLR); 2987 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 2988 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 2989 2990 /* set double/single buffering */ 2991 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS); 2992 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 2993 max_out_frame_size / 2)) { 2994 /* double buffer */ 2995 temp &= ~(1 << ep_no); 2996 } else { 2997 /* single buffer */ 2998 temp |= (1 << ep_no); 2999 } 3000 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp); 3001 3002 /* clear sent stall */ 3003 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) { 3004 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 3005 } 3006 } 3007} 3008 3009static void 3010musbotg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3011{ 3012 struct musbotg_softc *sc; 3013 struct usb_endpoint_descriptor *ed; 3014 3015 DPRINTFN(4, "endpoint=%p\n", ep); 3016 3017 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3018 3019 /* check mode */ 3020 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3021 /* not supported */ 3022 return; 3023 } 3024 /* get softc */ 3025 sc = MUSBOTG_BUS2SC(udev->bus); 3026 3027 /* get endpoint descriptor */ 3028 ed = ep->edesc; 3029 3030 /* reset endpoint */ 3031 musbotg_clear_stall_sub(sc, 3032 UGETW(ed->wMaxPacketSize), 3033 (ed->bEndpointAddress & UE_ADDR), 3034 (ed->bmAttributes & UE_XFERTYPE), 3035 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 3036} 3037 3038usb_error_t 3039musbotg_init(struct musbotg_softc *sc) 3040{ 3041 const struct musb_otg_ep_cfg *cfg; 3042 struct usb_hw_ep_profile *pf; 3043 int i; 3044 uint16_t offset; 3045 uint8_t nrx; 3046 uint8_t ntx; 3047 uint8_t temp; 3048 uint8_t fsize; 3049 uint8_t frx; 3050 uint8_t ftx; 3051 uint8_t dynfifo; 3052 3053 DPRINTFN(1, "start\n"); 3054 3055 /* set up the bus structure */ 3056 sc->sc_bus.usbrev = USB_REV_2_0; 3057 sc->sc_bus.methods = &musbotg_bus_methods; 3058 3059 /* Set a default endpoint configuration */ 3060 if (sc->sc_ep_cfg == NULL) 3061 sc->sc_ep_cfg = musbotg_ep_default; 3062 3063 USB_BUS_LOCK(&sc->sc_bus); 3064 3065 /* turn on clocks */ 3066 3067 if (sc->sc_clocks_on) { 3068 (sc->sc_clocks_on) (sc->sc_clocks_arg); 3069 } 3070 3071 /* wait a little for things to stabilise */ 3072 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 3073 3074 /* disable all interrupts */ 3075 3076 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 3077 DPRINTF("pre-DEVCTL=0x%02x\n", temp); 3078 3079 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 3080 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 3081 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 3082 3083 /* disable pullup */ 3084 3085 musbotg_pull_common(sc, 0); 3086 3087 /* wait a little bit (10ms) */ 3088 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3089 3090 /* disable double packet buffering */ 3091 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 3092 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 3093 3094 /* enable HighSpeed and ISO Update flags */ 3095 3096 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, 3097 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 3098 3099 if (sc->sc_mode == MUSB2_DEVICE_MODE) { 3100 /* clear Session bit, if set */ 3101 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 3102 temp &= ~MUSB2_MASK_SESS; 3103 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 3104 } else { 3105 /* Enter session for Host mode */ 3106 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 3107 temp |= MUSB2_MASK_SESS; 3108 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 3109 } 3110 3111 /* wait a little for things to stabilise */ 3112 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); 3113 3114 DPRINTF("DEVCTL=0x%02x\n", temp); 3115 3116 /* disable testmode */ 3117 3118 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0); 3119 3120 /* set default value */ 3121 3122 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0); 3123 3124 /* select endpoint index 0 */ 3125 3126 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 3127 3128 if (sc->sc_ep_max == 0) { 3129 /* read out number of endpoints */ 3130 3131 nrx = 3132 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16); 3133 3134 ntx = 3135 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16); 3136 3137 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx; 3138 } else { 3139 nrx = ntx = sc->sc_ep_max; 3140 } 3141 3142 /* these numbers exclude the control endpoint */ 3143 3144 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx); 3145 3146 if (sc->sc_ep_max == 0) { 3147 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n"); 3148 } 3149 /* read out configuration data */ 3150 3151 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA); 3152 3153 DPRINTFN(2, "Config Data: 0x%02x\n", 3154 sc->sc_conf_data); 3155 3156 dynfifo = (sc->sc_conf_data & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0; 3157 3158 if (dynfifo) { 3159 device_printf(sc->sc_bus.bdev, "Dynamic FIFO sizing detected, " 3160 "assuming 16Kbytes of FIFO RAM\n"); 3161 } 3162 3163 DPRINTFN(2, "HW version: 0x%04x\n", 3164 MUSB2_READ_1(sc, MUSB2_REG_HWVERS)); 3165 3166 /* initialise endpoint profiles */ 3167 3168 offset = 0; 3169 3170 for (temp = 1; temp <= sc->sc_ep_max; temp++) { 3171 pf = sc->sc_hw_ep_profile + temp; 3172 3173 /* select endpoint */ 3174 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp); 3175 3176 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE); 3177 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16; 3178 ftx = (fsize & MUSB2_MASK_TX_FSIZE); 3179 3180 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n", 3181 temp, ftx, frx, dynfifo); 3182 3183 if (dynfifo) { 3184 if (frx && (temp <= nrx)) { 3185 for (i = 0; sc->sc_ep_cfg[i].ep_end >= 0; i++) { 3186 cfg = &sc->sc_ep_cfg[i]; 3187 if (temp <= cfg->ep_end) { 3188 frx = cfg->ep_fifosz_shift; 3189 MUSB2_WRITE_1(sc, 3190 MUSB2_REG_RXFIFOSZ, 3191 cfg->ep_fifosz_reg); 3192 break; 3193 } 3194 } 3195 3196 MUSB2_WRITE_2(sc, MUSB2_REG_RXFIFOADD, 3197 offset >> 3); 3198 3199 offset += (1 << frx); 3200 } 3201 if (ftx && (temp <= ntx)) { 3202 for (i = 0; sc->sc_ep_cfg[i].ep_end >= 0; i++) { 3203 cfg = &sc->sc_ep_cfg[i]; 3204 if (temp <= cfg->ep_end) { 3205 ftx = cfg->ep_fifosz_shift; 3206 MUSB2_WRITE_1(sc, 3207 MUSB2_REG_TXFIFOSZ, 3208 cfg->ep_fifosz_reg); 3209 break; 3210 } 3211 } 3212 3213 MUSB2_WRITE_2(sc, MUSB2_REG_TXFIFOADD, 3214 offset >> 3); 3215 3216 offset += (1 << ftx); 3217 } 3218 } 3219 3220 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) { 3221 pf->max_in_frame_size = 1 << ftx; 3222 pf->max_out_frame_size = 1 << frx; 3223 pf->is_simplex = 0; /* duplex */ 3224 pf->support_multi_buffer = 1; 3225 pf->support_bulk = 1; 3226 pf->support_interrupt = 1; 3227 pf->support_isochronous = 1; 3228 pf->support_in = 1; 3229 pf->support_out = 1; 3230 } else if (frx && (temp <= nrx)) { 3231 pf->max_out_frame_size = 1 << frx; 3232 pf->max_in_frame_size = 0; 3233 pf->is_simplex = 1; /* simplex */ 3234 pf->support_multi_buffer = 1; 3235 pf->support_bulk = 1; 3236 pf->support_interrupt = 1; 3237 pf->support_isochronous = 1; 3238 pf->support_out = 1; 3239 } else if (ftx && (temp <= ntx)) { 3240 pf->max_in_frame_size = 1 << ftx; 3241 pf->max_out_frame_size = 0; 3242 pf->is_simplex = 1; /* simplex */ 3243 pf->support_multi_buffer = 1; 3244 pf->support_bulk = 1; 3245 pf->support_interrupt = 1; 3246 pf->support_isochronous = 1; 3247 pf->support_in = 1; 3248 } 3249 } 3250 3251 DPRINTFN(2, "Dynamic FIFO size = %d bytes\n", offset); 3252 3253 /* turn on default interrupts */ 3254 3255 if (sc->sc_mode == MUSB2_HOST_MODE) 3256 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0xff); 3257 else 3258 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 3259 MUSB2_MASK_IRESET); 3260 3261 musbotg_clocks_off(sc); 3262 3263 USB_BUS_UNLOCK(&sc->sc_bus); 3264 3265 /* catch any lost interrupts */ 3266 3267 musbotg_do_poll(&sc->sc_bus); 3268 3269 return (0); /* success */ 3270} 3271 3272void 3273musbotg_uninit(struct musbotg_softc *sc) 3274{ 3275 USB_BUS_LOCK(&sc->sc_bus); 3276 3277 /* disable all interrupts */ 3278 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 3279 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 3280 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 3281 3282 sc->sc_flags.port_powered = 0; 3283 sc->sc_flags.status_vbus = 0; 3284 sc->sc_flags.status_bus_reset = 0; 3285 sc->sc_flags.status_suspend = 0; 3286 sc->sc_flags.change_suspend = 0; 3287 sc->sc_flags.change_connect = 1; 3288 3289 musbotg_pull_down(sc); 3290 musbotg_clocks_off(sc); 3291 USB_BUS_UNLOCK(&sc->sc_bus); 3292} 3293 3294static void 3295musbotg_do_poll(struct usb_bus *bus) 3296{ 3297 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 3298 3299 USB_BUS_LOCK(&sc->sc_bus); 3300 musbotg_interrupt_poll(sc); 3301 USB_BUS_UNLOCK(&sc->sc_bus); 3302} 3303 3304/*------------------------------------------------------------------------* 3305 * musbotg bulk support 3306 *------------------------------------------------------------------------*/ 3307static void 3308musbotg_device_bulk_open(struct usb_xfer *xfer) 3309{ 3310 return; 3311} 3312 3313static void 3314musbotg_device_bulk_close(struct usb_xfer *xfer) 3315{ 3316 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3317} 3318 3319static void 3320musbotg_device_bulk_enter(struct usb_xfer *xfer) 3321{ 3322 return; 3323} 3324 3325static void 3326musbotg_device_bulk_start(struct usb_xfer *xfer) 3327{ 3328 /* setup TDs */ 3329 musbotg_setup_standard_chain(xfer); 3330 musbotg_start_standard_chain(xfer); 3331} 3332 3333static const struct usb_pipe_methods musbotg_device_bulk_methods = 3334{ 3335 .open = musbotg_device_bulk_open, 3336 .close = musbotg_device_bulk_close, 3337 .enter = musbotg_device_bulk_enter, 3338 .start = musbotg_device_bulk_start, 3339}; 3340 3341/*------------------------------------------------------------------------* 3342 * musbotg control support 3343 *------------------------------------------------------------------------*/ 3344static void 3345musbotg_device_ctrl_open(struct usb_xfer *xfer) 3346{ 3347 return; 3348} 3349 3350static void 3351musbotg_device_ctrl_close(struct usb_xfer *xfer) 3352{ 3353 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3354} 3355 3356static void 3357musbotg_device_ctrl_enter(struct usb_xfer *xfer) 3358{ 3359 return; 3360} 3361 3362static void 3363musbotg_device_ctrl_start(struct usb_xfer *xfer) 3364{ 3365 /* setup TDs */ 3366 musbotg_setup_standard_chain(xfer); 3367 musbotg_start_standard_chain(xfer); 3368} 3369 3370static const struct usb_pipe_methods musbotg_device_ctrl_methods = 3371{ 3372 .open = musbotg_device_ctrl_open, 3373 .close = musbotg_device_ctrl_close, 3374 .enter = musbotg_device_ctrl_enter, 3375 .start = musbotg_device_ctrl_start, 3376}; 3377 3378/*------------------------------------------------------------------------* 3379 * musbotg interrupt support 3380 *------------------------------------------------------------------------*/ 3381static void 3382musbotg_device_intr_open(struct usb_xfer *xfer) 3383{ 3384 return; 3385} 3386 3387static void 3388musbotg_device_intr_close(struct usb_xfer *xfer) 3389{ 3390 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3391} 3392 3393static void 3394musbotg_device_intr_enter(struct usb_xfer *xfer) 3395{ 3396 return; 3397} 3398 3399static void 3400musbotg_device_intr_start(struct usb_xfer *xfer) 3401{ 3402 /* setup TDs */ 3403 musbotg_setup_standard_chain(xfer); 3404 musbotg_start_standard_chain(xfer); 3405} 3406 3407static const struct usb_pipe_methods musbotg_device_intr_methods = 3408{ 3409 .open = musbotg_device_intr_open, 3410 .close = musbotg_device_intr_close, 3411 .enter = musbotg_device_intr_enter, 3412 .start = musbotg_device_intr_start, 3413}; 3414 3415/*------------------------------------------------------------------------* 3416 * musbotg full speed isochronous support 3417 *------------------------------------------------------------------------*/ 3418static void 3419musbotg_device_isoc_open(struct usb_xfer *xfer) 3420{ 3421 return; 3422} 3423 3424static void 3425musbotg_device_isoc_close(struct usb_xfer *xfer) 3426{ 3427 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3428} 3429 3430static void 3431musbotg_device_isoc_enter(struct usb_xfer *xfer) 3432{ 3433 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 3434 uint32_t nframes; 3435 3436 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n", 3437 xfer, xfer->endpoint->isoc_next, xfer->nframes); 3438 3439 /* get the current frame index */ 3440 3441 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME); 3442 3443 if (usbd_xfer_get_isochronous_start_frame( 3444 xfer, nframes, 0, 1, MUSB2_MASK_FRAME, NULL)) 3445 DPRINTFN(2, "start next=%d\n", xfer->endpoint->isoc_next); 3446 3447 /* setup TDs */ 3448 musbotg_setup_standard_chain(xfer); 3449} 3450 3451static void 3452musbotg_device_isoc_start(struct usb_xfer *xfer) 3453{ 3454 /* start TD chain */ 3455 musbotg_start_standard_chain(xfer); 3456} 3457 3458static const struct usb_pipe_methods musbotg_device_isoc_methods = 3459{ 3460 .open = musbotg_device_isoc_open, 3461 .close = musbotg_device_isoc_close, 3462 .enter = musbotg_device_isoc_enter, 3463 .start = musbotg_device_isoc_start, 3464}; 3465 3466/*------------------------------------------------------------------------* 3467 * musbotg root control support 3468 *------------------------------------------------------------------------* 3469 * Simulate a hardware HUB by handling all the necessary requests. 3470 *------------------------------------------------------------------------*/ 3471 3472static const struct usb_device_descriptor musbotg_devd = { 3473 .bLength = sizeof(struct usb_device_descriptor), 3474 .bDescriptorType = UDESC_DEVICE, 3475 .bcdUSB = {0x00, 0x02}, 3476 .bDeviceClass = UDCLASS_HUB, 3477 .bDeviceSubClass = UDSUBCLASS_HUB, 3478 .bDeviceProtocol = UDPROTO_HSHUBSTT, 3479 .bMaxPacketSize = 64, 3480 .bcdDevice = {0x00, 0x01}, 3481 .iManufacturer = 1, 3482 .iProduct = 2, 3483 .bNumConfigurations = 1, 3484}; 3485 3486static const struct usb_device_qualifier musbotg_odevd = { 3487 .bLength = sizeof(struct usb_device_qualifier), 3488 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 3489 .bcdUSB = {0x00, 0x02}, 3490 .bDeviceClass = UDCLASS_HUB, 3491 .bDeviceSubClass = UDSUBCLASS_HUB, 3492 .bDeviceProtocol = UDPROTO_FSHUB, 3493 .bMaxPacketSize0 = 0, 3494 .bNumConfigurations = 0, 3495}; 3496 3497static const struct musbotg_config_desc musbotg_confd = { 3498 .confd = { 3499 .bLength = sizeof(struct usb_config_descriptor), 3500 .bDescriptorType = UDESC_CONFIG, 3501 .wTotalLength[0] = sizeof(musbotg_confd), 3502 .bNumInterface = 1, 3503 .bConfigurationValue = 1, 3504 .iConfiguration = 0, 3505 .bmAttributes = UC_SELF_POWERED, 3506 .bMaxPower = 0, 3507 }, 3508 .ifcd = { 3509 .bLength = sizeof(struct usb_interface_descriptor), 3510 .bDescriptorType = UDESC_INTERFACE, 3511 .bNumEndpoints = 1, 3512 .bInterfaceClass = UICLASS_HUB, 3513 .bInterfaceSubClass = UISUBCLASS_HUB, 3514 .bInterfaceProtocol = 0, 3515 }, 3516 .endpd = { 3517 .bLength = sizeof(struct usb_endpoint_descriptor), 3518 .bDescriptorType = UDESC_ENDPOINT, 3519 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT), 3520 .bmAttributes = UE_INTERRUPT, 3521 .wMaxPacketSize[0] = 8, 3522 .bInterval = 255, 3523 }, 3524}; 3525#define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3526 3527static const struct usb_hub_descriptor_min musbotg_hubd = { 3528 .bDescLength = sizeof(musbotg_hubd), 3529 .bDescriptorType = UDESC_HUB, 3530 .bNbrPorts = 1, 3531 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 3532 .bPwrOn2PwrGood = 50, 3533 .bHubContrCurrent = 0, 3534 .DeviceRemovable = {0}, /* port is removable */ 3535}; 3536 3537#define STRING_VENDOR \ 3538 "M\0e\0n\0t\0o\0r\0 \0G\0r\0a\0p\0h\0i\0c\0s" 3539 3540#define STRING_PRODUCT \ 3541 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B" 3542 3543USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor); 3544USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product); 3545 3546static usb_error_t 3547musbotg_roothub_exec(struct usb_device *udev, 3548 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3549{ 3550 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 3551 const void *ptr; 3552 uint16_t len; 3553 uint16_t value; 3554 uint16_t index; 3555 uint8_t reg; 3556 usb_error_t err; 3557 3558 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3559 3560 /* buffer reset */ 3561 ptr = (const void *)&sc->sc_hub_temp; 3562 len = 0; 3563 err = 0; 3564 3565 value = UGETW(req->wValue); 3566 index = UGETW(req->wIndex); 3567 3568 /* demultiplex the control request */ 3569 3570 switch (req->bmRequestType) { 3571 case UT_READ_DEVICE: 3572 switch (req->bRequest) { 3573 case UR_GET_DESCRIPTOR: 3574 goto tr_handle_get_descriptor; 3575 case UR_GET_CONFIG: 3576 goto tr_handle_get_config; 3577 case UR_GET_STATUS: 3578 goto tr_handle_get_status; 3579 default: 3580 goto tr_stalled; 3581 } 3582 break; 3583 3584 case UT_WRITE_DEVICE: 3585 switch (req->bRequest) { 3586 case UR_SET_ADDRESS: 3587 goto tr_handle_set_address; 3588 case UR_SET_CONFIG: 3589 goto tr_handle_set_config; 3590 case UR_CLEAR_FEATURE: 3591 goto tr_valid; /* nop */ 3592 case UR_SET_DESCRIPTOR: 3593 goto tr_valid; /* nop */ 3594 case UR_SET_FEATURE: 3595 default: 3596 goto tr_stalled; 3597 } 3598 break; 3599 3600 case UT_WRITE_ENDPOINT: 3601 switch (req->bRequest) { 3602 case UR_CLEAR_FEATURE: 3603 switch (UGETW(req->wValue)) { 3604 case UF_ENDPOINT_HALT: 3605 goto tr_handle_clear_halt; 3606 case UF_DEVICE_REMOTE_WAKEUP: 3607 goto tr_handle_clear_wakeup; 3608 default: 3609 goto tr_stalled; 3610 } 3611 break; 3612 case UR_SET_FEATURE: 3613 switch (UGETW(req->wValue)) { 3614 case UF_ENDPOINT_HALT: 3615 goto tr_handle_set_halt; 3616 case UF_DEVICE_REMOTE_WAKEUP: 3617 goto tr_handle_set_wakeup; 3618 default: 3619 goto tr_stalled; 3620 } 3621 break; 3622 case UR_SYNCH_FRAME: 3623 goto tr_valid; /* nop */ 3624 default: 3625 goto tr_stalled; 3626 } 3627 break; 3628 3629 case UT_READ_ENDPOINT: 3630 switch (req->bRequest) { 3631 case UR_GET_STATUS: 3632 goto tr_handle_get_ep_status; 3633 default: 3634 goto tr_stalled; 3635 } 3636 break; 3637 3638 case UT_WRITE_INTERFACE: 3639 switch (req->bRequest) { 3640 case UR_SET_INTERFACE: 3641 goto tr_handle_set_interface; 3642 case UR_CLEAR_FEATURE: 3643 goto tr_valid; /* nop */ 3644 case UR_SET_FEATURE: 3645 default: 3646 goto tr_stalled; 3647 } 3648 break; 3649 3650 case UT_READ_INTERFACE: 3651 switch (req->bRequest) { 3652 case UR_GET_INTERFACE: 3653 goto tr_handle_get_interface; 3654 case UR_GET_STATUS: 3655 goto tr_handle_get_iface_status; 3656 default: 3657 goto tr_stalled; 3658 } 3659 break; 3660 3661 case UT_WRITE_CLASS_INTERFACE: 3662 case UT_WRITE_VENDOR_INTERFACE: 3663 /* XXX forward */ 3664 break; 3665 3666 case UT_READ_CLASS_INTERFACE: 3667 case UT_READ_VENDOR_INTERFACE: 3668 /* XXX forward */ 3669 break; 3670 3671 case UT_WRITE_CLASS_DEVICE: 3672 switch (req->bRequest) { 3673 case UR_CLEAR_FEATURE: 3674 goto tr_valid; 3675 case UR_SET_DESCRIPTOR: 3676 case UR_SET_FEATURE: 3677 break; 3678 default: 3679 goto tr_stalled; 3680 } 3681 break; 3682 3683 case UT_WRITE_CLASS_OTHER: 3684 switch (req->bRequest) { 3685 case UR_CLEAR_FEATURE: 3686 goto tr_handle_clear_port_feature; 3687 case UR_SET_FEATURE: 3688 goto tr_handle_set_port_feature; 3689 case UR_CLEAR_TT_BUFFER: 3690 case UR_RESET_TT: 3691 case UR_STOP_TT: 3692 goto tr_valid; 3693 3694 default: 3695 goto tr_stalled; 3696 } 3697 break; 3698 3699 case UT_READ_CLASS_OTHER: 3700 switch (req->bRequest) { 3701 case UR_GET_TT_STATE: 3702 goto tr_handle_get_tt_state; 3703 case UR_GET_STATUS: 3704 goto tr_handle_get_port_status; 3705 default: 3706 goto tr_stalled; 3707 } 3708 break; 3709 3710 case UT_READ_CLASS_DEVICE: 3711 switch (req->bRequest) { 3712 case UR_GET_DESCRIPTOR: 3713 goto tr_handle_get_class_descriptor; 3714 case UR_GET_STATUS: 3715 goto tr_handle_get_class_status; 3716 3717 default: 3718 goto tr_stalled; 3719 } 3720 break; 3721 default: 3722 goto tr_stalled; 3723 } 3724 goto tr_valid; 3725 3726tr_handle_get_descriptor: 3727 switch (value >> 8) { 3728 case UDESC_DEVICE: 3729 if (value & 0xff) { 3730 goto tr_stalled; 3731 } 3732 len = sizeof(musbotg_devd); 3733 ptr = (const void *)&musbotg_devd; 3734 goto tr_valid; 3735 case UDESC_DEVICE_QUALIFIER: 3736 if (value & 0xff) { 3737 goto tr_stalled; 3738 } 3739 len = sizeof(musbotg_odevd); 3740 ptr = (const void *)&musbotg_odevd; 3741 goto tr_valid; 3742 case UDESC_CONFIG: 3743 if (value & 0xff) { 3744 goto tr_stalled; 3745 } 3746 len = sizeof(musbotg_confd); 3747 ptr = (const void *)&musbotg_confd; 3748 goto tr_valid; 3749 case UDESC_STRING: 3750 switch (value & 0xff) { 3751 case 0: /* Language table */ 3752 len = sizeof(usb_string_lang_en); 3753 ptr = (const void *)&usb_string_lang_en; 3754 goto tr_valid; 3755 3756 case 1: /* Vendor */ 3757 len = sizeof(musbotg_vendor); 3758 ptr = (const void *)&musbotg_vendor; 3759 goto tr_valid; 3760 3761 case 2: /* Product */ 3762 len = sizeof(musbotg_product); 3763 ptr = (const void *)&musbotg_product; 3764 goto tr_valid; 3765 default: 3766 break; 3767 } 3768 break; 3769 default: 3770 goto tr_stalled; 3771 } 3772 goto tr_stalled; 3773 3774tr_handle_get_config: 3775 len = 1; 3776 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 3777 goto tr_valid; 3778 3779tr_handle_get_status: 3780 len = 2; 3781 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 3782 goto tr_valid; 3783 3784tr_handle_set_address: 3785 if (value & 0xFF00) { 3786 goto tr_stalled; 3787 } 3788 sc->sc_rt_addr = value; 3789 goto tr_valid; 3790 3791tr_handle_set_config: 3792 if (value >= 2) { 3793 goto tr_stalled; 3794 } 3795 sc->sc_conf = value; 3796 goto tr_valid; 3797 3798tr_handle_get_interface: 3799 len = 1; 3800 sc->sc_hub_temp.wValue[0] = 0; 3801 goto tr_valid; 3802 3803tr_handle_get_tt_state: 3804tr_handle_get_class_status: 3805tr_handle_get_iface_status: 3806tr_handle_get_ep_status: 3807 len = 2; 3808 USETW(sc->sc_hub_temp.wValue, 0); 3809 goto tr_valid; 3810 3811tr_handle_set_halt: 3812tr_handle_set_interface: 3813tr_handle_set_wakeup: 3814tr_handle_clear_wakeup: 3815tr_handle_clear_halt: 3816 goto tr_valid; 3817 3818tr_handle_clear_port_feature: 3819 if (index != 1) { 3820 goto tr_stalled; 3821 } 3822 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 3823 3824 switch (value) { 3825 case UHF_PORT_SUSPEND: 3826 if (sc->sc_mode == MUSB2_HOST_MODE) 3827 musbotg_wakeup_host(sc); 3828 else 3829 musbotg_wakeup_peer(sc); 3830 break; 3831 3832 case UHF_PORT_ENABLE: 3833 sc->sc_flags.port_enabled = 0; 3834 break; 3835 3836 case UHF_C_PORT_ENABLE: 3837 sc->sc_flags.change_enabled = 0; 3838 break; 3839 3840 case UHF_C_PORT_OVER_CURRENT: 3841 sc->sc_flags.change_over_current = 0; 3842 break; 3843 3844 case UHF_C_PORT_RESET: 3845 sc->sc_flags.change_reset = 0; 3846 break; 3847 3848 case UHF_PORT_TEST: 3849 case UHF_PORT_INDICATOR: 3850 /* nops */ 3851 break; 3852 3853 case UHF_PORT_POWER: 3854 sc->sc_flags.port_powered = 0; 3855 musbotg_pull_down(sc); 3856 musbotg_clocks_off(sc); 3857 break; 3858 case UHF_C_PORT_CONNECTION: 3859 sc->sc_flags.change_connect = 0; 3860 break; 3861 case UHF_C_PORT_SUSPEND: 3862 sc->sc_flags.change_suspend = 0; 3863 break; 3864 default: 3865 err = USB_ERR_IOERROR; 3866 goto done; 3867 } 3868 goto tr_valid; 3869 3870tr_handle_set_port_feature: 3871 if (index != 1) { 3872 goto tr_stalled; 3873 } 3874 DPRINTFN(8, "UR_SET_PORT_FEATURE\n"); 3875 3876 switch (value) { 3877 case UHF_PORT_ENABLE: 3878 sc->sc_flags.port_enabled = 1; 3879 break; 3880 case UHF_PORT_SUSPEND: 3881 if (sc->sc_mode == MUSB2_HOST_MODE) 3882 musbotg_suspend_host(sc); 3883 break; 3884 3885 case UHF_PORT_RESET: 3886 if (sc->sc_mode == MUSB2_HOST_MODE) { 3887 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER); 3888 reg |= MUSB2_MASK_RESET; 3889 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg); 3890 3891 /* Wait for 20 msec */ 3892 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 5); 3893 3894 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER); 3895 reg &= ~MUSB2_MASK_RESET; 3896 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg); 3897 3898 /* determine line speed */ 3899 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER); 3900 if (reg & MUSB2_MASK_HSMODE) 3901 sc->sc_flags.status_high_speed = 1; 3902 else 3903 sc->sc_flags.status_high_speed = 0; 3904 3905 sc->sc_flags.change_reset = 1; 3906 } else 3907 err = USB_ERR_IOERROR; 3908 break; 3909 3910 case UHF_PORT_TEST: 3911 case UHF_PORT_INDICATOR: 3912 /* nops */ 3913 break; 3914 case UHF_PORT_POWER: 3915 sc->sc_flags.port_powered = 1; 3916 break; 3917 default: 3918 err = USB_ERR_IOERROR; 3919 goto done; 3920 } 3921 goto tr_valid; 3922 3923tr_handle_get_port_status: 3924 3925 DPRINTFN(8, "UR_GET_PORT_STATUS\n"); 3926 3927 if (index != 1) { 3928 goto tr_stalled; 3929 } 3930 if (sc->sc_flags.status_vbus) { 3931 musbotg_clocks_on(sc); 3932 musbotg_pull_up(sc); 3933 } else { 3934 musbotg_pull_down(sc); 3935 musbotg_clocks_off(sc); 3936 } 3937 3938 /* Select Device Side Mode */ 3939 if (sc->sc_mode == MUSB2_DEVICE_MODE) 3940 value = UPS_PORT_MODE_DEVICE; 3941 else 3942 value = 0; 3943 3944 if (sc->sc_flags.status_high_speed) { 3945 value |= UPS_HIGH_SPEED; 3946 } 3947 if (sc->sc_flags.port_powered) { 3948 value |= UPS_PORT_POWER; 3949 } 3950 if (sc->sc_flags.port_enabled) { 3951 value |= UPS_PORT_ENABLED; 3952 } 3953 3954 if (sc->sc_flags.port_over_current) 3955 value |= UPS_OVERCURRENT_INDICATOR; 3956 3957 if (sc->sc_flags.status_vbus && 3958 sc->sc_flags.status_bus_reset) { 3959 value |= UPS_CURRENT_CONNECT_STATUS; 3960 } 3961 if (sc->sc_flags.status_suspend) { 3962 value |= UPS_SUSPEND; 3963 } 3964 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 3965 3966 value = 0; 3967 3968 if (sc->sc_flags.change_connect) { 3969 value |= UPS_C_CONNECT_STATUS; 3970 3971 if (sc->sc_mode == MUSB2_DEVICE_MODE) { 3972 if (sc->sc_flags.status_vbus && 3973 sc->sc_flags.status_bus_reset) { 3974 /* reset EP0 state */ 3975 sc->sc_ep0_busy = 0; 3976 sc->sc_ep0_cmd = 0; 3977 } 3978 } 3979 } 3980 if (sc->sc_flags.change_suspend) 3981 value |= UPS_C_SUSPEND; 3982 if (sc->sc_flags.change_reset) 3983 value |= UPS_C_PORT_RESET; 3984 if (sc->sc_flags.change_over_current) 3985 value |= UPS_C_OVERCURRENT_INDICATOR; 3986 3987 USETW(sc->sc_hub_temp.ps.wPortChange, value); 3988 len = sizeof(sc->sc_hub_temp.ps); 3989 goto tr_valid; 3990 3991tr_handle_get_class_descriptor: 3992 if (value & 0xFF) { 3993 goto tr_stalled; 3994 } 3995 ptr = (const void *)&musbotg_hubd; 3996 len = sizeof(musbotg_hubd); 3997 goto tr_valid; 3998 3999tr_stalled: 4000 err = USB_ERR_STALLED; 4001tr_valid: 4002done: 4003 *plength = len; 4004 *pptr = ptr; 4005 return (err); 4006} 4007 4008static void 4009musbotg_xfer_setup(struct usb_setup_params *parm) 4010{ 4011 struct usb_xfer *xfer; 4012 void *last_obj; 4013 uint32_t ntd; 4014 uint32_t n; 4015 uint8_t ep_no; 4016 4017 xfer = parm->curr_xfer; 4018 4019 /* 4020 * NOTE: This driver does not use any of the parameters that 4021 * are computed from the following values. Just set some 4022 * reasonable dummies: 4023 */ 4024 parm->hc_max_packet_size = 0x400; 4025 parm->hc_max_frame_size = 0xc00; 4026 4027 if ((parm->methods == &musbotg_device_isoc_methods) || 4028 (parm->methods == &musbotg_device_intr_methods)) 4029 parm->hc_max_packet_count = 3; 4030 else 4031 parm->hc_max_packet_count = 1; 4032 4033 usbd_transfer_setup_sub(parm); 4034 4035 /* 4036 * compute maximum number of TDs 4037 */ 4038 if (parm->methods == &musbotg_device_ctrl_methods) { 4039 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ; 4040 4041 } else if (parm->methods == &musbotg_device_bulk_methods) { 4042 ntd = xfer->nframes + 1 /* SYNC */ ; 4043 4044 } else if (parm->methods == &musbotg_device_intr_methods) { 4045 ntd = xfer->nframes + 1 /* SYNC */ ; 4046 4047 } else if (parm->methods == &musbotg_device_isoc_methods) { 4048 ntd = xfer->nframes + 1 /* SYNC */ ; 4049 4050 } else { 4051 ntd = 0; 4052 } 4053 4054 /* 4055 * check if "usbd_transfer_setup_sub" set an error 4056 */ 4057 if (parm->err) { 4058 return; 4059 } 4060 /* 4061 * allocate transfer descriptors 4062 */ 4063 last_obj = NULL; 4064 4065 ep_no = xfer->endpointno & UE_ADDR; 4066 4067 /* 4068 * Check for a valid endpoint profile in USB device mode: 4069 */ 4070 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 4071 const struct usb_hw_ep_profile *pf; 4072 4073 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no); 4074 4075 if (pf == NULL) { 4076 /* should not happen */ 4077 parm->err = USB_ERR_INVAL; 4078 return; 4079 } 4080 } 4081 4082 /* align data */ 4083 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 4084 4085 for (n = 0; n != ntd; n++) { 4086 struct musbotg_td *td; 4087 4088 if (parm->buf) { 4089 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 4090 4091 /* init TD */ 4092 td->max_frame_size = xfer->max_frame_size; 4093 td->reg_max_packet = xfer->max_packet_size | 4094 ((xfer->max_packet_count - 1) << 11); 4095 td->ep_no = ep_no; 4096 td->obj_next = last_obj; 4097 4098 last_obj = td; 4099 } 4100 parm->size[0] += sizeof(*td); 4101 } 4102 4103 xfer->td_start[0] = last_obj; 4104} 4105 4106static void 4107musbotg_xfer_unsetup(struct usb_xfer *xfer) 4108{ 4109 return; 4110} 4111 4112static void 4113musbotg_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4114{ 4115 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 4116 4117 if (sc->sc_mode == MUSB2_HOST_MODE) 4118 *pus = 2000; /* microseconds */ 4119 else 4120 *pus = 0; 4121} 4122 4123static void 4124musbotg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4125 struct usb_endpoint *ep) 4126{ 4127 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 4128 4129 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 4130 ep, udev->address, 4131 edesc->bEndpointAddress, udev->flags.usb_mode, 4132 sc->sc_rt_addr); 4133 4134 if (udev->device_index != sc->sc_rt_addr) { 4135 switch (edesc->bmAttributes & UE_XFERTYPE) { 4136 case UE_CONTROL: 4137 ep->methods = &musbotg_device_ctrl_methods; 4138 break; 4139 case UE_INTERRUPT: 4140 ep->methods = &musbotg_device_intr_methods; 4141 break; 4142 case UE_ISOCHRONOUS: 4143 ep->methods = &musbotg_device_isoc_methods; 4144 break; 4145 case UE_BULK: 4146 ep->methods = &musbotg_device_bulk_methods; 4147 break; 4148 default: 4149 /* do nothing */ 4150 break; 4151 } 4152 } 4153} 4154 4155static void 4156musbotg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 4157{ 4158 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 4159 4160 switch (state) { 4161 case USB_HW_POWER_SUSPEND: 4162 musbotg_uninit(sc); 4163 break; 4164 case USB_HW_POWER_SHUTDOWN: 4165 musbotg_uninit(sc); 4166 break; 4167 case USB_HW_POWER_RESUME: 4168 musbotg_init(sc); 4169 break; 4170 default: 4171 break; 4172 } 4173} 4174 4175static const struct usb_bus_methods musbotg_bus_methods = 4176{ 4177 .endpoint_init = &musbotg_ep_init, 4178 .get_dma_delay = &musbotg_get_dma_delay, 4179 .xfer_setup = &musbotg_xfer_setup, 4180 .xfer_unsetup = &musbotg_xfer_unsetup, 4181 .get_hw_ep_profile = &musbotg_get_hw_ep_profile, 4182 .xfer_stall = &musbotg_xfer_stall, 4183 .set_stall = &musbotg_set_stall, 4184 .clear_stall = &musbotg_clear_stall, 4185 .roothub_exec = &musbotg_roothub_exec, 4186 .xfer_poll = &musbotg_do_poll, 4187 .set_hw_power_sleep = &musbotg_set_hw_power_sleep, 4188}; 4189