| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600OptimizeVectorRegisters.cpp | 189 Register SrcVec = BaseRSI->Instr->getOperand(0).getReg(); local
200 .addReg(SrcVec)
211 SrcVec = DstReg;
214 BuildMI(MBB, Pos, DL, TII->get(R600::COPY), Reg).addReg(SrcVec);
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| H A D | SIISelLowering.cpp | 4505 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src); local
4509 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg());
4517 SrcVec->getReg(),
4528 .add(*SrcVec)
4547 .addReg(SrcVec->getReg())
4557 .addReg(SrcVec->getReg())
4574 auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg, Offset,
8268 SDValue SrcVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, local
8271 SDValue SrcHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, SrcVec,
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| /freebsd-current/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineVectorOps.cpp | 399 Value *SrcVec = EI.getVectorOperand(); local
401 if (Value *V = simplifyExtractElementInst(SrcVec, Index,
430 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(SrcVec)) {
459 if (auto *Phi = dyn_cast<PHINode>(SrcVec))
467 if (match(SrcVec, m_UnOp(UO)) && cheapToScalarize(SrcVec, Index)) {
475 if (match(SrcVec, m_BinOp(BO)) && cheapToScalarize(SrcVec, Index)) {
485 if (match(SrcVec, m_Cmp(Pred, m_Value(X), m_Value(Y))) &&
486 cheapToScalarize(SrcVec, Inde
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 497 Register SrcVec = Left; local
501 SrcVec = Right;
505 MatchInfo = std::make_tuple(DstVec, DstLane, SrcVec, SrcLane);
515 Register DstVec, SrcVec; local
517 std::tie(DstVec, DstLane, SrcVec, SrcLane) = MatchInfo;
519 auto Extract = Builder.buildExtractVectorElement(ScalarTy, SrcVec, SrcCst);
|
| /freebsd-current/contrib/llvm-project/llvm/lib/IR/ |
| H A D | Verifier.cpp | 3173 bool SrcVec = SrcTy->isVectorTy(); local
3176 Check(SrcVec == DstVec,
3183 if (SrcVec && DstVec)
3196 bool SrcVec = SrcTy->isVectorTy(); local
3199 Check(SrcVec == DstVec,
3206 if (SrcVec && DstVec)
3219 bool SrcVec = SrcTy->isVectorTy(); local
3222 Check(SrcVec == DstVec,
3228 if (SrcVec && DstVec)
3241 bool SrcVec local
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VectorCombine.cpp | 630 Value *SrcVec;
634 m_ExtractElt(m_Value(SrcVec), m_SpecificInt(Index))))))
639 if (SrcVec->getType() != VecTy)
673 // insertelt DestVec, (fneg (extractelt SrcVec, Index)), Index -->
674 // shuffle DestVec, (fneg SrcVec), Mask
675 Value *VecFNeg = Builder.CreateFNegFMF(SrcVec, FNeg);
|
| /freebsd-current/contrib/llvm-project/llvm/lib/ExecutionEngine/Interpreter/ |
| H A D | Execution.cpp | 1549 GenericValue TempDst, TempSrc, SrcVec;
1561 SrcVec = Src;
1567 SrcVec.AggregateVal.push_back(Src);
1588 APInt::floatToBits(SrcVec.AggregateVal[i].FloatVal);
1593 APInt::doubleToBits(SrcVec.AggregateVal[i].DoubleVal);
1596 TempSrc.AggregateVal[i].IntVal = SrcVec.AggregateVal[i].IntVal;
|
| /freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 3107 auto [Dst, DstTy, SrcVec, SrcVecTy, Idx, IdxTy] = MI.getFirst3RegLLTs();
3114 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0);
3243 auto [Dst, DstTy, SrcVec, SrcVecTy, Val, ValTy, Idx, IdxTy] =
3255 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0);
4337 auto [DstReg, SrcVec] = MI.getFirst2Regs();
4351 LLT VecTy = MRI.getType(SrcVec);
4367 LLT GCDTy = extractGCDType(VecParts, VecTy, NarrowVecTy, SrcVec);
7131 Register SrcVec = MI.getOperand(1).getReg();
7138 LLT VecTy = MRI.getType(SrcVec);
7145 extractParts(SrcVec, EltT
[all...] |
| H A D | CombinerHelper.cpp | 3985 Register SrcVec = MI.getOperand(1).getReg();
3986 LLT SrcTy = MRI.getType(SrcVec);
3996 MachineInstr *SrcVecMI = MRI.getVRegDef(SrcVec);
4006 if (!MRI.hasOneNonDBGUse(SrcVec) &&
|
| /freebsd-current/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | IRBuilder.h | 1031 CallInst *CreateExtractVector(Type *DstType, Value *SrcVec, Value *Idx, argument
1034 {DstType, SrcVec->getType()}, {SrcVec, Idx}, nullptr,
1039 CallInst *CreateInsertVector(Type *DstType, Value *SrcVec, Value *SubVec, argument
1042 {DstType, SubVec->getType()}, {SrcVec, SubVec, Idx},
|
| /freebsd-current/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CodeGenFunction.cpp | 2957 llvm::Value *CodeGenFunction::emitBoolVecConversion(llvm::Value *SrcVec,
2960 auto *SrcTy = cast<llvm::FixedVectorType>(SrcVec->getType());
2963 return SrcVec;
2970 return Builder.CreateShuffleVector(SrcVec, ShuffleMask, Name);
|
| H A D | CodeGenFunction.h | 4835 llvm::Value *emitBoolVecConversion(llvm::Value *SrcVec,
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 5907 SDValue SrcVec = SrcExtract.getOperand(0);
5908 EVT SrcVT = SrcVec.getValueType();
5919 Ops.push_back(SrcVec);
5922 Ops.push_back(SrcVec);
8317 static SDValue createVariablePermute(MVT VT, SDValue SrcVec, SDValue IndicesVec,
8343 // Handle SrcVec that don't match VT type.
8344 if (SrcVec.getValueSizeInBits() != SizeInBits) {
8345 if ((SrcVec.getValueSizeInBits() % SizeInBits) == 0) {
8346 // Handle larger SrcVec by treating it as a larger permute.
8347 unsigned Scale = SrcVec
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 1974 auto GetConvertedLane = [](SDValue Op, unsigned &Opcode, SDValue &SrcVec,
1997 SrcVec = ExtractVector.getOperand(0);
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 861 auto IsBuildFromExtracts = [this,&Values] (SDValue &SrcVec,
883 SrcVec = Vec;
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 4723 SDValue SrcVec = (unsigned)SrcVecIdx >= VRegsPerSrc ? V2 : V1; local
4724 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, M1VT, SrcVec,
12131 SDValue SrcVec = RHS.getOperand(0); local
12132 EVT SrcVecVT = SrcVec.getValueType();
12145 LHS.getOperand(0) == SrcVec && isa<ConstantSDNode>(LHS.getOperand(1))) {
12150 SDValue Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ReduceVT, SrcVec,
12172 SDValue Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ReduceVT, SrcVec,
|
| /freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 26091 SDValue SrcVec = Scalar.getOperand(0);
26092 EVT SrcVT = SrcVec.getValueType();
26100 SrcVT, SDLoc(N), SrcVec, DAG.getUNDEF(SrcVT), Mask, DAG);
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 12317 SDValue SrcVec = V1; local
12320 SrcVec = V2;
12332 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 14897 SDValue SrcVec = Ext1.getOperand(0);
14901 SrcVec, DAG.getIntPtrConstant(SubvecIdx, dl));
|