Searched refs:CSR_READ_2 (Results 1 - 25 of 38) sorted by relevance

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/freebsd-current/sys/dev/vte/
H A Dif_vte.c179 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_READ) == 0)
188 return (CSR_READ_2(sc, VTE_MMRD));
204 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_WRITE) == 0)
360 mid = CSR_READ_2(sc, VTE_MID0L);
363 mid = CSR_READ_2(sc, VTE_MID0M);
366 mid = CSR_READ_2(sc, VTE_MID0H);
409 CSR_READ_2(sc, VTE_MACID));
410 macid = CSR_READ_2(sc, VTE_MACID_REV);
1236 mcr = CSR_READ_2(sc, VTE_MCR0);
1261 CSR_READ_2(s
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H A Dif_vtevar.h151 #define CSR_READ_2(_sc, reg) \ macro
/freebsd-current/sys/dev/vge/
H A Dif_vgevar.h226 #define CSR_READ_2(sc, reg) \ macro
234 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
241 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
/freebsd-current/sys/dev/ste/
H A Dif_ste.c189 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
192 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
281 cfg = CSR_READ_2(sc, STE_MACCTL0);
366 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY)
397 *dest = le16toh(CSR_READ_2(sc, STE_EEPROM_DATA));
489 status = CSR_READ_2(sc, STE_ISR_ACK);
521 status = CSR_READ_2(sc, STE_ISR_ACK);
687 txstat = CSR_READ_2(sc, STE_TX_STATUS);
811 CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO);
812 CSR_READ_2(s
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H A Dif_stereg.h490 #define CSR_READ_2(sc, reg) \ macro
/freebsd-current/sys/dev/bwi/
H A Dif_bwivar.h78 #define CSR_READ_2(sc, reg) \ macro
89 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))
94 CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))
99 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))
H A Dbwirf.c221 return CSR_READ_2(sc, BWI_RF_DATA_LO);
252 val = CSR_READ_2(sc, BWI_RF_DATA_HI);
256 val |= CSR_READ_2(sc, BWI_RF_DATA_LO);
783 bphy_ctrl = CSR_READ_2(sc, BWI_BPHY_CTRL);
820 bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN);
821 rf_chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
1281 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);
1283 chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
1662 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);
1663 CSR_READ_2(s
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H A Dbwimac.c174 return CSR_READ_2(sc, data_reg);
188 ret = CSR_READ_2(sc, BWI_MOBJ_DATA_UNALIGN);
193 ret |= CSR_READ_2(sc, BWI_MOBJ_DATA);
735 if (CSR_READ_2(sc, 0x50e) & 0x80)
740 if (CSR_READ_2(sc, 0x50e) & 0x400)
745 if ((CSR_READ_2(sc, 0x690) & 0x100) == 0)
1947 CSR_READ_2(sc, BWI_PHYINFO); /* dummy read */
/freebsd-current/sys/dev/stge/
H A Dif_stge.c381 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0)
403 *data = CSR_READ_2(sc, STGE_EepromData);
541 v = CSR_READ_2(sc, STGE_StationAddress0);
544 v = CSR_READ_2(sc, STGE_StationAddress1);
547 v = CSR_READ_2(sc, STGE_StationAddress2);
1467 status = CSR_READ_2(sc, STGE_IntStatus);
1473 status = CSR_READ_2(sc, STGE_IntStatusAck);
1798 status = CSR_READ_2(sc, STGE_IntStatus);
1877 if_inc_counter(ifp, IFCOUNTER_IERRORS, CSR_READ_2(sc, STGE_FramesLostRxErrors));
1889 CSR_READ_2(s
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H A Dif_stgereg.h98 #define CSR_READ_2(_sc, reg) \ macro
/freebsd-current/sys/dev/fxp/
H A Dif_fxpvar.h245 #define CSR_READ_2(sc, reg) bus_read_2(sc->fxp_res[0], reg) macro
/freebsd-current/sys/dev/xl/
H A Dif_xl.c358 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0)
388 val = CSR_READ_2(sc, XL_W4_PHY_MGMT);
530 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
579 word = CSR_READ_2(sc, XL_W0_EE_DATA);
746 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
856 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
880 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) |
1364 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
2159 status = CSR_READ_2(sc, XL_STATUS);
2246 status = CSR_READ_2(s
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/freebsd-current/sys/dev/rl/
H A Dif_rl.c427 return (CSR_READ_2(sc, rl8139_reg));
1131 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1134 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1323 if (CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_LINK_OK) {
1339 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS;
1368 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS;
1466 status = CSR_READ_2(sc, RL_ISR);
1503 status = CSR_READ_2(sc, RL_ISR);
1524 status = CSR_READ_2(sc, RL_ISR);
H A Dif_rlreg.h956 #define CSR_READ_2(sc, reg) \ macro
971 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
974 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
/freebsd-current/sys/dev/vr/
H A Dif_vrreg.h753 #define CSR_READ_2(sc, reg) bus_read_2(sc->vr_res, reg) macro
759 #define VR_SETBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
760 #define VR_CLRBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
H A Dif_vr.c259 return (CSR_READ_2(sc, VR_MIIDATA));
1616 status = CSR_READ_2(sc, VR_ISR);
1677 status = CSR_READ_2(sc, VR_ISR);
1703 status = CSR_READ_2(sc, VR_ISR);
1741 status = CSR_READ_2(sc, VR_ISR);
/freebsd-current/sys/dev/alc/
H A Dif_alcvar.h266 #define CSR_READ_2(_sc, reg) \ macro
/freebsd-current/sys/dev/age/
H A Dif_agevar.h241 #define CSR_READ_2(_sc, reg) \ macro
/freebsd-current/sys/dev/ale/
H A Dif_alevar.h235 #define CSR_READ_2(_sc, reg) \ macro
/freebsd-current/sys/dev/ipw/
H A Dif_ipwreg.h329 #define CSR_READ_2(sc, reg) \ macro
/freebsd-current/sys/dev/iwi/
H A Dif_iwireg.h575 #define CSR_READ_2(sc, reg) \ macro
/freebsd-current/sys/dev/my/
H A Dif_myreg.h397 #define CSR_READ_2(sc, reg) \ macro
/freebsd-current/sys/dev/re/
H A Dif_re.c562 rval = CSR_READ_2(sc, re8139_reg);
850 status = CSR_READ_2(sc, RL_ISR);
2542 status = CSR_READ_2(sc, RL_ISR);
2572 status = CSR_READ_2(sc, RL_ISR);
2595 status = CSR_READ_2(sc, RL_ISR);
2644 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) {
2677 status = CSR_READ_2(sc, RL_ISR);
/freebsd-current/sys/dev/sge/
H A Dif_sge.c185 #define CSR_READ_2(sc, reg) bus_read_2(sc->sge_res, reg) macro
462 rxfilt = CSR_READ_2(sc, RxMacControl);
495 rxfilt = CSR_READ_2(sc, RxMacControl);
/freebsd-current/sys/dev/msk/
H A Dif_mskreg.h2133 #define CSR_READ_2(sc, reg) \ macro
2155 CSR_READ_2((sc_if)->msk_softc, (reg))
2171 CSR_READ_2((sc), GMAC_REG((port), (reg)))

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