1/*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998-2003 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35#include <sys/cdefs.h> 36/* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124#include <sys/lock.h> 125#include <sys/mutex.h> 126#include <sys/sysctl.h> 127#include <sys/taskqueue.h> 128 129#include <net/debugnet.h> 130#include <net/if.h> 131#include <net/if_var.h> 132#include <net/if_arp.h> 133#include <net/ethernet.h> 134#include <net/if_dl.h> 135#include <net/if_media.h> 136#include <net/if_types.h> 137#include <net/if_vlan_var.h> 138 139#include <net/bpf.h> 140 141#include <machine/bus.h> 142#include <machine/resource.h> 143#include <sys/bus.h> 144#include <sys/rman.h> 145 146#include <dev/mii/mii.h> 147#include <dev/mii/miivar.h> 148 149#include <dev/pci/pcireg.h> 150#include <dev/pci/pcivar.h> 151 152#include <dev/rl/if_rlreg.h> 153 154MODULE_DEPEND(re, pci, 1, 1, 1); 155MODULE_DEPEND(re, ether, 1, 1, 1); 156MODULE_DEPEND(re, miibus, 1, 1, 1); 157 158/* "device miibus" required. See GENERIC if you get errors here. */ 159#include "miibus_if.h" 160 161/* Tunables. */ 162static int intr_filter = 0; 163TUNABLE_INT("hw.re.intr_filter", &intr_filter); 164static int msi_disable = 0; 165TUNABLE_INT("hw.re.msi_disable", &msi_disable); 166static int msix_disable = 0; 167TUNABLE_INT("hw.re.msix_disable", &msix_disable); 168static int prefer_iomap = 0; 169TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 170 171#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 172 173/* 174 * Various supported device vendors/types and their names. 175 */ 176static const struct rl_type re_devs[] = { 177 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 178 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 179 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0, 180 "D-Link DGE-530(T) Gigabit Ethernet Adapter" }, 181 { RT_VENDORID, RT_DEVICEID_2600, 0, 182 "RealTek Killer E2600 Gigabit Ethernet Controller" }, 183 { RT_VENDORID, RT_DEVICEID_8139, 0, 184 "RealTek 8139C+ 10/100BaseTX" }, 185 { RT_VENDORID, RT_DEVICEID_8101E, 0, 186 "RealTek 810xE PCIe 10/100baseTX" }, 187 { RT_VENDORID, RT_DEVICEID_8168, 0, 188 "RealTek 8168/8111 B/C/CP/D/DP/E/F/G PCIe Gigabit Ethernet" }, 189 { RT_VENDORID, RT_DEVICEID_8161, 0, 190 "RealTek 8168 Gigabit Ethernet" }, 191 { NCUBE_VENDORID, RT_DEVICEID_8168, 0, 192 "TP-Link TG-3468 v2 (RTL8168) Gigabit Ethernet" }, 193 { RT_VENDORID, RT_DEVICEID_8169, 0, 194 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 195 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 196 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 197 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 198 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 199 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 200 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 201 { USR_VENDORID, USR_DEVICEID_997902, 0, 202 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 203}; 204 205static const struct rl_hwrev re_hwrevs[] = { 206 { RL_HWREV_8139, RL_8139, "", RL_MTU }, 207 { RL_HWREV_8139A, RL_8139, "A", RL_MTU }, 208 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU }, 209 { RL_HWREV_8139B, RL_8139, "B", RL_MTU }, 210 { RL_HWREV_8130, RL_8139, "8130", RL_MTU }, 211 { RL_HWREV_8139C, RL_8139, "C", RL_MTU }, 212 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU }, 213 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU }, 214 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU }, 215 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU }, 216 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU }, 217 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU }, 218 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU }, 219 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 220 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU }, 221 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 222 { RL_HWREV_8100, RL_8139, "8100", RL_MTU }, 223 { RL_HWREV_8101, RL_8139, "8101", RL_MTU }, 224 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU }, 225 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU }, 226 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU }, 227 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU }, 228 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU }, 229 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU }, 230 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU }, 231 { RL_HWREV_8402, RL_8169, "8402", RL_MTU }, 232 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU }, 233 { RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU }, 234 { RL_HWREV_8106E, RL_8169, "8106E", RL_MTU }, 235 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU }, 236 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU }, 237 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 238 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 239 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K }, 240 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K }, 241 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K }, 242 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K}, 243 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K}, 244 { RL_HWREV_8168EP, RL_8169, "8168EP/8111EP", RL_JUMBO_MTU_9K}, 245 { RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K}, 246 { RL_HWREV_8168FP, RL_8169, "8168FP/8111FP", RL_JUMBO_MTU_9K}, 247 { RL_HWREV_8168G, RL_8169, "8168G/8111G", RL_JUMBO_MTU_9K}, 248 { RL_HWREV_8168GU, RL_8169, "8168GU/8111GU", RL_JUMBO_MTU_9K}, 249 { RL_HWREV_8168H, RL_8169, "8168H/8111H", RL_JUMBO_MTU_9K}, 250 { RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K}, 251 { RL_HWREV_8411B, RL_8169, "8411B", RL_JUMBO_MTU_9K}, 252 { 0, 0, NULL, 0 } 253}; 254 255static int re_probe (device_t); 256static int re_attach (device_t); 257static int re_detach (device_t); 258 259static int re_encap (struct rl_softc *, struct mbuf **); 260 261static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 262static int re_allocmem (device_t, struct rl_softc *); 263static __inline void re_discard_rxbuf 264 (struct rl_softc *, int); 265static int re_newbuf (struct rl_softc *, int); 266static int re_jumbo_newbuf (struct rl_softc *, int); 267static int re_rx_list_init (struct rl_softc *); 268static int re_jrx_list_init (struct rl_softc *); 269static int re_tx_list_init (struct rl_softc *); 270#ifdef RE_FIXUP_RX 271static __inline void re_fixup_rx 272 (struct mbuf *); 273#endif 274static int re_rxeof (struct rl_softc *, int *); 275static void re_txeof (struct rl_softc *); 276#ifdef DEVICE_POLLING 277static int re_poll (if_t, enum poll_cmd, int); 278static int re_poll_locked (if_t, enum poll_cmd, int); 279#endif 280static int re_intr (void *); 281static void re_intr_msi (void *); 282static void re_tick (void *); 283static void re_int_task (void *, int); 284static void re_start (if_t); 285static void re_start_locked (if_t); 286static void re_start_tx (struct rl_softc *); 287static int re_ioctl (if_t, u_long, caddr_t); 288static void re_init (void *); 289static void re_init_locked (struct rl_softc *); 290static void re_stop (struct rl_softc *); 291static void re_watchdog (struct rl_softc *); 292static int re_suspend (device_t); 293static int re_resume (device_t); 294static int re_shutdown (device_t); 295static int re_ifmedia_upd (if_t); 296static void re_ifmedia_sts (if_t, struct ifmediareq *); 297 298static void re_eeprom_putbyte (struct rl_softc *, int); 299static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 300static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 301static int re_gmii_readreg (device_t, int, int); 302static int re_gmii_writereg (device_t, int, int, int); 303 304static int re_miibus_readreg (device_t, int, int); 305static int re_miibus_writereg (device_t, int, int, int); 306static void re_miibus_statchg (device_t); 307 308static void re_set_jumbo (struct rl_softc *, int); 309static void re_set_rxmode (struct rl_softc *); 310static void re_reset (struct rl_softc *); 311static void re_setwol (struct rl_softc *); 312static void re_clrwol (struct rl_softc *); 313static void re_set_linkspeed (struct rl_softc *); 314 315DEBUGNET_DEFINE(re); 316 317#ifdef DEV_NETMAP /* see ixgbe.c for details */ 318#include <dev/netmap/if_re_netmap.h> 319MODULE_DEPEND(re, netmap, 1, 1, 1); 320#endif /* !DEV_NETMAP */ 321 322#ifdef RE_DIAG 323static int re_diag (struct rl_softc *); 324#endif 325 326static void re_add_sysctls (struct rl_softc *); 327static int re_sysctl_stats (SYSCTL_HANDLER_ARGS); 328static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int); 329static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS); 330 331static device_method_t re_methods[] = { 332 /* Device interface */ 333 DEVMETHOD(device_probe, re_probe), 334 DEVMETHOD(device_attach, re_attach), 335 DEVMETHOD(device_detach, re_detach), 336 DEVMETHOD(device_suspend, re_suspend), 337 DEVMETHOD(device_resume, re_resume), 338 DEVMETHOD(device_shutdown, re_shutdown), 339 340 /* MII interface */ 341 DEVMETHOD(miibus_readreg, re_miibus_readreg), 342 DEVMETHOD(miibus_writereg, re_miibus_writereg), 343 DEVMETHOD(miibus_statchg, re_miibus_statchg), 344 345 DEVMETHOD_END 346}; 347 348static driver_t re_driver = { 349 "re", 350 re_methods, 351 sizeof(struct rl_softc) 352}; 353 354DRIVER_MODULE(re, pci, re_driver, 0, 0); 355DRIVER_MODULE(miibus, re, miibus_driver, 0, 0); 356 357#define EE_SET(x) \ 358 CSR_WRITE_1(sc, RL_EECMD, \ 359 CSR_READ_1(sc, RL_EECMD) | x) 360 361#define EE_CLR(x) \ 362 CSR_WRITE_1(sc, RL_EECMD, \ 363 CSR_READ_1(sc, RL_EECMD) & ~x) 364 365/* 366 * Send a read command and address to the EEPROM, check for ACK. 367 */ 368static void 369re_eeprom_putbyte(struct rl_softc *sc, int addr) 370{ 371 int d, i; 372 373 d = addr | (RL_9346_READ << sc->rl_eewidth); 374 375 /* 376 * Feed in each bit and strobe the clock. 377 */ 378 379 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 380 if (d & i) { 381 EE_SET(RL_EE_DATAIN); 382 } else { 383 EE_CLR(RL_EE_DATAIN); 384 } 385 DELAY(100); 386 EE_SET(RL_EE_CLK); 387 DELAY(150); 388 EE_CLR(RL_EE_CLK); 389 DELAY(100); 390 } 391} 392 393/* 394 * Read a word of data stored in the EEPROM at address 'addr.' 395 */ 396static void 397re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 398{ 399 int i; 400 u_int16_t word = 0; 401 402 /* 403 * Send address of word we want to read. 404 */ 405 re_eeprom_putbyte(sc, addr); 406 407 /* 408 * Start reading bits from EEPROM. 409 */ 410 for (i = 0x8000; i; i >>= 1) { 411 EE_SET(RL_EE_CLK); 412 DELAY(100); 413 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 414 word |= i; 415 EE_CLR(RL_EE_CLK); 416 DELAY(100); 417 } 418 419 *dest = word; 420} 421 422/* 423 * Read a sequence of words from the EEPROM. 424 */ 425static void 426re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 427{ 428 int i; 429 u_int16_t word = 0, *ptr; 430 431 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 432 433 DELAY(100); 434 435 for (i = 0; i < cnt; i++) { 436 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 437 re_eeprom_getword(sc, off + i, &word); 438 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 439 ptr = (u_int16_t *)(dest + (i * 2)); 440 *ptr = word; 441 } 442 443 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 444} 445 446static int 447re_gmii_readreg(device_t dev, int phy, int reg) 448{ 449 struct rl_softc *sc; 450 u_int32_t rval; 451 int i; 452 453 sc = device_get_softc(dev); 454 455 /* Let the rgephy driver read the GMEDIASTAT register */ 456 457 if (reg == RL_GMEDIASTAT) { 458 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 459 return (rval); 460 } 461 462 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 463 464 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 465 rval = CSR_READ_4(sc, RL_PHYAR); 466 if (rval & RL_PHYAR_BUSY) 467 break; 468 DELAY(25); 469 } 470 471 if (i == RL_PHY_TIMEOUT) { 472 device_printf(sc->rl_dev, "PHY read failed\n"); 473 return (0); 474 } 475 476 /* 477 * Controller requires a 20us delay to process next MDIO request. 478 */ 479 DELAY(20); 480 481 return (rval & RL_PHYAR_PHYDATA); 482} 483 484static int 485re_gmii_writereg(device_t dev, int phy, int reg, int data) 486{ 487 struct rl_softc *sc; 488 u_int32_t rval; 489 int i; 490 491 sc = device_get_softc(dev); 492 493 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 494 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 495 496 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 497 rval = CSR_READ_4(sc, RL_PHYAR); 498 if (!(rval & RL_PHYAR_BUSY)) 499 break; 500 DELAY(25); 501 } 502 503 if (i == RL_PHY_TIMEOUT) { 504 device_printf(sc->rl_dev, "PHY write failed\n"); 505 return (0); 506 } 507 508 /* 509 * Controller requires a 20us delay to process next MDIO request. 510 */ 511 DELAY(20); 512 513 return (0); 514} 515 516static int 517re_miibus_readreg(device_t dev, int phy, int reg) 518{ 519 struct rl_softc *sc; 520 u_int16_t rval = 0; 521 u_int16_t re8139_reg = 0; 522 523 sc = device_get_softc(dev); 524 525 if (sc->rl_type == RL_8169) { 526 rval = re_gmii_readreg(dev, phy, reg); 527 return (rval); 528 } 529 530 switch (reg) { 531 case MII_BMCR: 532 re8139_reg = RL_BMCR; 533 break; 534 case MII_BMSR: 535 re8139_reg = RL_BMSR; 536 break; 537 case MII_ANAR: 538 re8139_reg = RL_ANAR; 539 break; 540 case MII_ANER: 541 re8139_reg = RL_ANER; 542 break; 543 case MII_ANLPAR: 544 re8139_reg = RL_LPAR; 545 break; 546 case MII_PHYIDR1: 547 case MII_PHYIDR2: 548 return (0); 549 /* 550 * Allow the rlphy driver to read the media status 551 * register. If we have a link partner which does not 552 * support NWAY, this is the register which will tell 553 * us the results of parallel detection. 554 */ 555 case RL_MEDIASTAT: 556 rval = CSR_READ_1(sc, RL_MEDIASTAT); 557 return (rval); 558 default: 559 device_printf(sc->rl_dev, "bad phy register\n"); 560 return (0); 561 } 562 rval = CSR_READ_2(sc, re8139_reg); 563 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 564 /* 8139C+ has different bit layout. */ 565 rval &= ~(BMCR_LOOP | BMCR_ISO); 566 } 567 return (rval); 568} 569 570static int 571re_miibus_writereg(device_t dev, int phy, int reg, int data) 572{ 573 struct rl_softc *sc; 574 u_int16_t re8139_reg = 0; 575 int rval = 0; 576 577 sc = device_get_softc(dev); 578 579 if (sc->rl_type == RL_8169) { 580 rval = re_gmii_writereg(dev, phy, reg, data); 581 return (rval); 582 } 583 584 switch (reg) { 585 case MII_BMCR: 586 re8139_reg = RL_BMCR; 587 if (sc->rl_type == RL_8139CPLUS) { 588 /* 8139C+ has different bit layout. */ 589 data &= ~(BMCR_LOOP | BMCR_ISO); 590 } 591 break; 592 case MII_BMSR: 593 re8139_reg = RL_BMSR; 594 break; 595 case MII_ANAR: 596 re8139_reg = RL_ANAR; 597 break; 598 case MII_ANER: 599 re8139_reg = RL_ANER; 600 break; 601 case MII_ANLPAR: 602 re8139_reg = RL_LPAR; 603 break; 604 case MII_PHYIDR1: 605 case MII_PHYIDR2: 606 return (0); 607 break; 608 default: 609 device_printf(sc->rl_dev, "bad phy register\n"); 610 return (0); 611 } 612 CSR_WRITE_2(sc, re8139_reg, data); 613 return (0); 614} 615 616static void 617re_miibus_statchg(device_t dev) 618{ 619 struct rl_softc *sc; 620 if_t ifp; 621 struct mii_data *mii; 622 623 sc = device_get_softc(dev); 624 mii = device_get_softc(sc->rl_miibus); 625 ifp = sc->rl_ifp; 626 if (mii == NULL || ifp == NULL || 627 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 628 return; 629 630 sc->rl_flags &= ~RL_FLAG_LINK; 631 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 632 (IFM_ACTIVE | IFM_AVALID)) { 633 switch (IFM_SUBTYPE(mii->mii_media_active)) { 634 case IFM_10_T: 635 case IFM_100_TX: 636 sc->rl_flags |= RL_FLAG_LINK; 637 break; 638 case IFM_1000_T: 639 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 640 break; 641 sc->rl_flags |= RL_FLAG_LINK; 642 break; 643 default: 644 break; 645 } 646 } 647 /* 648 * RealTek controllers do not provide any interface to the RX/TX 649 * MACs for resolved speed, duplex and flow-control parameters. 650 */ 651} 652 653static u_int 654re_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 655{ 656 uint32_t h, *hashes = arg; 657 658 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26; 659 if (h < 32) 660 hashes[0] |= (1 << h); 661 else 662 hashes[1] |= (1 << (h - 32)); 663 664 return (1); 665} 666 667/* 668 * Set the RX configuration and 64-bit multicast hash filter. 669 */ 670static void 671re_set_rxmode(struct rl_softc *sc) 672{ 673 if_t ifp; 674 uint32_t h, hashes[2] = { 0, 0 }; 675 uint32_t rxfilt; 676 677 RL_LOCK_ASSERT(sc); 678 679 ifp = sc->rl_ifp; 680 681 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 682 if ((sc->rl_flags & RL_FLAG_EARLYOFF) != 0) 683 rxfilt |= RL_RXCFG_EARLYOFF; 684 else if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) 685 rxfilt |= RL_RXCFG_EARLYOFFV2; 686 687 if (if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) { 688 if (if_getflags(ifp) & IFF_PROMISC) 689 rxfilt |= RL_RXCFG_RX_ALLPHYS; 690 /* 691 * Unlike other hardwares, we have to explicitly set 692 * RL_RXCFG_RX_MULTI to receive multicast frames in 693 * promiscuous mode. 694 */ 695 rxfilt |= RL_RXCFG_RX_MULTI; 696 hashes[0] = hashes[1] = 0xffffffff; 697 goto done; 698 } 699 700 if_foreach_llmaddr(ifp, re_hash_maddr, hashes); 701 702 if (hashes[0] != 0 || hashes[1] != 0) { 703 /* 704 * For some unfathomable reason, RealTek decided to 705 * reverse the order of the multicast hash registers 706 * in the PCI Express parts. This means we have to 707 * write the hash pattern in reverse order for those 708 * devices. 709 */ 710 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 711 h = bswap32(hashes[0]); 712 hashes[0] = bswap32(hashes[1]); 713 hashes[1] = h; 714 } 715 rxfilt |= RL_RXCFG_RX_MULTI; 716 } 717 718 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168F) { 719 /* Disable multicast filtering due to silicon bug. */ 720 hashes[0] = 0xffffffff; 721 hashes[1] = 0xffffffff; 722 } 723 724done: 725 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 726 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 727 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 728} 729 730static void 731re_reset(struct rl_softc *sc) 732{ 733 int i; 734 735 RL_LOCK_ASSERT(sc); 736 737 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 738 739 for (i = 0; i < RL_TIMEOUT; i++) { 740 DELAY(10); 741 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 742 break; 743 } 744 if (i == RL_TIMEOUT) 745 device_printf(sc->rl_dev, "reset never completed!\n"); 746 747 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 748 CSR_WRITE_1(sc, 0x82, 1); 749 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S) 750 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 751} 752 753#ifdef RE_DIAG 754 755/* 756 * The following routine is designed to test for a defect on some 757 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 758 * lines connected to the bus, however for a 32-bit only card, they 759 * should be pulled high. The result of this defect is that the 760 * NIC will not work right if you plug it into a 64-bit slot: DMA 761 * operations will be done with 64-bit transfers, which will fail 762 * because the 64-bit data lines aren't connected. 763 * 764 * There's no way to work around this (short of talking a soldering 765 * iron to the board), however we can detect it. The method we use 766 * here is to put the NIC into digital loopback mode, set the receiver 767 * to promiscuous mode, and then try to send a frame. We then compare 768 * the frame data we sent to what was received. If the data matches, 769 * then the NIC is working correctly, otherwise we know the user has 770 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 771 * slot. In the latter case, there's no way the NIC can work correctly, 772 * so we print out a message on the console and abort the device attach. 773 */ 774 775static int 776re_diag(struct rl_softc *sc) 777{ 778 if_t ifp = sc->rl_ifp; 779 struct mbuf *m0; 780 struct ether_header *eh; 781 struct rl_desc *cur_rx; 782 u_int16_t status; 783 u_int32_t rxstat; 784 int total_len, i, error = 0, phyaddr; 785 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 786 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 787 788 /* Allocate a single mbuf */ 789 MGETHDR(m0, M_NOWAIT, MT_DATA); 790 if (m0 == NULL) 791 return (ENOBUFS); 792 793 RL_LOCK(sc); 794 795 /* 796 * Initialize the NIC in test mode. This sets the chip up 797 * so that it can send and receive frames, but performs the 798 * following special functions: 799 * - Puts receiver in promiscuous mode 800 * - Enables digital loopback mode 801 * - Leaves interrupts turned off 802 */ 803 804 if_setflagbit(ifp, IFF_PROMISC, 0); 805 sc->rl_testmode = 1; 806 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 807 re_init_locked(sc); 808 sc->rl_flags |= RL_FLAG_LINK; 809 if (sc->rl_type == RL_8169) 810 phyaddr = 1; 811 else 812 phyaddr = 0; 813 814 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 815 for (i = 0; i < RL_TIMEOUT; i++) { 816 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 817 if (!(status & BMCR_RESET)) 818 break; 819 } 820 821 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 822 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 823 824 DELAY(100000); 825 826 /* Put some data in the mbuf */ 827 828 eh = mtod(m0, struct ether_header *); 829 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 830 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 831 eh->ether_type = htons(ETHERTYPE_IP); 832 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 833 834 /* 835 * Queue the packet, start transmission. 836 * Note: IF_HANDOFF() ultimately calls re_start() for us. 837 */ 838 839 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 840 RL_UNLOCK(sc); 841 /* XXX: re_diag must not be called when in ALTQ mode */ 842 if_handoff(ifp, m0, ifp); 843 RL_LOCK(sc); 844 m0 = NULL; 845 846 /* Wait for it to propagate through the chip */ 847 848 DELAY(100000); 849 for (i = 0; i < RL_TIMEOUT; i++) { 850 status = CSR_READ_2(sc, RL_ISR); 851 CSR_WRITE_2(sc, RL_ISR, status); 852 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 853 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 854 break; 855 DELAY(10); 856 } 857 858 if (i == RL_TIMEOUT) { 859 device_printf(sc->rl_dev, 860 "diagnostic failed, failed to receive packet in" 861 " loopback mode\n"); 862 error = EIO; 863 goto done; 864 } 865 866 /* 867 * The packet should have been dumped into the first 868 * entry in the RX DMA ring. Grab it from there. 869 */ 870 871 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 872 sc->rl_ldata.rl_rx_list_map, 873 BUS_DMASYNC_POSTREAD); 874 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 875 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 876 BUS_DMASYNC_POSTREAD); 877 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 878 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 879 880 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 881 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 882 eh = mtod(m0, struct ether_header *); 883 884 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 885 total_len = RL_RXBYTES(cur_rx); 886 rxstat = le32toh(cur_rx->rl_cmdstat); 887 888 if (total_len != ETHER_MIN_LEN) { 889 device_printf(sc->rl_dev, 890 "diagnostic failed, received short packet\n"); 891 error = EIO; 892 goto done; 893 } 894 895 /* Test that the received packet data matches what we sent. */ 896 897 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 898 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 899 ntohs(eh->ether_type) != ETHERTYPE_IP) { 900 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 901 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 902 dst, ":", src, ":", ETHERTYPE_IP); 903 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 904 eh->ether_dhost, ":", eh->ether_shost, ":", 905 ntohs(eh->ether_type)); 906 device_printf(sc->rl_dev, "You may have a defective 32-bit " 907 "NIC plugged into a 64-bit PCI slot.\n"); 908 device_printf(sc->rl_dev, "Please re-install the NIC in a " 909 "32-bit slot for proper operation.\n"); 910 device_printf(sc->rl_dev, "Read the re(4) man page for more " 911 "details.\n"); 912 error = EIO; 913 } 914 915done: 916 /* Turn interface off, release resources */ 917 918 sc->rl_testmode = 0; 919 sc->rl_flags &= ~RL_FLAG_LINK; 920 if_setflagbit(ifp, 0, IFF_PROMISC); 921 re_stop(sc); 922 if (m0 != NULL) 923 m_freem(m0); 924 925 RL_UNLOCK(sc); 926 927 return (error); 928} 929 930#endif 931 932/* 933 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 934 * IDs against our list and return a device name if we find a match. 935 */ 936static int 937re_probe(device_t dev) 938{ 939 const struct rl_type *t; 940 uint16_t devid, vendor; 941 uint16_t revid, sdevid; 942 int i; 943 944 vendor = pci_get_vendor(dev); 945 devid = pci_get_device(dev); 946 revid = pci_get_revid(dev); 947 sdevid = pci_get_subdevice(dev); 948 949 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 950 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 951 /* 952 * Only attach to rev. 3 of the Linksys EG1032 adapter. 953 * Rev. 2 is supported by sk(4). 954 */ 955 return (ENXIO); 956 } 957 } 958 959 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 960 if (revid != 0x20) { 961 /* 8139, let rl(4) take care of this device. */ 962 return (ENXIO); 963 } 964 } 965 966 t = re_devs; 967 for (i = 0; i < nitems(re_devs); i++, t++) { 968 if (vendor == t->rl_vid && devid == t->rl_did) { 969 device_set_desc(dev, t->rl_name); 970 return (BUS_PROBE_DEFAULT); 971 } 972 } 973 974 return (ENXIO); 975} 976 977/* 978 * Map a single buffer address. 979 */ 980 981static void 982re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 983{ 984 bus_addr_t *addr; 985 986 if (error) 987 return; 988 989 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 990 addr = arg; 991 *addr = segs->ds_addr; 992} 993 994static int 995re_allocmem(device_t dev, struct rl_softc *sc) 996{ 997 bus_addr_t lowaddr; 998 bus_size_t rx_list_size, tx_list_size; 999 int error; 1000 int i; 1001 1002 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 1003 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 1004 1005 /* 1006 * Allocate the parent bus DMA tag appropriate for PCI. 1007 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 1008 * register should be set. However some RealTek chips are known 1009 * to be buggy on DAC handling, therefore disable DAC by limiting 1010 * DMA address space to 32bit. PCIe variants of RealTek chips 1011 * may not have the limitation. 1012 */ 1013 lowaddr = BUS_SPACE_MAXADDR; 1014 if ((sc->rl_flags & RL_FLAG_PCIE) == 0) 1015 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1016 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1017 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 1018 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 1019 NULL, NULL, &sc->rl_parent_tag); 1020 if (error) { 1021 device_printf(dev, "could not allocate parent DMA tag\n"); 1022 return (error); 1023 } 1024 1025 /* 1026 * Allocate map for TX mbufs. 1027 */ 1028 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 1029 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1030 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 1031 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 1032 if (error) { 1033 device_printf(dev, "could not allocate TX DMA tag\n"); 1034 return (error); 1035 } 1036 1037 /* 1038 * Allocate map for RX mbufs. 1039 */ 1040 1041 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1042 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 1043 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1044 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL, 1045 &sc->rl_ldata.rl_jrx_mtag); 1046 if (error) { 1047 device_printf(dev, 1048 "could not allocate jumbo RX DMA tag\n"); 1049 return (error); 1050 } 1051 } 1052 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1053 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1054 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1055 if (error) { 1056 device_printf(dev, "could not allocate RX DMA tag\n"); 1057 return (error); 1058 } 1059 1060 /* 1061 * Allocate map for TX descriptor list. 1062 */ 1063 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1064 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1065 NULL, tx_list_size, 1, tx_list_size, 0, 1066 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1067 if (error) { 1068 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1069 return (error); 1070 } 1071 1072 /* Allocate DMA'able memory for the TX ring */ 1073 1074 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1075 (void **)&sc->rl_ldata.rl_tx_list, 1076 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1077 &sc->rl_ldata.rl_tx_list_map); 1078 if (error) { 1079 device_printf(dev, "could not allocate TX DMA ring\n"); 1080 return (error); 1081 } 1082 1083 /* Load the map for the TX ring. */ 1084 1085 sc->rl_ldata.rl_tx_list_addr = 0; 1086 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1087 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1088 tx_list_size, re_dma_map_addr, 1089 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1090 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1091 device_printf(dev, "could not load TX DMA ring\n"); 1092 return (ENOMEM); 1093 } 1094 1095 /* Create DMA maps for TX buffers */ 1096 1097 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1098 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1099 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1100 if (error) { 1101 device_printf(dev, "could not create DMA map for TX\n"); 1102 return (error); 1103 } 1104 } 1105 1106 /* 1107 * Allocate map for RX descriptor list. 1108 */ 1109 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1110 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1111 NULL, rx_list_size, 1, rx_list_size, 0, 1112 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1113 if (error) { 1114 device_printf(dev, "could not create RX DMA ring tag\n"); 1115 return (error); 1116 } 1117 1118 /* Allocate DMA'able memory for the RX ring */ 1119 1120 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1121 (void **)&sc->rl_ldata.rl_rx_list, 1122 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1123 &sc->rl_ldata.rl_rx_list_map); 1124 if (error) { 1125 device_printf(dev, "could not allocate RX DMA ring\n"); 1126 return (error); 1127 } 1128 1129 /* Load the map for the RX ring. */ 1130 1131 sc->rl_ldata.rl_rx_list_addr = 0; 1132 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1133 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1134 rx_list_size, re_dma_map_addr, 1135 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1136 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1137 device_printf(dev, "could not load RX DMA ring\n"); 1138 return (ENOMEM); 1139 } 1140 1141 /* Create DMA maps for RX buffers */ 1142 1143 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1144 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1145 &sc->rl_ldata.rl_jrx_sparemap); 1146 if (error) { 1147 device_printf(dev, 1148 "could not create spare DMA map for jumbo RX\n"); 1149 return (error); 1150 } 1151 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1152 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1153 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1154 if (error) { 1155 device_printf(dev, 1156 "could not create DMA map for jumbo RX\n"); 1157 return (error); 1158 } 1159 } 1160 } 1161 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1162 &sc->rl_ldata.rl_rx_sparemap); 1163 if (error) { 1164 device_printf(dev, "could not create spare DMA map for RX\n"); 1165 return (error); 1166 } 1167 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1168 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1169 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1170 if (error) { 1171 device_printf(dev, "could not create DMA map for RX\n"); 1172 return (error); 1173 } 1174 } 1175 1176 /* Create DMA map for statistics. */ 1177 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0, 1178 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1179 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL, 1180 &sc->rl_ldata.rl_stag); 1181 if (error) { 1182 device_printf(dev, "could not create statistics DMA tag\n"); 1183 return (error); 1184 } 1185 /* Allocate DMA'able memory for statistics. */ 1186 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag, 1187 (void **)&sc->rl_ldata.rl_stats, 1188 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1189 &sc->rl_ldata.rl_smap); 1190 if (error) { 1191 device_printf(dev, 1192 "could not allocate statistics DMA memory\n"); 1193 return (error); 1194 } 1195 /* Load the map for statistics. */ 1196 sc->rl_ldata.rl_stats_addr = 0; 1197 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap, 1198 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr, 1199 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT); 1200 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) { 1201 device_printf(dev, "could not load statistics DMA memory\n"); 1202 return (ENOMEM); 1203 } 1204 1205 return (0); 1206} 1207 1208/* 1209 * Attach the interface. Allocate softc structures, do ifmedia 1210 * setup and ethernet/BPF attach. 1211 */ 1212static int 1213re_attach(device_t dev) 1214{ 1215 u_char eaddr[ETHER_ADDR_LEN]; 1216 u_int16_t as[ETHER_ADDR_LEN / 2]; 1217 struct rl_softc *sc; 1218 if_t ifp; 1219 const struct rl_hwrev *hw_rev; 1220 int capmask, error = 0, hwrev, i, msic, msixc, 1221 phy, reg, rid; 1222 u_int32_t cap, ctl; 1223 u_int16_t devid, re_did = 0; 1224 uint8_t cfg; 1225 1226 sc = device_get_softc(dev); 1227 sc->rl_dev = dev; 1228 1229 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1230 MTX_DEF); 1231 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1232 1233 /* 1234 * Map control/status registers. 1235 */ 1236 pci_enable_busmaster(dev); 1237 1238 devid = pci_get_device(dev); 1239 /* 1240 * Prefer memory space register mapping over IO space. 1241 * Because RTL8169SC does not seem to work when memory mapping 1242 * is used always activate io mapping. 1243 */ 1244 if (devid == RT_DEVICEID_8169SC) 1245 prefer_iomap = 1; 1246 if (prefer_iomap == 0) { 1247 sc->rl_res_id = PCIR_BAR(1); 1248 sc->rl_res_type = SYS_RES_MEMORY; 1249 /* RTL8168/8101E seems to use different BARs. */ 1250 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1251 sc->rl_res_id = PCIR_BAR(2); 1252 } else { 1253 sc->rl_res_id = PCIR_BAR(0); 1254 sc->rl_res_type = SYS_RES_IOPORT; 1255 } 1256 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1257 &sc->rl_res_id, RF_ACTIVE); 1258 if (sc->rl_res == NULL && prefer_iomap == 0) { 1259 sc->rl_res_id = PCIR_BAR(0); 1260 sc->rl_res_type = SYS_RES_IOPORT; 1261 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1262 &sc->rl_res_id, RF_ACTIVE); 1263 } 1264 if (sc->rl_res == NULL) { 1265 device_printf(dev, "couldn't map ports/memory\n"); 1266 error = ENXIO; 1267 goto fail; 1268 } 1269 1270 sc->rl_btag = rman_get_bustag(sc->rl_res); 1271 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1272 1273 msic = pci_msi_count(dev); 1274 msixc = pci_msix_count(dev); 1275 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 1276 sc->rl_flags |= RL_FLAG_PCIE; 1277 sc->rl_expcap = reg; 1278 } 1279 if (bootverbose) { 1280 device_printf(dev, "MSI count : %d\n", msic); 1281 device_printf(dev, "MSI-X count : %d\n", msixc); 1282 } 1283 if (msix_disable > 0) 1284 msixc = 0; 1285 if (msi_disable > 0) 1286 msic = 0; 1287 /* Prefer MSI-X to MSI. */ 1288 if (msixc > 0) { 1289 msixc = RL_MSI_MESSAGES; 1290 rid = PCIR_BAR(4); 1291 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1292 &rid, RF_ACTIVE); 1293 if (sc->rl_res_pba == NULL) { 1294 device_printf(sc->rl_dev, 1295 "could not allocate MSI-X PBA resource\n"); 1296 } 1297 if (sc->rl_res_pba != NULL && 1298 pci_alloc_msix(dev, &msixc) == 0) { 1299 if (msixc == RL_MSI_MESSAGES) { 1300 device_printf(dev, "Using %d MSI-X message\n", 1301 msixc); 1302 sc->rl_flags |= RL_FLAG_MSIX; 1303 } else 1304 pci_release_msi(dev); 1305 } 1306 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) { 1307 if (sc->rl_res_pba != NULL) 1308 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1309 sc->rl_res_pba); 1310 sc->rl_res_pba = NULL; 1311 msixc = 0; 1312 } 1313 } 1314 /* Prefer MSI to INTx. */ 1315 if (msixc == 0 && msic > 0) { 1316 msic = RL_MSI_MESSAGES; 1317 if (pci_alloc_msi(dev, &msic) == 0) { 1318 if (msic == RL_MSI_MESSAGES) { 1319 device_printf(dev, "Using %d MSI message\n", 1320 msic); 1321 sc->rl_flags |= RL_FLAG_MSI; 1322 /* Explicitly set MSI enable bit. */ 1323 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1324 cfg = CSR_READ_1(sc, RL_CFG2); 1325 cfg |= RL_CFG2_MSI; 1326 CSR_WRITE_1(sc, RL_CFG2, cfg); 1327 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1328 } else 1329 pci_release_msi(dev); 1330 } 1331 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1332 msic = 0; 1333 } 1334 1335 /* Allocate interrupt */ 1336 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) { 1337 rid = 0; 1338 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1339 RF_SHAREABLE | RF_ACTIVE); 1340 if (sc->rl_irq[0] == NULL) { 1341 device_printf(dev, "couldn't allocate IRQ resources\n"); 1342 error = ENXIO; 1343 goto fail; 1344 } 1345 } else { 1346 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1347 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1348 SYS_RES_IRQ, &rid, RF_ACTIVE); 1349 if (sc->rl_irq[i] == NULL) { 1350 device_printf(dev, 1351 "couldn't allocate IRQ resources for " 1352 "message %d\n", rid); 1353 error = ENXIO; 1354 goto fail; 1355 } 1356 } 1357 } 1358 1359 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1360 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1361 cfg = CSR_READ_1(sc, RL_CFG2); 1362 if ((cfg & RL_CFG2_MSI) != 0) { 1363 device_printf(dev, "turning off MSI enable bit.\n"); 1364 cfg &= ~RL_CFG2_MSI; 1365 CSR_WRITE_1(sc, RL_CFG2, cfg); 1366 } 1367 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1368 } 1369 1370 /* Disable ASPM L0S/L1 and CLKREQ. */ 1371 if (sc->rl_expcap != 0) { 1372 cap = pci_read_config(dev, sc->rl_expcap + 1373 PCIER_LINK_CAP, 2); 1374 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1375 ctl = pci_read_config(dev, sc->rl_expcap + 1376 PCIER_LINK_CTL, 2); 1377 if ((ctl & (PCIEM_LINK_CTL_ECPM | 1378 PCIEM_LINK_CTL_ASPMC))!= 0) { 1379 ctl &= ~(PCIEM_LINK_CTL_ECPM | 1380 PCIEM_LINK_CTL_ASPMC); 1381 pci_write_config(dev, sc->rl_expcap + 1382 PCIER_LINK_CTL, ctl, 2); 1383 device_printf(dev, "ASPM disabled\n"); 1384 } 1385 } else 1386 device_printf(dev, "no ASPM capability\n"); 1387 } 1388 1389 hw_rev = re_hwrevs; 1390 hwrev = CSR_READ_4(sc, RL_TXCFG); 1391 switch (hwrev & 0x70000000) { 1392 case 0x00000000: 1393 case 0x10000000: 1394 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1395 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1396 break; 1397 default: 1398 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1399 sc->rl_macrev = hwrev & 0x00700000; 1400 hwrev &= RL_TXCFG_HWREV; 1401 break; 1402 } 1403 device_printf(dev, "MAC rev. 0x%08x\n", sc->rl_macrev); 1404 while (hw_rev->rl_desc != NULL) { 1405 if (hw_rev->rl_rev == hwrev) { 1406 sc->rl_type = hw_rev->rl_type; 1407 sc->rl_hwrev = hw_rev; 1408 break; 1409 } 1410 hw_rev++; 1411 } 1412 if (hw_rev->rl_desc == NULL) { 1413 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1414 error = ENXIO; 1415 goto fail; 1416 } 1417 1418 switch (hw_rev->rl_rev) { 1419 case RL_HWREV_8139CPLUS: 1420 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD; 1421 break; 1422 case RL_HWREV_8100E: 1423 case RL_HWREV_8101E: 1424 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER; 1425 break; 1426 case RL_HWREV_8102E: 1427 case RL_HWREV_8102EL: 1428 case RL_HWREV_8102EL_SPIN1: 1429 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1430 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1431 RL_FLAG_AUTOPAD; 1432 break; 1433 case RL_HWREV_8103E: 1434 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1435 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1436 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP; 1437 break; 1438 case RL_HWREV_8401E: 1439 case RL_HWREV_8105E: 1440 case RL_HWREV_8105E_SPIN1: 1441 case RL_HWREV_8106E: 1442 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1443 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1444 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 1445 break; 1446 case RL_HWREV_8402: 1447 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1448 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1449 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | 1450 RL_FLAG_CMDSTOP_WAIT_TXQ; 1451 break; 1452 case RL_HWREV_8168B_SPIN1: 1453 case RL_HWREV_8168B_SPIN2: 1454 sc->rl_flags |= RL_FLAG_WOLRXENB; 1455 /* FALLTHROUGH */ 1456 case RL_HWREV_8168B_SPIN3: 1457 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1458 break; 1459 case RL_HWREV_8168C_SPIN2: 1460 sc->rl_flags |= RL_FLAG_MACSLEEP; 1461 /* FALLTHROUGH */ 1462 case RL_HWREV_8168C: 1463 if (sc->rl_macrev == 0x00200000) 1464 sc->rl_flags |= RL_FLAG_MACSLEEP; 1465 /* FALLTHROUGH */ 1466 case RL_HWREV_8168CP: 1467 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1468 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1469 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1470 break; 1471 case RL_HWREV_8168D: 1472 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1473 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1474 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1475 RL_FLAG_WOL_MANLINK; 1476 break; 1477 case RL_HWREV_8168DP: 1478 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1479 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD | 1480 RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK; 1481 break; 1482 case RL_HWREV_8168E: 1483 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1484 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1485 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1486 RL_FLAG_WOL_MANLINK; 1487 break; 1488 case RL_HWREV_8168E_VL: 1489 case RL_HWREV_8168F: 1490 sc->rl_flags |= RL_FLAG_EARLYOFF; 1491 /* FALLTHROUGH */ 1492 case RL_HWREV_8411: 1493 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1494 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1495 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1496 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK; 1497 break; 1498 case RL_HWREV_8168EP: 1499 case RL_HWREV_8168FP: 1500 case RL_HWREV_8168G: 1501 case RL_HWREV_8411B: 1502 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1503 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1504 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1505 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK | 1506 RL_FLAG_8168G_PLUS; 1507 break; 1508 case RL_HWREV_8168GU: 1509 case RL_HWREV_8168H: 1510 if (pci_get_device(dev) == RT_DEVICEID_8101E) { 1511 /* RTL8106E(US), RTL8107E */ 1512 sc->rl_flags |= RL_FLAG_FASTETHER; 1513 } else 1514 sc->rl_flags |= RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1515 1516 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1517 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1518 RL_FLAG_AUTOPAD | RL_FLAG_CMDSTOP_WAIT_TXQ | 1519 RL_FLAG_8168G_PLUS; 1520 break; 1521 case RL_HWREV_8169_8110SB: 1522 case RL_HWREV_8169_8110SBL: 1523 case RL_HWREV_8169_8110SC: 1524 case RL_HWREV_8169_8110SCE: 1525 sc->rl_flags |= RL_FLAG_PHYWAKE; 1526 /* FALLTHROUGH */ 1527 case RL_HWREV_8169: 1528 case RL_HWREV_8169S: 1529 case RL_HWREV_8110S: 1530 sc->rl_flags |= RL_FLAG_MACRESET; 1531 break; 1532 default: 1533 break; 1534 } 1535 1536 if (sc->rl_hwrev->rl_rev == RL_HWREV_8139CPLUS) { 1537 sc->rl_cfg0 = RL_8139_CFG0; 1538 sc->rl_cfg1 = RL_8139_CFG1; 1539 sc->rl_cfg2 = 0; 1540 sc->rl_cfg3 = RL_8139_CFG3; 1541 sc->rl_cfg4 = RL_8139_CFG4; 1542 sc->rl_cfg5 = RL_8139_CFG5; 1543 } else { 1544 sc->rl_cfg0 = RL_CFG0; 1545 sc->rl_cfg1 = RL_CFG1; 1546 sc->rl_cfg2 = RL_CFG2; 1547 sc->rl_cfg3 = RL_CFG3; 1548 sc->rl_cfg4 = RL_CFG4; 1549 sc->rl_cfg5 = RL_CFG5; 1550 } 1551 1552 /* Reset the adapter. */ 1553 RL_LOCK(sc); 1554 re_reset(sc); 1555 RL_UNLOCK(sc); 1556 1557 /* Enable PME. */ 1558 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1559 cfg = CSR_READ_1(sc, sc->rl_cfg1); 1560 cfg |= RL_CFG1_PME; 1561 CSR_WRITE_1(sc, sc->rl_cfg1, cfg); 1562 cfg = CSR_READ_1(sc, sc->rl_cfg5); 1563 cfg &= RL_CFG5_PME_STS; 1564 CSR_WRITE_1(sc, sc->rl_cfg5, cfg); 1565 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1566 1567 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1568 /* 1569 * XXX Should have a better way to extract station 1570 * address from EEPROM. 1571 */ 1572 for (i = 0; i < ETHER_ADDR_LEN; i++) 1573 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1574 } else { 1575 sc->rl_eewidth = RL_9356_ADDR_LEN; 1576 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1577 if (re_did != 0x8129) 1578 sc->rl_eewidth = RL_9346_ADDR_LEN; 1579 1580 /* 1581 * Get station address from the EEPROM. 1582 */ 1583 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1584 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1585 as[i] = le16toh(as[i]); 1586 bcopy(as, eaddr, ETHER_ADDR_LEN); 1587 } 1588 1589 if (sc->rl_type == RL_8169) { 1590 /* Set RX length mask and number of descriptors. */ 1591 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1592 sc->rl_txstart = RL_GTXSTART; 1593 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1594 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1595 } else { 1596 /* Set RX length mask and number of descriptors. */ 1597 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1598 sc->rl_txstart = RL_TXSTART; 1599 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1600 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1601 } 1602 1603 error = re_allocmem(dev, sc); 1604 if (error) 1605 goto fail; 1606 re_add_sysctls(sc); 1607 1608 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1609 if (ifp == NULL) { 1610 device_printf(dev, "can not if_alloc()\n"); 1611 error = ENOSPC; 1612 goto fail; 1613 } 1614 1615 /* Take controller out of deep sleep mode. */ 1616 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1617 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1618 CSR_WRITE_1(sc, RL_GPIO, 1619 CSR_READ_1(sc, RL_GPIO) | 0x01); 1620 else 1621 CSR_WRITE_1(sc, RL_GPIO, 1622 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1623 } 1624 1625 /* Take PHY out of power down mode. */ 1626 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) { 1627 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); 1628 if (hw_rev->rl_rev == RL_HWREV_8401E) 1629 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08); 1630 } 1631 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1632 re_gmii_writereg(dev, 1, 0x1f, 0); 1633 re_gmii_writereg(dev, 1, 0x0e, 0); 1634 } 1635 1636 if_setsoftc(ifp, sc); 1637 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1638 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1639 if_setioctlfn(ifp, re_ioctl); 1640 if_setstartfn(ifp, re_start); 1641 /* 1642 * RTL8168/8111C generates wrong IP checksummed frame if the 1643 * packet has IP options so disable TX checksum offloading. 1644 */ 1645 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C || 1646 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2 || 1647 sc->rl_hwrev->rl_rev == RL_HWREV_8168CP) { 1648 if_sethwassist(ifp, 0); 1649 if_setcapabilities(ifp, IFCAP_RXCSUM | IFCAP_TSO4); 1650 } else { 1651 if_sethwassist(ifp, CSUM_IP | CSUM_TCP | CSUM_UDP); 1652 if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_TSO4); 1653 } 1654 if_sethwassistbits(ifp, CSUM_TSO, 0); 1655 if_setcapenable(ifp, if_getcapabilities(ifp)); 1656 if_setinitfn(ifp, re_init); 1657 if_setsendqlen(ifp, RL_IFQ_MAXLEN); 1658 if_setsendqready(ifp); 1659 1660 NET_TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1661 1662#define RE_PHYAD_INTERNAL 0 1663 1664 /* Do MII setup. */ 1665 phy = RE_PHYAD_INTERNAL; 1666 if (sc->rl_type == RL_8169) 1667 phy = 1; 1668 capmask = BMSR_DEFCAPMASK; 1669 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 1670 capmask &= ~BMSR_EXTSTAT; 1671 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd, 1672 re_ifmedia_sts, capmask, phy, MII_OFFSET_ANY, MIIF_DOPAUSE); 1673 if (error != 0) { 1674 device_printf(dev, "attaching PHYs failed\n"); 1675 goto fail; 1676 } 1677 1678 /* If address was not found, create one based on the hostid and name. */ 1679 if (ETHER_IS_ZERO(eaddr)) { 1680 ether_gen_addr(ifp, (struct ether_addr *)eaddr); 1681 } 1682 1683 /* 1684 * Call MI attach routine. 1685 */ 1686 ether_ifattach(ifp, eaddr); 1687 1688 /* VLAN capability setup */ 1689 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING, 0); 1690 if (if_getcapabilities(ifp) & IFCAP_HWCSUM) 1691 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0); 1692 /* Enable WOL if PM is supported. */ 1693 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0) 1694 if_setcapabilitiesbit(ifp, IFCAP_WOL, 0); 1695 if_setcapenable(ifp, if_getcapabilities(ifp)); 1696 if_setcapenablebit(ifp, 0, (IFCAP_WOL_UCAST | IFCAP_WOL_MCAST)); 1697 /* 1698 * Don't enable TSO by default. It is known to generate 1699 * corrupted TCP segments(bad TCP options) under certain 1700 * circumstances. 1701 */ 1702 if_sethwassistbits(ifp, 0, CSUM_TSO); 1703 if_setcapenablebit(ifp, 0, (IFCAP_TSO4 | IFCAP_VLAN_HWTSO)); 1704#ifdef DEVICE_POLLING 1705 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 1706#endif 1707 /* 1708 * Tell the upper layer(s) we support long frames. 1709 * Must appear after the call to ether_ifattach() because 1710 * ether_ifattach() sets ifi_hdrlen to the default value. 1711 */ 1712 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 1713 1714#ifdef DEV_NETMAP 1715 re_netmap_attach(sc); 1716#endif /* DEV_NETMAP */ 1717 1718#ifdef RE_DIAG 1719 /* 1720 * Perform hardware diagnostic on the original RTL8169. 1721 * Some 32-bit cards were incorrectly wired and would 1722 * malfunction if plugged into a 64-bit slot. 1723 */ 1724 if (hwrev == RL_HWREV_8169) { 1725 error = re_diag(sc); 1726 if (error) { 1727 device_printf(dev, 1728 "attach aborted due to hardware diag failure\n"); 1729 ether_ifdetach(ifp); 1730 goto fail; 1731 } 1732 } 1733#endif 1734 1735#ifdef RE_TX_MODERATION 1736 intr_filter = 1; 1737#endif 1738 /* Hook interrupt last to avoid having to lock softc */ 1739 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 1740 intr_filter == 0) { 1741 error = bus_setup_intr(dev, sc->rl_irq[0], 1742 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc, 1743 &sc->rl_intrhand[0]); 1744 } else { 1745 error = bus_setup_intr(dev, sc->rl_irq[0], 1746 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1747 &sc->rl_intrhand[0]); 1748 } 1749 if (error) { 1750 device_printf(dev, "couldn't set up irq\n"); 1751 ether_ifdetach(ifp); 1752 goto fail; 1753 } 1754 1755 DEBUGNET_SET(ifp, re); 1756 1757fail: 1758 if (error) 1759 re_detach(dev); 1760 1761 return (error); 1762} 1763 1764/* 1765 * Shutdown hardware and free up resources. This can be called any 1766 * time after the mutex has been initialized. It is called in both 1767 * the error case in attach and the normal detach case so it needs 1768 * to be careful about only freeing resources that have actually been 1769 * allocated. 1770 */ 1771static int 1772re_detach(device_t dev) 1773{ 1774 struct rl_softc *sc; 1775 if_t ifp; 1776 int i, rid; 1777 1778 sc = device_get_softc(dev); 1779 ifp = sc->rl_ifp; 1780 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1781 1782 /* These should only be active if attach succeeded */ 1783 if (device_is_attached(dev)) { 1784#ifdef DEVICE_POLLING 1785 if (if_getcapenable(ifp) & IFCAP_POLLING) 1786 ether_poll_deregister(ifp); 1787#endif 1788 RL_LOCK(sc); 1789#if 0 1790 sc->suspended = 1; 1791#endif 1792 re_stop(sc); 1793 RL_UNLOCK(sc); 1794 callout_drain(&sc->rl_stat_callout); 1795 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1796 /* 1797 * Force off the IFF_UP flag here, in case someone 1798 * still had a BPF descriptor attached to this 1799 * interface. If they do, ether_ifdetach() will cause 1800 * the BPF code to try and clear the promisc mode 1801 * flag, which will bubble down to re_ioctl(), 1802 * which will try to call re_init() again. This will 1803 * turn the NIC back on and restart the MII ticker, 1804 * which will panic the system when the kernel tries 1805 * to invoke the re_tick() function that isn't there 1806 * anymore. 1807 */ 1808 if_setflagbits(ifp, 0, IFF_UP); 1809 ether_ifdetach(ifp); 1810 } 1811 if (sc->rl_miibus) 1812 device_delete_child(dev, sc->rl_miibus); 1813 bus_generic_detach(dev); 1814 1815 /* 1816 * The rest is resource deallocation, so we should already be 1817 * stopped here. 1818 */ 1819 1820 if (sc->rl_intrhand[0] != NULL) { 1821 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); 1822 sc->rl_intrhand[0] = NULL; 1823 } 1824 if (ifp != NULL) { 1825#ifdef DEV_NETMAP 1826 netmap_detach(ifp); 1827#endif /* DEV_NETMAP */ 1828 if_free(ifp); 1829 } 1830 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 1831 rid = 0; 1832 else 1833 rid = 1; 1834 if (sc->rl_irq[0] != NULL) { 1835 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]); 1836 sc->rl_irq[0] = NULL; 1837 } 1838 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0) 1839 pci_release_msi(dev); 1840 if (sc->rl_res_pba) { 1841 rid = PCIR_BAR(4); 1842 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba); 1843 } 1844 if (sc->rl_res) 1845 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1846 sc->rl_res); 1847 1848 /* Unload and free the RX DMA ring memory and map */ 1849 1850 if (sc->rl_ldata.rl_rx_list_tag) { 1851 if (sc->rl_ldata.rl_rx_list_addr) 1852 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1853 sc->rl_ldata.rl_rx_list_map); 1854 if (sc->rl_ldata.rl_rx_list) 1855 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1856 sc->rl_ldata.rl_rx_list, 1857 sc->rl_ldata.rl_rx_list_map); 1858 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1859 } 1860 1861 /* Unload and free the TX DMA ring memory and map */ 1862 1863 if (sc->rl_ldata.rl_tx_list_tag) { 1864 if (sc->rl_ldata.rl_tx_list_addr) 1865 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1866 sc->rl_ldata.rl_tx_list_map); 1867 if (sc->rl_ldata.rl_tx_list) 1868 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1869 sc->rl_ldata.rl_tx_list, 1870 sc->rl_ldata.rl_tx_list_map); 1871 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1872 } 1873 1874 /* Destroy all the RX and TX buffer maps */ 1875 1876 if (sc->rl_ldata.rl_tx_mtag) { 1877 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1878 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap) 1879 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1880 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1881 } 1882 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1883 } 1884 if (sc->rl_ldata.rl_rx_mtag) { 1885 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1886 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap) 1887 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1888 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1889 } 1890 if (sc->rl_ldata.rl_rx_sparemap) 1891 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1892 sc->rl_ldata.rl_rx_sparemap); 1893 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1894 } 1895 if (sc->rl_ldata.rl_jrx_mtag) { 1896 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1897 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap) 1898 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1899 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1900 } 1901 if (sc->rl_ldata.rl_jrx_sparemap) 1902 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1903 sc->rl_ldata.rl_jrx_sparemap); 1904 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag); 1905 } 1906 /* Unload and free the stats buffer and map */ 1907 1908 if (sc->rl_ldata.rl_stag) { 1909 if (sc->rl_ldata.rl_stats_addr) 1910 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1911 sc->rl_ldata.rl_smap); 1912 if (sc->rl_ldata.rl_stats) 1913 bus_dmamem_free(sc->rl_ldata.rl_stag, 1914 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap); 1915 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1916 } 1917 1918 if (sc->rl_parent_tag) 1919 bus_dma_tag_destroy(sc->rl_parent_tag); 1920 1921 mtx_destroy(&sc->rl_mtx); 1922 1923 return (0); 1924} 1925 1926static __inline void 1927re_discard_rxbuf(struct rl_softc *sc, int idx) 1928{ 1929 struct rl_desc *desc; 1930 struct rl_rxdesc *rxd; 1931 uint32_t cmdstat; 1932 1933 if (if_getmtu(sc->rl_ifp) > RL_MTU && 1934 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 1935 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1936 else 1937 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1938 desc = &sc->rl_ldata.rl_rx_list[idx]; 1939 desc->rl_vlanctl = 0; 1940 cmdstat = rxd->rx_size; 1941 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1942 cmdstat |= RL_RDESC_CMD_EOR; 1943 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1944} 1945 1946static int 1947re_newbuf(struct rl_softc *sc, int idx) 1948{ 1949 struct mbuf *m; 1950 struct rl_rxdesc *rxd; 1951 bus_dma_segment_t segs[1]; 1952 bus_dmamap_t map; 1953 struct rl_desc *desc; 1954 uint32_t cmdstat; 1955 int error, nsegs; 1956 1957 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1958 if (m == NULL) 1959 return (ENOBUFS); 1960 1961 m->m_len = m->m_pkthdr.len = MCLBYTES; 1962#ifdef RE_FIXUP_RX 1963 /* 1964 * This is part of an evil trick to deal with non-x86 platforms. 1965 * The RealTek chip requires RX buffers to be aligned on 64-bit 1966 * boundaries, but that will hose non-x86 machines. To get around 1967 * this, we leave some empty space at the start of each buffer 1968 * and for non-x86 hosts, we copy the buffer back six bytes 1969 * to achieve word alignment. This is slightly more efficient 1970 * than allocating a new buffer, copying the contents, and 1971 * discarding the old buffer. 1972 */ 1973 m_adj(m, RE_ETHER_ALIGN); 1974#endif 1975 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1976 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1977 if (error != 0) { 1978 m_freem(m); 1979 return (ENOBUFS); 1980 } 1981 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1982 1983 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1984 if (rxd->rx_m != NULL) { 1985 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1986 BUS_DMASYNC_POSTREAD); 1987 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1988 } 1989 1990 rxd->rx_m = m; 1991 map = rxd->rx_dmamap; 1992 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1993 rxd->rx_size = segs[0].ds_len; 1994 sc->rl_ldata.rl_rx_sparemap = map; 1995 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1996 BUS_DMASYNC_PREREAD); 1997 1998 desc = &sc->rl_ldata.rl_rx_list[idx]; 1999 desc->rl_vlanctl = 0; 2000 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 2001 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 2002 cmdstat = segs[0].ds_len; 2003 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 2004 cmdstat |= RL_RDESC_CMD_EOR; 2005 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 2006 2007 return (0); 2008} 2009 2010static int 2011re_jumbo_newbuf(struct rl_softc *sc, int idx) 2012{ 2013 struct mbuf *m; 2014 struct rl_rxdesc *rxd; 2015 bus_dma_segment_t segs[1]; 2016 bus_dmamap_t map; 2017 struct rl_desc *desc; 2018 uint32_t cmdstat; 2019 int error, nsegs; 2020 2021 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 2022 if (m == NULL) 2023 return (ENOBUFS); 2024 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 2025#ifdef RE_FIXUP_RX 2026 m_adj(m, RE_ETHER_ALIGN); 2027#endif 2028 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag, 2029 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 2030 if (error != 0) { 2031 m_freem(m); 2032 return (ENOBUFS); 2033 } 2034 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 2035 2036 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 2037 if (rxd->rx_m != NULL) { 2038 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 2039 BUS_DMASYNC_POSTREAD); 2040 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap); 2041 } 2042 2043 rxd->rx_m = m; 2044 map = rxd->rx_dmamap; 2045 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap; 2046 rxd->rx_size = segs[0].ds_len; 2047 sc->rl_ldata.rl_jrx_sparemap = map; 2048 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 2049 BUS_DMASYNC_PREREAD); 2050 2051 desc = &sc->rl_ldata.rl_rx_list[idx]; 2052 desc->rl_vlanctl = 0; 2053 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 2054 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 2055 cmdstat = segs[0].ds_len; 2056 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 2057 cmdstat |= RL_RDESC_CMD_EOR; 2058 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 2059 2060 return (0); 2061} 2062 2063#ifdef RE_FIXUP_RX 2064static __inline void 2065re_fixup_rx(struct mbuf *m) 2066{ 2067 int i; 2068 uint16_t *src, *dst; 2069 2070 src = mtod(m, uint16_t *); 2071 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 2072 2073 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2074 *dst++ = *src++; 2075 2076 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 2077} 2078#endif 2079 2080static int 2081re_tx_list_init(struct rl_softc *sc) 2082{ 2083 struct rl_desc *desc; 2084 int i; 2085 2086 RL_LOCK_ASSERT(sc); 2087 2088 bzero(sc->rl_ldata.rl_tx_list, 2089 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 2090 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 2091 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 2092#ifdef DEV_NETMAP 2093 re_netmap_tx_init(sc); 2094#endif /* DEV_NETMAP */ 2095 /* Set EOR. */ 2096 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 2097 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 2098 2099 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2100 sc->rl_ldata.rl_tx_list_map, 2101 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2102 2103 sc->rl_ldata.rl_tx_prodidx = 0; 2104 sc->rl_ldata.rl_tx_considx = 0; 2105 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 2106 2107 return (0); 2108} 2109 2110static int 2111re_rx_list_init(struct rl_softc *sc) 2112{ 2113 int error, i; 2114 2115 bzero(sc->rl_ldata.rl_rx_list, 2116 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2117 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2118 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 2119 if ((error = re_newbuf(sc, i)) != 0) 2120 return (error); 2121 } 2122#ifdef DEV_NETMAP 2123 re_netmap_rx_init(sc); 2124#endif /* DEV_NETMAP */ 2125 2126 /* Flush the RX descriptors */ 2127 2128 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2129 sc->rl_ldata.rl_rx_list_map, 2130 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2131 2132 sc->rl_ldata.rl_rx_prodidx = 0; 2133 sc->rl_head = sc->rl_tail = NULL; 2134 sc->rl_int_rx_act = 0; 2135 2136 return (0); 2137} 2138 2139static int 2140re_jrx_list_init(struct rl_softc *sc) 2141{ 2142 int error, i; 2143 2144 bzero(sc->rl_ldata.rl_rx_list, 2145 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2146 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2147 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL; 2148 if ((error = re_jumbo_newbuf(sc, i)) != 0) 2149 return (error); 2150 } 2151 2152 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2153 sc->rl_ldata.rl_rx_list_map, 2154 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2155 2156 sc->rl_ldata.rl_rx_prodidx = 0; 2157 sc->rl_head = sc->rl_tail = NULL; 2158 sc->rl_int_rx_act = 0; 2159 2160 return (0); 2161} 2162 2163/* 2164 * RX handler for C+ and 8169. For the gigE chips, we support 2165 * the reception of jumbo frames that have been fragmented 2166 * across multiple 2K mbuf cluster buffers. 2167 */ 2168static int 2169re_rxeof(struct rl_softc *sc, int *rx_npktsp) 2170{ 2171 struct mbuf *m; 2172 if_t ifp; 2173 int i, rxerr, total_len; 2174 struct rl_desc *cur_rx; 2175 u_int32_t rxstat, rxvlan; 2176 int jumbo, maxpkt = 16, rx_npkts = 0; 2177 2178 RL_LOCK_ASSERT(sc); 2179 2180 ifp = sc->rl_ifp; 2181#ifdef DEV_NETMAP 2182 if (netmap_rx_irq(ifp, 0, &rx_npkts)) 2183 return 0; 2184#endif /* DEV_NETMAP */ 2185 if (if_getmtu(ifp) > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 2186 jumbo = 1; 2187 else 2188 jumbo = 0; 2189 2190 /* Invalidate the descriptor memory */ 2191 2192 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2193 sc->rl_ldata.rl_rx_list_map, 2194 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2195 2196 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 2197 i = RL_RX_DESC_NXT(sc, i)) { 2198 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 2199 break; 2200 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 2201 rxstat = le32toh(cur_rx->rl_cmdstat); 2202 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 2203 break; 2204 total_len = rxstat & sc->rl_rxlenmask; 2205 rxvlan = le32toh(cur_rx->rl_vlanctl); 2206 if (jumbo != 0) 2207 m = sc->rl_ldata.rl_jrx_desc[i].rx_m; 2208 else 2209 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 2210 2211 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 2212 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) != 2213 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) { 2214 /* 2215 * RTL8168C or later controllers do not 2216 * support multi-fragment packet. 2217 */ 2218 re_discard_rxbuf(sc, i); 2219 continue; 2220 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) { 2221 if (re_newbuf(sc, i) != 0) { 2222 /* 2223 * If this is part of a multi-fragment packet, 2224 * discard all the pieces. 2225 */ 2226 if (sc->rl_head != NULL) { 2227 m_freem(sc->rl_head); 2228 sc->rl_head = sc->rl_tail = NULL; 2229 } 2230 re_discard_rxbuf(sc, i); 2231 continue; 2232 } 2233 m->m_len = RE_RX_DESC_BUFLEN; 2234 if (sc->rl_head == NULL) 2235 sc->rl_head = sc->rl_tail = m; 2236 else { 2237 m->m_flags &= ~M_PKTHDR; 2238 sc->rl_tail->m_next = m; 2239 sc->rl_tail = m; 2240 } 2241 continue; 2242 } 2243 2244 /* 2245 * NOTE: for the 8139C+, the frame length field 2246 * is always 12 bits in size, but for the gigE chips, 2247 * it is 13 bits (since the max RX frame length is 16K). 2248 * Unfortunately, all 32 bits in the status word 2249 * were already used, so to make room for the extra 2250 * length bit, RealTek took out the 'frame alignment 2251 * error' bit and shifted the other status bits 2252 * over one slot. The OWN, EOR, FS and LS bits are 2253 * still in the same places. We have already extracted 2254 * the frame length and checked the OWN bit, so rather 2255 * than using an alternate bit mapping, we shift the 2256 * status bits one space to the right so we can evaluate 2257 * them using the 8169 status as though it was in the 2258 * same format as that of the 8139C+. 2259 */ 2260 if (sc->rl_type == RL_8169) 2261 rxstat >>= 1; 2262 2263 /* 2264 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 2265 * set, but if CRC is clear, it will still be a valid frame. 2266 */ 2267 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) { 2268 rxerr = 1; 2269 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 && 2270 total_len > 8191 && 2271 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT) 2272 rxerr = 0; 2273 if (rxerr != 0) { 2274 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2275 /* 2276 * If this is part of a multi-fragment packet, 2277 * discard all the pieces. 2278 */ 2279 if (sc->rl_head != NULL) { 2280 m_freem(sc->rl_head); 2281 sc->rl_head = sc->rl_tail = NULL; 2282 } 2283 re_discard_rxbuf(sc, i); 2284 continue; 2285 } 2286 } 2287 2288 /* 2289 * If allocating a replacement mbuf fails, 2290 * reload the current one. 2291 */ 2292 if (jumbo != 0) 2293 rxerr = re_jumbo_newbuf(sc, i); 2294 else 2295 rxerr = re_newbuf(sc, i); 2296 if (rxerr != 0) { 2297 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2298 if (sc->rl_head != NULL) { 2299 m_freem(sc->rl_head); 2300 sc->rl_head = sc->rl_tail = NULL; 2301 } 2302 re_discard_rxbuf(sc, i); 2303 continue; 2304 } 2305 2306 if (sc->rl_head != NULL) { 2307 if (jumbo != 0) 2308 m->m_len = total_len; 2309 else { 2310 m->m_len = total_len % RE_RX_DESC_BUFLEN; 2311 if (m->m_len == 0) 2312 m->m_len = RE_RX_DESC_BUFLEN; 2313 } 2314 /* 2315 * Special case: if there's 4 bytes or less 2316 * in this buffer, the mbuf can be discarded: 2317 * the last 4 bytes is the CRC, which we don't 2318 * care about anyway. 2319 */ 2320 if (m->m_len <= ETHER_CRC_LEN) { 2321 sc->rl_tail->m_len -= 2322 (ETHER_CRC_LEN - m->m_len); 2323 m_freem(m); 2324 } else { 2325 m->m_len -= ETHER_CRC_LEN; 2326 m->m_flags &= ~M_PKTHDR; 2327 sc->rl_tail->m_next = m; 2328 } 2329 m = sc->rl_head; 2330 sc->rl_head = sc->rl_tail = NULL; 2331 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2332 } else 2333 m->m_pkthdr.len = m->m_len = 2334 (total_len - ETHER_CRC_LEN); 2335 2336#ifdef RE_FIXUP_RX 2337 re_fixup_rx(m); 2338#endif 2339 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2340 m->m_pkthdr.rcvif = ifp; 2341 2342 /* Do RX checksumming if enabled */ 2343 2344 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 2345 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2346 /* Check IP header checksum */ 2347 if (rxstat & RL_RDESC_STAT_PROTOID) 2348 m->m_pkthdr.csum_flags |= 2349 CSUM_IP_CHECKED; 2350 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 2351 m->m_pkthdr.csum_flags |= 2352 CSUM_IP_VALID; 2353 2354 /* Check TCP/UDP checksum */ 2355 if ((RL_TCPPKT(rxstat) && 2356 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2357 (RL_UDPPKT(rxstat) && 2358 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2359 m->m_pkthdr.csum_flags |= 2360 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2361 m->m_pkthdr.csum_data = 0xffff; 2362 } 2363 } else { 2364 /* 2365 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 2366 */ 2367 if ((rxstat & RL_RDESC_STAT_PROTOID) && 2368 (rxvlan & RL_RDESC_IPV4)) 2369 m->m_pkthdr.csum_flags |= 2370 CSUM_IP_CHECKED; 2371 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 2372 (rxvlan & RL_RDESC_IPV4)) 2373 m->m_pkthdr.csum_flags |= 2374 CSUM_IP_VALID; 2375 if (((rxstat & RL_RDESC_STAT_TCP) && 2376 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2377 ((rxstat & RL_RDESC_STAT_UDP) && 2378 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2379 m->m_pkthdr.csum_flags |= 2380 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2381 m->m_pkthdr.csum_data = 0xffff; 2382 } 2383 } 2384 } 2385 maxpkt--; 2386 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 2387 m->m_pkthdr.ether_vtag = 2388 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 2389 m->m_flags |= M_VLANTAG; 2390 } 2391 RL_UNLOCK(sc); 2392 if_input(ifp, m); 2393 RL_LOCK(sc); 2394 rx_npkts++; 2395 } 2396 2397 /* Flush the RX DMA ring */ 2398 2399 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2400 sc->rl_ldata.rl_rx_list_map, 2401 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2402 2403 sc->rl_ldata.rl_rx_prodidx = i; 2404 2405 if (rx_npktsp != NULL) 2406 *rx_npktsp = rx_npkts; 2407 if (maxpkt) 2408 return (EAGAIN); 2409 2410 return (0); 2411} 2412 2413static void 2414re_txeof(struct rl_softc *sc) 2415{ 2416 if_t ifp; 2417 struct rl_txdesc *txd; 2418 u_int32_t txstat; 2419 int cons; 2420 2421 cons = sc->rl_ldata.rl_tx_considx; 2422 if (cons == sc->rl_ldata.rl_tx_prodidx) 2423 return; 2424 2425 ifp = sc->rl_ifp; 2426#ifdef DEV_NETMAP 2427 if (netmap_tx_irq(ifp, 0)) 2428 return; 2429#endif /* DEV_NETMAP */ 2430 /* Invalidate the TX descriptor list */ 2431 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2432 sc->rl_ldata.rl_tx_list_map, 2433 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2434 2435 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2436 cons = RL_TX_DESC_NXT(sc, cons)) { 2437 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2438 if (txstat & RL_TDESC_STAT_OWN) 2439 break; 2440 /* 2441 * We only stash mbufs in the last descriptor 2442 * in a fragment chain, which also happens to 2443 * be the only place where the TX status bits 2444 * are valid. 2445 */ 2446 if (txstat & RL_TDESC_CMD_EOF) { 2447 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2448 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2449 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2450 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2451 txd->tx_dmamap); 2452 KASSERT(txd->tx_m != NULL, 2453 ("%s: freeing NULL mbufs!", __func__)); 2454 m_freem(txd->tx_m); 2455 txd->tx_m = NULL; 2456 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2457 RL_TDESC_STAT_COLCNT)) 2458 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 2459 if (txstat & RL_TDESC_STAT_TXERRSUM) 2460 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2461 else 2462 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2463 } 2464 sc->rl_ldata.rl_tx_free++; 2465 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2466 } 2467 sc->rl_ldata.rl_tx_considx = cons; 2468 2469 /* No changes made to the TX ring, so no flush needed */ 2470 2471 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2472#ifdef RE_TX_MODERATION 2473 /* 2474 * If not all descriptors have been reaped yet, reload 2475 * the timer so that we will eventually get another 2476 * interrupt that will cause us to re-enter this routine. 2477 * This is done in case the transmitter has gone idle. 2478 */ 2479 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2480#endif 2481 } else 2482 sc->rl_watchdog_timer = 0; 2483} 2484 2485static void 2486re_tick(void *xsc) 2487{ 2488 struct rl_softc *sc; 2489 struct mii_data *mii; 2490 2491 sc = xsc; 2492 2493 RL_LOCK_ASSERT(sc); 2494 2495 mii = device_get_softc(sc->rl_miibus); 2496 mii_tick(mii); 2497 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2498 re_miibus_statchg(sc->rl_dev); 2499 /* 2500 * Reclaim transmitted frames here. Technically it is not 2501 * necessary to do here but it ensures periodic reclamation 2502 * regardless of Tx completion interrupt which seems to be 2503 * lost on PCIe based controllers under certain situations. 2504 */ 2505 re_txeof(sc); 2506 re_watchdog(sc); 2507 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2508} 2509 2510#ifdef DEVICE_POLLING 2511static int 2512re_poll(if_t ifp, enum poll_cmd cmd, int count) 2513{ 2514 struct rl_softc *sc = if_getsoftc(ifp); 2515 int rx_npkts = 0; 2516 2517 RL_LOCK(sc); 2518 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2519 rx_npkts = re_poll_locked(ifp, cmd, count); 2520 RL_UNLOCK(sc); 2521 return (rx_npkts); 2522} 2523 2524static int 2525re_poll_locked(if_t ifp, enum poll_cmd cmd, int count) 2526{ 2527 struct rl_softc *sc = if_getsoftc(ifp); 2528 int rx_npkts; 2529 2530 RL_LOCK_ASSERT(sc); 2531 2532 sc->rxcycles = count; 2533 re_rxeof(sc, &rx_npkts); 2534 re_txeof(sc); 2535 2536 if (!if_sendq_empty(ifp)) 2537 re_start_locked(ifp); 2538 2539 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2540 u_int16_t status; 2541 2542 status = CSR_READ_2(sc, RL_ISR); 2543 if (status == 0xffff) 2544 return (rx_npkts); 2545 if (status) 2546 CSR_WRITE_2(sc, RL_ISR, status); 2547 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2548 (sc->rl_flags & RL_FLAG_PCIE)) 2549 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2550 2551 /* 2552 * XXX check behaviour on receiver stalls. 2553 */ 2554 2555 if (status & RL_ISR_SYSTEM_ERR) { 2556 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2557 re_init_locked(sc); 2558 } 2559 } 2560 return (rx_npkts); 2561} 2562#endif /* DEVICE_POLLING */ 2563 2564static int 2565re_intr(void *arg) 2566{ 2567 struct rl_softc *sc; 2568 uint16_t status; 2569 2570 sc = arg; 2571 2572 status = CSR_READ_2(sc, RL_ISR); 2573 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2574 return (FILTER_STRAY); 2575 CSR_WRITE_2(sc, RL_IMR, 0); 2576 2577 taskqueue_enqueue(taskqueue_fast, &sc->rl_inttask); 2578 2579 return (FILTER_HANDLED); 2580} 2581 2582static void 2583re_int_task(void *arg, int npending) 2584{ 2585 struct rl_softc *sc; 2586 if_t ifp; 2587 u_int16_t status; 2588 int rval = 0; 2589 2590 sc = arg; 2591 ifp = sc->rl_ifp; 2592 2593 RL_LOCK(sc); 2594 2595 status = CSR_READ_2(sc, RL_ISR); 2596 CSR_WRITE_2(sc, RL_ISR, status); 2597 2598 if (sc->suspended || 2599 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 2600 RL_UNLOCK(sc); 2601 return; 2602 } 2603 2604#ifdef DEVICE_POLLING 2605 if (if_getcapenable(ifp) & IFCAP_POLLING) { 2606 RL_UNLOCK(sc); 2607 return; 2608 } 2609#endif 2610 2611 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2612 rval = re_rxeof(sc, NULL); 2613 2614 /* 2615 * Some chips will ignore a second TX request issued 2616 * while an existing transmission is in progress. If 2617 * the transmitter goes idle but there are still 2618 * packets waiting to be sent, we need to restart the 2619 * channel here to flush them out. This only seems to 2620 * be required with the PCIe devices. 2621 */ 2622 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2623 (sc->rl_flags & RL_FLAG_PCIE)) 2624 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2625 if (status & ( 2626#ifdef RE_TX_MODERATION 2627 RL_ISR_TIMEOUT_EXPIRED| 2628#else 2629 RL_ISR_TX_OK| 2630#endif 2631 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2632 re_txeof(sc); 2633 2634 if (status & RL_ISR_SYSTEM_ERR) { 2635 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2636 re_init_locked(sc); 2637 } 2638 2639 if (!if_sendq_empty(ifp)) 2640 re_start_locked(ifp); 2641 2642 RL_UNLOCK(sc); 2643 2644 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2645 taskqueue_enqueue(taskqueue_fast, &sc->rl_inttask); 2646 return; 2647 } 2648 2649 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2650} 2651 2652static void 2653re_intr_msi(void *xsc) 2654{ 2655 struct rl_softc *sc; 2656 if_t ifp; 2657 uint16_t intrs, status; 2658 2659 sc = xsc; 2660 RL_LOCK(sc); 2661 2662 ifp = sc->rl_ifp; 2663#ifdef DEVICE_POLLING 2664 if (if_getcapenable(ifp) & IFCAP_POLLING) { 2665 RL_UNLOCK(sc); 2666 return; 2667 } 2668#endif 2669 /* Disable interrupts. */ 2670 CSR_WRITE_2(sc, RL_IMR, 0); 2671 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 2672 RL_UNLOCK(sc); 2673 return; 2674 } 2675 2676 intrs = RL_INTRS_CPLUS; 2677 status = CSR_READ_2(sc, RL_ISR); 2678 CSR_WRITE_2(sc, RL_ISR, status); 2679 if (sc->rl_int_rx_act > 0) { 2680 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2681 RL_ISR_RX_OVERRUN); 2682 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2683 RL_ISR_RX_OVERRUN); 2684 } 2685 2686 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR | 2687 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) { 2688 re_rxeof(sc, NULL); 2689 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2690 if (sc->rl_int_rx_mod != 0 && 2691 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR | 2692 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) { 2693 /* Rearm one-shot timer. */ 2694 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2695 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | 2696 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN); 2697 sc->rl_int_rx_act = 1; 2698 } else { 2699 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR | 2700 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN; 2701 sc->rl_int_rx_act = 0; 2702 } 2703 } 2704 } 2705 2706 /* 2707 * Some chips will ignore a second TX request issued 2708 * while an existing transmission is in progress. If 2709 * the transmitter goes idle but there are still 2710 * packets waiting to be sent, we need to restart the 2711 * channel here to flush them out. This only seems to 2712 * be required with the PCIe devices. 2713 */ 2714 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2715 (sc->rl_flags & RL_FLAG_PCIE)) 2716 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2717 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL)) 2718 re_txeof(sc); 2719 2720 if (status & RL_ISR_SYSTEM_ERR) { 2721 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2722 re_init_locked(sc); 2723 } 2724 2725 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2726 if (!if_sendq_empty(ifp)) 2727 re_start_locked(ifp); 2728 CSR_WRITE_2(sc, RL_IMR, intrs); 2729 } 2730 RL_UNLOCK(sc); 2731} 2732 2733static int 2734re_encap(struct rl_softc *sc, struct mbuf **m_head) 2735{ 2736 struct rl_txdesc *txd, *txd_last; 2737 bus_dma_segment_t segs[RL_NTXSEGS]; 2738 bus_dmamap_t map; 2739 struct mbuf *m_new; 2740 struct rl_desc *desc; 2741 int nsegs, prod; 2742 int i, error, ei, si; 2743 int padlen; 2744 uint32_t cmdstat, csum_flags, vlanctl; 2745 2746 RL_LOCK_ASSERT(sc); 2747 M_ASSERTPKTHDR((*m_head)); 2748 2749 /* 2750 * With some of the RealTek chips, using the checksum offload 2751 * support in conjunction with the autopadding feature results 2752 * in the transmission of corrupt frames. For example, if we 2753 * need to send a really small IP fragment that's less than 60 2754 * bytes in size, and IP header checksumming is enabled, the 2755 * resulting ethernet frame that appears on the wire will 2756 * have garbled payload. To work around this, if TX IP checksum 2757 * offload is enabled, we always manually pad short frames out 2758 * to the minimum ethernet frame size. 2759 */ 2760 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2761 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2762 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2763 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2764 if (M_WRITABLE(*m_head) == 0) { 2765 /* Get a writable copy. */ 2766 m_new = m_dup(*m_head, M_NOWAIT); 2767 m_freem(*m_head); 2768 if (m_new == NULL) { 2769 *m_head = NULL; 2770 return (ENOBUFS); 2771 } 2772 *m_head = m_new; 2773 } 2774 if ((*m_head)->m_next != NULL || 2775 M_TRAILINGSPACE(*m_head) < padlen) { 2776 m_new = m_defrag(*m_head, M_NOWAIT); 2777 if (m_new == NULL) { 2778 m_freem(*m_head); 2779 *m_head = NULL; 2780 return (ENOBUFS); 2781 } 2782 } else 2783 m_new = *m_head; 2784 2785 /* 2786 * Manually pad short frames, and zero the pad space 2787 * to avoid leaking data. 2788 */ 2789 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2790 m_new->m_pkthdr.len += padlen; 2791 m_new->m_len = m_new->m_pkthdr.len; 2792 *m_head = m_new; 2793 } 2794 2795 prod = sc->rl_ldata.rl_tx_prodidx; 2796 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2797 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2798 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2799 if (error == EFBIG) { 2800 m_new = m_collapse(*m_head, M_NOWAIT, RL_NTXSEGS); 2801 if (m_new == NULL) { 2802 m_freem(*m_head); 2803 *m_head = NULL; 2804 return (ENOBUFS); 2805 } 2806 *m_head = m_new; 2807 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2808 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2809 if (error != 0) { 2810 m_freem(*m_head); 2811 *m_head = NULL; 2812 return (error); 2813 } 2814 } else if (error != 0) 2815 return (error); 2816 if (nsegs == 0) { 2817 m_freem(*m_head); 2818 *m_head = NULL; 2819 return (EIO); 2820 } 2821 2822 /* Check for number of available descriptors. */ 2823 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2824 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2825 return (ENOBUFS); 2826 } 2827 2828 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2829 BUS_DMASYNC_PREWRITE); 2830 2831 /* 2832 * Set up checksum offload. Note: checksum offload bits must 2833 * appear in all descriptors of a multi-descriptor transmit 2834 * attempt. This is according to testing done with an 8169 2835 * chip. This is a requirement. 2836 */ 2837 vlanctl = 0; 2838 csum_flags = 0; 2839 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2840 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) { 2841 csum_flags |= RL_TDESC_CMD_LGSEND; 2842 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2843 RL_TDESC_CMD_MSSVALV2_SHIFT); 2844 } else { 2845 csum_flags |= RL_TDESC_CMD_LGSEND | 2846 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2847 RL_TDESC_CMD_MSSVAL_SHIFT); 2848 } 2849 } else { 2850 /* 2851 * Unconditionally enable IP checksum if TCP or UDP 2852 * checksum is required. Otherwise, TCP/UDP checksum 2853 * doesn't make effects. 2854 */ 2855 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2856 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2857 csum_flags |= RL_TDESC_CMD_IPCSUM; 2858 if (((*m_head)->m_pkthdr.csum_flags & 2859 CSUM_TCP) != 0) 2860 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2861 if (((*m_head)->m_pkthdr.csum_flags & 2862 CSUM_UDP) != 0) 2863 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2864 } else { 2865 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2866 if (((*m_head)->m_pkthdr.csum_flags & 2867 CSUM_TCP) != 0) 2868 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2869 if (((*m_head)->m_pkthdr.csum_flags & 2870 CSUM_UDP) != 0) 2871 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2872 } 2873 } 2874 } 2875 2876 /* 2877 * Set up hardware VLAN tagging. Note: vlan tag info must 2878 * appear in all descriptors of a multi-descriptor 2879 * transmission attempt. 2880 */ 2881 if ((*m_head)->m_flags & M_VLANTAG) 2882 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2883 RL_TDESC_VLANCTL_TAG; 2884 2885 si = prod; 2886 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2887 desc = &sc->rl_ldata.rl_tx_list[prod]; 2888 desc->rl_vlanctl = htole32(vlanctl); 2889 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2890 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2891 cmdstat = segs[i].ds_len; 2892 if (i != 0) 2893 cmdstat |= RL_TDESC_CMD_OWN; 2894 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2895 cmdstat |= RL_TDESC_CMD_EOR; 2896 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2897 sc->rl_ldata.rl_tx_free--; 2898 } 2899 /* Update producer index. */ 2900 sc->rl_ldata.rl_tx_prodidx = prod; 2901 2902 /* Set EOF on the last descriptor. */ 2903 ei = RL_TX_DESC_PRV(sc, prod); 2904 desc = &sc->rl_ldata.rl_tx_list[ei]; 2905 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2906 2907 desc = &sc->rl_ldata.rl_tx_list[si]; 2908 /* Set SOF and transfer ownership of packet to the chip. */ 2909 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2910 2911 /* 2912 * Insure that the map for this transmission 2913 * is placed at the array index of the last descriptor 2914 * in this chain. (Swap last and first dmamaps.) 2915 */ 2916 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2917 map = txd->tx_dmamap; 2918 txd->tx_dmamap = txd_last->tx_dmamap; 2919 txd_last->tx_dmamap = map; 2920 txd_last->tx_m = *m_head; 2921 2922 return (0); 2923} 2924 2925static void 2926re_start(if_t ifp) 2927{ 2928 struct rl_softc *sc; 2929 2930 sc = if_getsoftc(ifp); 2931 RL_LOCK(sc); 2932 re_start_locked(ifp); 2933 RL_UNLOCK(sc); 2934} 2935 2936/* 2937 * Main transmit routine for C+ and gigE NICs. 2938 */ 2939static void 2940re_start_locked(if_t ifp) 2941{ 2942 struct rl_softc *sc; 2943 struct mbuf *m_head; 2944 int queued; 2945 2946 sc = if_getsoftc(ifp); 2947 2948#ifdef DEV_NETMAP 2949 /* XXX is this necessary ? */ 2950 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2951 struct netmap_kring *kring = NA(ifp)->tx_rings[0]; 2952 if (sc->rl_ldata.rl_tx_prodidx != kring->nr_hwcur) { 2953 /* kick the tx unit */ 2954 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2955#ifdef RE_TX_MODERATION 2956 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2957#endif 2958 sc->rl_watchdog_timer = 5; 2959 } 2960 return; 2961 } 2962#endif /* DEV_NETMAP */ 2963 2964 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2965 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 2966 return; 2967 2968 for (queued = 0; !if_sendq_empty(ifp) && 2969 sc->rl_ldata.rl_tx_free > 1;) { 2970 m_head = if_dequeue(ifp); 2971 if (m_head == NULL) 2972 break; 2973 2974 if (re_encap(sc, &m_head) != 0) { 2975 if (m_head == NULL) 2976 break; 2977 if_sendq_prepend(ifp, m_head); 2978 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2979 break; 2980 } 2981 2982 /* 2983 * If there's a BPF listener, bounce a copy of this frame 2984 * to him. 2985 */ 2986 ETHER_BPF_MTAP(ifp, m_head); 2987 2988 queued++; 2989 } 2990 2991 if (queued == 0) { 2992#ifdef RE_TX_MODERATION 2993 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2994 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2995#endif 2996 return; 2997 } 2998 2999 re_start_tx(sc); 3000} 3001 3002static void 3003re_start_tx(struct rl_softc *sc) 3004{ 3005 3006 /* Flush the TX descriptors */ 3007 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 3008 sc->rl_ldata.rl_tx_list_map, 3009 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 3010 3011 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 3012 3013#ifdef RE_TX_MODERATION 3014 /* 3015 * Use the countdown timer for interrupt moderation. 3016 * 'TX done' interrupts are disabled. Instead, we reset the 3017 * countdown timer, which will begin counting until it hits 3018 * the value in the TIMERINT register, and then trigger an 3019 * interrupt. Each time we write to the TIMERCNT register, 3020 * the timer count is reset to 0. 3021 */ 3022 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 3023#endif 3024 3025 /* 3026 * Set a timeout in case the chip goes out to lunch. 3027 */ 3028 sc->rl_watchdog_timer = 5; 3029} 3030 3031static void 3032re_set_jumbo(struct rl_softc *sc, int jumbo) 3033{ 3034 3035 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) { 3036 pci_set_max_read_req(sc->rl_dev, 4096); 3037 return; 3038 } 3039 3040 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3041 if (jumbo != 0) { 3042 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) | 3043 RL_CFG3_JUMBO_EN0); 3044 switch (sc->rl_hwrev->rl_rev) { 3045 case RL_HWREV_8168DP: 3046 break; 3047 case RL_HWREV_8168E: 3048 CSR_WRITE_1(sc, sc->rl_cfg4, 3049 CSR_READ_1(sc, sc->rl_cfg4) | 0x01); 3050 break; 3051 default: 3052 CSR_WRITE_1(sc, sc->rl_cfg4, 3053 CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1); 3054 } 3055 } else { 3056 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) & 3057 ~RL_CFG3_JUMBO_EN0); 3058 switch (sc->rl_hwrev->rl_rev) { 3059 case RL_HWREV_8168DP: 3060 break; 3061 case RL_HWREV_8168E: 3062 CSR_WRITE_1(sc, sc->rl_cfg4, 3063 CSR_READ_1(sc, sc->rl_cfg4) & ~0x01); 3064 break; 3065 default: 3066 CSR_WRITE_1(sc, sc->rl_cfg4, 3067 CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1); 3068 } 3069 } 3070 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3071 3072 switch (sc->rl_hwrev->rl_rev) { 3073 case RL_HWREV_8168DP: 3074 pci_set_max_read_req(sc->rl_dev, 4096); 3075 break; 3076 default: 3077 if (jumbo != 0) 3078 pci_set_max_read_req(sc->rl_dev, 512); 3079 else 3080 pci_set_max_read_req(sc->rl_dev, 4096); 3081 } 3082} 3083 3084static void 3085re_init(void *xsc) 3086{ 3087 struct rl_softc *sc = xsc; 3088 3089 RL_LOCK(sc); 3090 re_init_locked(sc); 3091 RL_UNLOCK(sc); 3092} 3093 3094static void 3095re_init_locked(struct rl_softc *sc) 3096{ 3097 if_t ifp = sc->rl_ifp; 3098 struct mii_data *mii; 3099 uint32_t reg; 3100 uint16_t cfg; 3101 uint32_t idr[2]; 3102 3103 RL_LOCK_ASSERT(sc); 3104 3105 mii = device_get_softc(sc->rl_miibus); 3106 3107 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3108 return; 3109 3110 /* 3111 * Cancel pending I/O and free all RX/TX buffers. 3112 */ 3113 re_stop(sc); 3114 3115 /* Put controller into known state. */ 3116 re_reset(sc); 3117 3118 /* 3119 * For C+ mode, initialize the RX descriptors and mbufs. 3120 */ 3121 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3122 if (if_getmtu(ifp) > RL_MTU) { 3123 if (re_jrx_list_init(sc) != 0) { 3124 device_printf(sc->rl_dev, 3125 "no memory for jumbo RX buffers\n"); 3126 re_stop(sc); 3127 return; 3128 } 3129 /* Disable checksum offloading for jumbo frames. */ 3130 if_setcapenablebit(ifp, 0, (IFCAP_HWCSUM | IFCAP_TSO4)); 3131 if_sethwassistbits(ifp, 0, (RE_CSUM_FEATURES | CSUM_TSO)); 3132 } else { 3133 if (re_rx_list_init(sc) != 0) { 3134 device_printf(sc->rl_dev, 3135 "no memory for RX buffers\n"); 3136 re_stop(sc); 3137 return; 3138 } 3139 } 3140 re_set_jumbo(sc, if_getmtu(ifp) > RL_MTU); 3141 } else { 3142 if (re_rx_list_init(sc) != 0) { 3143 device_printf(sc->rl_dev, "no memory for RX buffers\n"); 3144 re_stop(sc); 3145 return; 3146 } 3147 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3148 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) { 3149 if (if_getmtu(ifp) > RL_MTU) 3150 pci_set_max_read_req(sc->rl_dev, 512); 3151 else 3152 pci_set_max_read_req(sc->rl_dev, 4096); 3153 } 3154 } 3155 re_tx_list_init(sc); 3156 3157 /* 3158 * Enable C+ RX and TX mode, as well as VLAN stripping and 3159 * RX checksum offload. We must configure the C+ register 3160 * before all others. 3161 */ 3162 cfg = RL_CPLUSCMD_PCI_MRW; 3163 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 3164 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 3165 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 3166 cfg |= RL_CPLUSCMD_VLANSTRIP; 3167 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 3168 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 3169 /* XXX magic. */ 3170 cfg |= 0x0001; 3171 } else 3172 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 3173 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 3174 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC || 3175 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) { 3176 reg = 0x000fff00; 3177 if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0) 3178 reg |= 0x000000ff; 3179 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) 3180 reg |= 0x00f00000; 3181 CSR_WRITE_4(sc, 0x7c, reg); 3182 /* Disable interrupt mitigation. */ 3183 CSR_WRITE_2(sc, 0xe2, 0); 3184 } 3185 /* 3186 * Disable TSO if interface MTU size is greater than MSS 3187 * allowed in controller. 3188 */ 3189 if (if_getmtu(ifp) > RL_TSO_MTU && (if_getcapenable(ifp) & IFCAP_TSO4) != 0) { 3190 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 3191 if_sethwassistbits(ifp, 0, CSUM_TSO); 3192 } 3193 3194 /* 3195 * Init our MAC address. Even though the chipset 3196 * documentation doesn't mention it, we need to enter "Config 3197 * register write enable" mode to modify the ID registers. 3198 */ 3199 /* Copy MAC address on stack to align. */ 3200 bzero(idr, sizeof(idr)); 3201 bcopy(if_getlladdr(ifp), idr, ETHER_ADDR_LEN); 3202 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3203 CSR_WRITE_4(sc, RL_IDR0, htole32(idr[0])); 3204 CSR_WRITE_4(sc, RL_IDR4, htole32(idr[1])); 3205 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3206 3207 /* 3208 * Load the addresses of the RX and TX lists into the chip. 3209 */ 3210 3211 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 3212 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 3213 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 3214 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 3215 3216 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 3217 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 3218 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 3219 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 3220 3221 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) { 3222 /* Disable RXDV gate. */ 3223 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) & 3224 ~0x00080000); 3225 } 3226 3227 /* 3228 * Enable transmit and receive for pre-RTL8168G controllers. 3229 * RX/TX MACs should be enabled before RX/TX configuration. 3230 */ 3231 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) == 0) 3232 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB); 3233 3234 /* 3235 * Set the initial TX configuration. 3236 */ 3237 if (sc->rl_testmode) { 3238 if (sc->rl_type == RL_8169) 3239 CSR_WRITE_4(sc, RL_TXCFG, 3240 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 3241 else 3242 CSR_WRITE_4(sc, RL_TXCFG, 3243 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 3244 } else 3245 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 3246 3247 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 3248 3249 /* 3250 * Set the initial RX configuration. 3251 */ 3252 re_set_rxmode(sc); 3253 3254 /* Configure interrupt moderation. */ 3255 if (sc->rl_type == RL_8169) { 3256 /* Magic from vendor. */ 3257 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100); 3258 } 3259 3260 /* 3261 * Enable transmit and receive for RTL8168G and later controllers. 3262 * RX/TX MACs should be enabled after RX/TX configuration. 3263 */ 3264 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) 3265 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB); 3266 3267#ifdef DEVICE_POLLING 3268 /* 3269 * Disable interrupts if we are polling. 3270 */ 3271 if (if_getcapenable(ifp) & IFCAP_POLLING) 3272 CSR_WRITE_2(sc, RL_IMR, 0); 3273 else /* otherwise ... */ 3274#endif 3275 3276 /* 3277 * Enable interrupts. 3278 */ 3279 if (sc->rl_testmode) 3280 CSR_WRITE_2(sc, RL_IMR, 0); 3281 else 3282 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3283 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 3284 3285 /* Set initial TX threshold */ 3286 sc->rl_txthresh = RL_TX_THRESH_INIT; 3287 3288 /* Start RX/TX process. */ 3289 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 3290 3291 /* 3292 * Initialize the timer interrupt register so that 3293 * a timer interrupt will be generated once the timer 3294 * reaches a certain number of ticks. The timer is 3295 * reloaded on each transmit. 3296 */ 3297#ifdef RE_TX_MODERATION 3298 /* 3299 * Use timer interrupt register to moderate TX interrupt 3300 * moderation, which dramatically improves TX frame rate. 3301 */ 3302 if (sc->rl_type == RL_8169) 3303 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 3304 else 3305 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 3306#else 3307 /* 3308 * Use timer interrupt register to moderate RX interrupt 3309 * moderation. 3310 */ 3311 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 3312 intr_filter == 0) { 3313 if (sc->rl_type == RL_8169) 3314 CSR_WRITE_4(sc, RL_TIMERINT_8169, 3315 RL_USECS(sc->rl_int_rx_mod)); 3316 } else { 3317 if (sc->rl_type == RL_8169) 3318 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0)); 3319 } 3320#endif 3321 3322 /* 3323 * For 8169 gigE NICs, set the max allowed RX packet 3324 * size so we can receive jumbo frames. 3325 */ 3326 if (sc->rl_type == RL_8169) { 3327 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3328 /* 3329 * For controllers that use new jumbo frame scheme, 3330 * set maximum size of jumbo frame depending on 3331 * controller revisions. 3332 */ 3333 if (if_getmtu(ifp) > RL_MTU) 3334 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3335 sc->rl_hwrev->rl_max_mtu + 3336 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN + 3337 ETHER_CRC_LEN); 3338 else 3339 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3340 RE_RX_DESC_BUFLEN); 3341 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3342 sc->rl_hwrev->rl_max_mtu == RL_MTU) { 3343 /* RTL810x has no jumbo frame support. */ 3344 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN); 3345 } else 3346 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 3347 } 3348 3349 if (sc->rl_testmode) 3350 return; 3351 3352 CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) | 3353 RL_CFG1_DRVLOAD); 3354 3355 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 3356 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 3357 3358 sc->rl_flags &= ~RL_FLAG_LINK; 3359 mii_mediachg(mii); 3360 3361 sc->rl_watchdog_timer = 0; 3362 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 3363 3364#ifdef DEV_NETMAP 3365 netmap_enable_all_rings(ifp); 3366#endif /* DEV_NETMAP */ 3367} 3368 3369/* 3370 * Set media options. 3371 */ 3372static int 3373re_ifmedia_upd(if_t ifp) 3374{ 3375 struct rl_softc *sc; 3376 struct mii_data *mii; 3377 int error; 3378 3379 sc = if_getsoftc(ifp); 3380 mii = device_get_softc(sc->rl_miibus); 3381 RL_LOCK(sc); 3382 error = mii_mediachg(mii); 3383 RL_UNLOCK(sc); 3384 3385 return (error); 3386} 3387 3388/* 3389 * Report current media status. 3390 */ 3391static void 3392re_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 3393{ 3394 struct rl_softc *sc; 3395 struct mii_data *mii; 3396 3397 sc = if_getsoftc(ifp); 3398 mii = device_get_softc(sc->rl_miibus); 3399 3400 RL_LOCK(sc); 3401 mii_pollstat(mii); 3402 ifmr->ifm_active = mii->mii_media_active; 3403 ifmr->ifm_status = mii->mii_media_status; 3404 RL_UNLOCK(sc); 3405} 3406 3407static int 3408re_ioctl(if_t ifp, u_long command, caddr_t data) 3409{ 3410 struct rl_softc *sc = if_getsoftc(ifp); 3411 struct ifreq *ifr = (struct ifreq *) data; 3412 struct mii_data *mii; 3413 int error = 0; 3414 3415 switch (command) { 3416 case SIOCSIFMTU: 3417 if (ifr->ifr_mtu < ETHERMIN || 3418 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu || 3419 ((sc->rl_flags & RL_FLAG_FASTETHER) != 0 && 3420 ifr->ifr_mtu > RL_MTU)) { 3421 error = EINVAL; 3422 break; 3423 } 3424 RL_LOCK(sc); 3425 if (if_getmtu(ifp) != ifr->ifr_mtu) { 3426 if_setmtu(ifp, ifr->ifr_mtu); 3427 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3428 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 3429 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3430 re_init_locked(sc); 3431 } 3432 if (if_getmtu(ifp) > RL_TSO_MTU && 3433 (if_getcapenable(ifp) & IFCAP_TSO4) != 0) { 3434 if_setcapenablebit(ifp, 0, 3435 IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 3436 if_sethwassistbits(ifp, 0, CSUM_TSO); 3437 } 3438 VLAN_CAPABILITIES(ifp); 3439 } 3440 RL_UNLOCK(sc); 3441 break; 3442 case SIOCSIFFLAGS: 3443 RL_LOCK(sc); 3444 if ((if_getflags(ifp) & IFF_UP) != 0) { 3445 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 3446 if (((if_getflags(ifp) ^ sc->rl_if_flags) 3447 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3448 re_set_rxmode(sc); 3449 } else 3450 re_init_locked(sc); 3451 } else { 3452 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3453 re_stop(sc); 3454 } 3455 sc->rl_if_flags = if_getflags(ifp); 3456 RL_UNLOCK(sc); 3457 break; 3458 case SIOCADDMULTI: 3459 case SIOCDELMULTI: 3460 RL_LOCK(sc); 3461 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3462 re_set_rxmode(sc); 3463 RL_UNLOCK(sc); 3464 break; 3465 case SIOCGIFMEDIA: 3466 case SIOCSIFMEDIA: 3467 mii = device_get_softc(sc->rl_miibus); 3468 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3469 break; 3470 case SIOCSIFCAP: 3471 { 3472 int mask, reinit; 3473 3474 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 3475 reinit = 0; 3476#ifdef DEVICE_POLLING 3477 if (mask & IFCAP_POLLING) { 3478 if (ifr->ifr_reqcap & IFCAP_POLLING) { 3479 error = ether_poll_register(re_poll, ifp); 3480 if (error) 3481 return (error); 3482 RL_LOCK(sc); 3483 /* Disable interrupts */ 3484 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3485 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 3486 RL_UNLOCK(sc); 3487 } else { 3488 error = ether_poll_deregister(ifp); 3489 /* Enable interrupts. */ 3490 RL_LOCK(sc); 3491 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3492 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 3493 RL_UNLOCK(sc); 3494 } 3495 } 3496#endif /* DEVICE_POLLING */ 3497 RL_LOCK(sc); 3498 if ((mask & IFCAP_TXCSUM) != 0 && 3499 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 3500 if_togglecapenable(ifp, IFCAP_TXCSUM); 3501 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 3502 if_sethwassistbits(ifp, RE_CSUM_FEATURES, 0); 3503 else 3504 if_sethwassistbits(ifp, 0, RE_CSUM_FEATURES); 3505 reinit = 1; 3506 } 3507 if ((mask & IFCAP_RXCSUM) != 0 && 3508 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) { 3509 if_togglecapenable(ifp, IFCAP_RXCSUM); 3510 reinit = 1; 3511 } 3512 if ((mask & IFCAP_TSO4) != 0 && 3513 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 3514 if_togglecapenable(ifp, IFCAP_TSO4); 3515 if ((IFCAP_TSO4 & if_getcapenable(ifp)) != 0) 3516 if_sethwassistbits(ifp, CSUM_TSO, 0); 3517 else 3518 if_sethwassistbits(ifp, 0, CSUM_TSO); 3519 if (if_getmtu(ifp) > RL_TSO_MTU && 3520 (if_getcapenable(ifp) & IFCAP_TSO4) != 0) { 3521 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 3522 if_sethwassistbits(ifp, 0, CSUM_TSO); 3523 } 3524 } 3525 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3526 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 3527 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 3528 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3529 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 3530 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 3531 /* TSO over VLAN requires VLAN hardware tagging. */ 3532 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 3533 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO); 3534 reinit = 1; 3535 } 3536 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3537 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 | 3538 IFCAP_VLAN_HWTSO)) != 0) 3539 reinit = 1; 3540 if ((mask & IFCAP_WOL) != 0 && 3541 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) { 3542 if ((mask & IFCAP_WOL_UCAST) != 0) 3543 if_togglecapenable(ifp, IFCAP_WOL_UCAST); 3544 if ((mask & IFCAP_WOL_MCAST) != 0) 3545 if_togglecapenable(ifp, IFCAP_WOL_MCAST); 3546 if ((mask & IFCAP_WOL_MAGIC) != 0) 3547 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 3548 } 3549 if (reinit && if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3550 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3551 re_init_locked(sc); 3552 } 3553 RL_UNLOCK(sc); 3554 VLAN_CAPABILITIES(ifp); 3555 } 3556 break; 3557 default: 3558 error = ether_ioctl(ifp, command, data); 3559 break; 3560 } 3561 3562 return (error); 3563} 3564 3565static void 3566re_watchdog(struct rl_softc *sc) 3567{ 3568 if_t ifp; 3569 3570 RL_LOCK_ASSERT(sc); 3571 3572 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 3573 return; 3574 3575 ifp = sc->rl_ifp; 3576 re_txeof(sc); 3577 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 3578 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 3579 "-- recovering\n"); 3580 if (!if_sendq_empty(ifp)) 3581 re_start_locked(ifp); 3582 return; 3583 } 3584 3585 if_printf(ifp, "watchdog timeout\n"); 3586 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3587 3588 re_rxeof(sc, NULL); 3589 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3590 re_init_locked(sc); 3591 if (!if_sendq_empty(ifp)) 3592 re_start_locked(ifp); 3593} 3594 3595/* 3596 * Stop the adapter and free any mbufs allocated to the 3597 * RX and TX lists. 3598 */ 3599static void 3600re_stop(struct rl_softc *sc) 3601{ 3602 int i; 3603 if_t ifp; 3604 struct rl_txdesc *txd; 3605 struct rl_rxdesc *rxd; 3606 3607 RL_LOCK_ASSERT(sc); 3608 3609 ifp = sc->rl_ifp; 3610 3611 sc->rl_watchdog_timer = 0; 3612 callout_stop(&sc->rl_stat_callout); 3613 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 3614 3615#ifdef DEV_NETMAP 3616 netmap_disable_all_rings(ifp); 3617#endif /* DEV_NETMAP */ 3618 3619 /* 3620 * Disable accepting frames to put RX MAC into idle state. 3621 * Otherwise it's possible to get frames while stop command 3622 * execution is in progress and controller can DMA the frame 3623 * to already freed RX buffer during that period. 3624 */ 3625 CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) & 3626 ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI | 3627 RL_RXCFG_RX_BROAD)); 3628 3629 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) { 3630 /* Enable RXDV gate. */ 3631 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) | 3632 0x00080000); 3633 } 3634 3635 if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) { 3636 for (i = RL_TIMEOUT; i > 0; i--) { 3637 if ((CSR_READ_1(sc, sc->rl_txstart) & 3638 RL_TXSTART_START) == 0) 3639 break; 3640 DELAY(20); 3641 } 3642 if (i == 0) 3643 device_printf(sc->rl_dev, 3644 "stopping TX poll timed out!\n"); 3645 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3646 } else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) { 3647 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 3648 RL_CMD_RX_ENB); 3649 if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) { 3650 for (i = RL_TIMEOUT; i > 0; i--) { 3651 if ((CSR_READ_4(sc, RL_TXCFG) & 3652 RL_TXCFG_QUEUE_EMPTY) != 0) 3653 break; 3654 DELAY(100); 3655 } 3656 if (i == 0) 3657 device_printf(sc->rl_dev, 3658 "stopping TXQ timed out!\n"); 3659 } 3660 } else 3661 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3662 DELAY(1000); 3663 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3664 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 3665 3666 if (sc->rl_head != NULL) { 3667 m_freem(sc->rl_head); 3668 sc->rl_head = sc->rl_tail = NULL; 3669 } 3670 3671 /* Free the TX list buffers. */ 3672 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 3673 txd = &sc->rl_ldata.rl_tx_desc[i]; 3674 if (txd->tx_m != NULL) { 3675 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3676 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3677 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 3678 txd->tx_dmamap); 3679 m_freem(txd->tx_m); 3680 txd->tx_m = NULL; 3681 } 3682 } 3683 3684 /* Free the RX list buffers. */ 3685 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3686 rxd = &sc->rl_ldata.rl_rx_desc[i]; 3687 if (rxd->rx_m != NULL) { 3688 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 3689 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3690 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 3691 rxd->rx_dmamap); 3692 m_freem(rxd->rx_m); 3693 rxd->rx_m = NULL; 3694 } 3695 } 3696 3697 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3698 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3699 rxd = &sc->rl_ldata.rl_jrx_desc[i]; 3700 if (rxd->rx_m != NULL) { 3701 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, 3702 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3703 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, 3704 rxd->rx_dmamap); 3705 m_freem(rxd->rx_m); 3706 rxd->rx_m = NULL; 3707 } 3708 } 3709 } 3710} 3711 3712/* 3713 * Device suspend routine. Stop the interface and save some PCI 3714 * settings in case the BIOS doesn't restore them properly on 3715 * resume. 3716 */ 3717static int 3718re_suspend(device_t dev) 3719{ 3720 struct rl_softc *sc; 3721 3722 sc = device_get_softc(dev); 3723 3724 RL_LOCK(sc); 3725 re_stop(sc); 3726 re_setwol(sc); 3727 sc->suspended = 1; 3728 RL_UNLOCK(sc); 3729 3730 return (0); 3731} 3732 3733/* 3734 * Device resume routine. Restore some PCI settings in case the BIOS 3735 * doesn't, re-enable busmastering, and restart the interface if 3736 * appropriate. 3737 */ 3738static int 3739re_resume(device_t dev) 3740{ 3741 struct rl_softc *sc; 3742 if_t ifp; 3743 3744 sc = device_get_softc(dev); 3745 3746 RL_LOCK(sc); 3747 3748 ifp = sc->rl_ifp; 3749 /* Take controller out of sleep mode. */ 3750 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3751 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3752 CSR_WRITE_1(sc, RL_GPIO, 3753 CSR_READ_1(sc, RL_GPIO) | 0x01); 3754 } 3755 3756 /* 3757 * Clear WOL matching such that normal Rx filtering 3758 * wouldn't interfere with WOL patterns. 3759 */ 3760 re_clrwol(sc); 3761 3762 /* reinitialize interface if necessary */ 3763 if (if_getflags(ifp) & IFF_UP) 3764 re_init_locked(sc); 3765 3766 sc->suspended = 0; 3767 RL_UNLOCK(sc); 3768 3769 return (0); 3770} 3771 3772/* 3773 * Stop all chip I/O so that the kernel's probe routines don't 3774 * get confused by errant DMAs when rebooting. 3775 */ 3776static int 3777re_shutdown(device_t dev) 3778{ 3779 struct rl_softc *sc; 3780 3781 sc = device_get_softc(dev); 3782 3783 RL_LOCK(sc); 3784 re_stop(sc); 3785 /* 3786 * Mark interface as down since otherwise we will panic if 3787 * interrupt comes in later on, which can happen in some 3788 * cases. 3789 */ 3790 if_setflagbits(sc->rl_ifp, 0, IFF_UP); 3791 re_setwol(sc); 3792 RL_UNLOCK(sc); 3793 3794 return (0); 3795} 3796 3797static void 3798re_set_linkspeed(struct rl_softc *sc) 3799{ 3800 struct mii_softc *miisc; 3801 struct mii_data *mii; 3802 int aneg, i, phyno; 3803 3804 RL_LOCK_ASSERT(sc); 3805 3806 mii = device_get_softc(sc->rl_miibus); 3807 mii_pollstat(mii); 3808 aneg = 0; 3809 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 3810 (IFM_ACTIVE | IFM_AVALID)) { 3811 switch IFM_SUBTYPE(mii->mii_media_active) { 3812 case IFM_10_T: 3813 case IFM_100_TX: 3814 return; 3815 case IFM_1000_T: 3816 aneg++; 3817 break; 3818 default: 3819 break; 3820 } 3821 } 3822 miisc = LIST_FIRST(&mii->mii_phys); 3823 phyno = miisc->mii_phy; 3824 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3825 PHY_RESET(miisc); 3826 re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0); 3827 re_miibus_writereg(sc->rl_dev, phyno, 3828 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 3829 re_miibus_writereg(sc->rl_dev, phyno, 3830 MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 3831 DELAY(1000); 3832 if (aneg != 0) { 3833 /* 3834 * Poll link state until re(4) get a 10/100Mbps link. 3835 */ 3836 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 3837 mii_pollstat(mii); 3838 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 3839 == (IFM_ACTIVE | IFM_AVALID)) { 3840 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3841 case IFM_10_T: 3842 case IFM_100_TX: 3843 return; 3844 default: 3845 break; 3846 } 3847 } 3848 RL_UNLOCK(sc); 3849 pause("relnk", hz); 3850 RL_LOCK(sc); 3851 } 3852 if (i == MII_ANEGTICKS_GIGE) 3853 device_printf(sc->rl_dev, 3854 "establishing a link failed, WOL may not work!"); 3855 } 3856 /* 3857 * No link, force MAC to have 100Mbps, full-duplex link. 3858 * MAC does not require reprogramming on resolved speed/duplex, 3859 * so this is just for completeness. 3860 */ 3861 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 3862 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 3863} 3864 3865static void 3866re_setwol(struct rl_softc *sc) 3867{ 3868 if_t ifp; 3869 int pmc; 3870 uint16_t pmstat; 3871 uint8_t v; 3872 3873 RL_LOCK_ASSERT(sc); 3874 3875 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3876 return; 3877 3878 ifp = sc->rl_ifp; 3879 /* Put controller into sleep mode. */ 3880 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3881 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3882 CSR_WRITE_1(sc, RL_GPIO, 3883 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3884 } 3885 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 3886 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) { 3887 /* Disable RXDV gate. */ 3888 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) & 3889 ~0x00080000); 3890 } 3891 re_set_rxmode(sc); 3892 if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0) 3893 re_set_linkspeed(sc); 3894 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3895 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3896 } 3897 /* Enable config register write. */ 3898 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3899 3900 /* Enable PME. */ 3901 v = CSR_READ_1(sc, sc->rl_cfg1); 3902 v &= ~RL_CFG1_PME; 3903 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 3904 v |= RL_CFG1_PME; 3905 CSR_WRITE_1(sc, sc->rl_cfg1, v); 3906 3907 v = CSR_READ_1(sc, sc->rl_cfg3); 3908 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3909 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 3910 v |= RL_CFG3_WOL_MAGIC; 3911 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3912 3913 v = CSR_READ_1(sc, sc->rl_cfg5); 3914 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST | 3915 RL_CFG5_WOL_LANWAKE); 3916 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) != 0) 3917 v |= RL_CFG5_WOL_UCAST; 3918 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 3919 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3920 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 3921 v |= RL_CFG5_WOL_LANWAKE; 3922 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3923 3924 /* Config register write done. */ 3925 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3926 3927 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0 && 3928 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 3929 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80); 3930 /* 3931 * It seems that hardware resets its link speed to 100Mbps in 3932 * power down mode so switching to 100Mbps in driver is not 3933 * needed. 3934 */ 3935 3936 /* Request PME if WOL is requested. */ 3937 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3938 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3939 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 3940 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3941 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3942} 3943 3944static void 3945re_clrwol(struct rl_softc *sc) 3946{ 3947 int pmc; 3948 uint8_t v; 3949 3950 RL_LOCK_ASSERT(sc); 3951 3952 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3953 return; 3954 3955 /* Enable config register write. */ 3956 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3957 3958 v = CSR_READ_1(sc, sc->rl_cfg3); 3959 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3960 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3961 3962 /* Config register write done. */ 3963 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3964 3965 v = CSR_READ_1(sc, sc->rl_cfg5); 3966 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3967 v &= ~RL_CFG5_WOL_LANWAKE; 3968 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3969} 3970 3971static void 3972re_add_sysctls(struct rl_softc *sc) 3973{ 3974 struct sysctl_ctx_list *ctx; 3975 struct sysctl_oid_list *children; 3976 int error; 3977 3978 ctx = device_get_sysctl_ctx(sc->rl_dev); 3979 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); 3980 3981 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats", 3982 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 3983 re_sysctl_stats, "I", "Statistics Information"); 3984 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 3985 return; 3986 3987 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod", 3988 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 3989 &sc->rl_int_rx_mod, 0, sysctl_hw_re_int_mod, "I", 3990 "re RX interrupt moderation"); 3991 /* Pull in device tunables. */ 3992 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3993 error = resource_int_value(device_get_name(sc->rl_dev), 3994 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod); 3995 if (error == 0) { 3996 if (sc->rl_int_rx_mod < RL_TIMER_MIN || 3997 sc->rl_int_rx_mod > RL_TIMER_MAX) { 3998 device_printf(sc->rl_dev, "int_rx_mod value out of " 3999 "range; using default: %d\n", 4000 RL_TIMER_DEFAULT); 4001 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 4002 } 4003 } 4004} 4005 4006static int 4007re_sysctl_stats(SYSCTL_HANDLER_ARGS) 4008{ 4009 struct rl_softc *sc; 4010 struct rl_stats *stats; 4011 int error, i, result; 4012 4013 result = -1; 4014 error = sysctl_handle_int(oidp, &result, 0, req); 4015 if (error || req->newptr == NULL) 4016 return (error); 4017 4018 if (result == 1) { 4019 sc = (struct rl_softc *)arg1; 4020 RL_LOCK(sc); 4021 if ((if_getdrvflags(sc->rl_ifp) & IFF_DRV_RUNNING) == 0) { 4022 RL_UNLOCK(sc); 4023 goto done; 4024 } 4025 bus_dmamap_sync(sc->rl_ldata.rl_stag, 4026 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD); 4027 CSR_WRITE_4(sc, RL_DUMPSTATS_HI, 4028 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr)); 4029 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 4030 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr)); 4031 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 4032 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr | 4033 RL_DUMPSTATS_START)); 4034 for (i = RL_TIMEOUT; i > 0; i--) { 4035 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) & 4036 RL_DUMPSTATS_START) == 0) 4037 break; 4038 DELAY(1000); 4039 } 4040 bus_dmamap_sync(sc->rl_ldata.rl_stag, 4041 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD); 4042 RL_UNLOCK(sc); 4043 if (i == 0) { 4044 device_printf(sc->rl_dev, 4045 "DUMP statistics request timed out\n"); 4046 return (ETIMEDOUT); 4047 } 4048done: 4049 stats = sc->rl_ldata.rl_stats; 4050 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev)); 4051 printf("Tx frames : %ju\n", 4052 (uintmax_t)le64toh(stats->rl_tx_pkts)); 4053 printf("Rx frames : %ju\n", 4054 (uintmax_t)le64toh(stats->rl_rx_pkts)); 4055 printf("Tx errors : %ju\n", 4056 (uintmax_t)le64toh(stats->rl_tx_errs)); 4057 printf("Rx errors : %u\n", 4058 le32toh(stats->rl_rx_errs)); 4059 printf("Rx missed frames : %u\n", 4060 (uint32_t)le16toh(stats->rl_missed_pkts)); 4061 printf("Rx frame alignment errs : %u\n", 4062 (uint32_t)le16toh(stats->rl_rx_framealign_errs)); 4063 printf("Tx single collisions : %u\n", 4064 le32toh(stats->rl_tx_onecoll)); 4065 printf("Tx multiple collisions : %u\n", 4066 le32toh(stats->rl_tx_multicolls)); 4067 printf("Rx unicast frames : %ju\n", 4068 (uintmax_t)le64toh(stats->rl_rx_ucasts)); 4069 printf("Rx broadcast frames : %ju\n", 4070 (uintmax_t)le64toh(stats->rl_rx_bcasts)); 4071 printf("Rx multicast frames : %u\n", 4072 le32toh(stats->rl_rx_mcasts)); 4073 printf("Tx aborts : %u\n", 4074 (uint32_t)le16toh(stats->rl_tx_aborts)); 4075 printf("Tx underruns : %u\n", 4076 (uint32_t)le16toh(stats->rl_rx_underruns)); 4077 } 4078 4079 return (error); 4080} 4081 4082static int 4083sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4084{ 4085 int error, value; 4086 4087 if (arg1 == NULL) 4088 return (EINVAL); 4089 value = *(int *)arg1; 4090 error = sysctl_handle_int(oidp, &value, 0, req); 4091 if (error || req->newptr == NULL) 4092 return (error); 4093 if (value < low || value > high) 4094 return (EINVAL); 4095 *(int *)arg1 = value; 4096 4097 return (0); 4098} 4099 4100static int 4101sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS) 4102{ 4103 4104 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN, 4105 RL_TIMER_MAX)); 4106} 4107 4108#ifdef DEBUGNET 4109static void 4110re_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 4111{ 4112 struct rl_softc *sc; 4113 4114 sc = if_getsoftc(ifp); 4115 RL_LOCK(sc); 4116 *nrxr = sc->rl_ldata.rl_rx_desc_cnt; 4117 *ncl = DEBUGNET_MAX_IN_FLIGHT; 4118 *clsize = (if_getmtu(ifp) > RL_MTU && 4119 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) ? MJUM9BYTES : MCLBYTES; 4120 RL_UNLOCK(sc); 4121} 4122 4123static void 4124re_debugnet_event(if_t ifp __unused, enum debugnet_ev event __unused) 4125{ 4126} 4127 4128static int 4129re_debugnet_transmit(if_t ifp, struct mbuf *m) 4130{ 4131 struct rl_softc *sc; 4132 int error; 4133 4134 sc = if_getsoftc(ifp); 4135 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4136 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 4137 return (EBUSY); 4138 4139 error = re_encap(sc, &m); 4140 if (error == 0) 4141 re_start_tx(sc); 4142 return (error); 4143} 4144 4145static int 4146re_debugnet_poll(if_t ifp, int count) 4147{ 4148 struct rl_softc *sc; 4149 int error; 4150 4151 sc = if_getsoftc(ifp); 4152 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 || 4153 (sc->rl_flags & RL_FLAG_LINK) == 0) 4154 return (EBUSY); 4155 4156 re_txeof(sc); 4157 error = re_rxeof(sc, NULL); 4158 if (error != 0 && error != EAGAIN) 4159 return (error); 4160 return (0); 4161} 4162#endif /* DEBUGNET */ 4163