1/*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 5 * 6 * This code is derived from software contributed to The DragonFly Project 7 * by Sepherosa Ziehau <sepherosa@gmail.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in 17 * the documentation and/or other materials provided with the 18 * distribution. 19 * 3. Neither the name of The DragonFly Project nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific, prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 26 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 27 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 31 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * $DragonFly: src/sys/dev/netif/bwi/if_bwivar.h,v 1.14 2008/02/15 11:15:38 sephe Exp $ 37 */ 38 39#ifndef _IF_BWIVAR_H 40#define _IF_BWIVAR_H 41 42#define BWI_ALIGN 0x1000 43#define BWI_RING_ALIGN BWI_ALIGN 44#define BWI_BUS_SPACE_MAXADDR 0x3fffffff 45 46#define BWI_TX_NRING 6 47#define BWI_TXRX_NRING 6 48#define BWI_TX_NDESC 128 49#define BWI_RX_NDESC 64 50#define BWI_TXSTATS_NDESC 64 51#define BWI_TX_NSPRDESC 2 52#define BWI_TX_DATA_RING 1 53 54/* XXX Onoe/Sample/AMRR probably need different configuration */ 55#define BWI_SHRETRY 7 56#define BWI_LGRETRY 4 57#define BWI_SHRETRY_FB 3 58#define BWI_LGRETRY_FB 2 59 60#define BWI_LED_EVENT_NONE -1 61#define BWI_LED_EVENT_POLL 0 62#define BWI_LED_EVENT_TX 1 63#define BWI_LED_EVENT_RX 2 64#define BWI_LED_SLOWDOWN(dur) (dur) = (((dur) * 3) / 2) 65 66enum bwi_txpwrcb_type { 67 BWI_TXPWR_INIT = 0, 68 BWI_TXPWR_FORCE = 1, 69 BWI_TXPWR_CALIB = 2 70}; 71 72#define BWI_NOISE_FLOOR -95 /* TODO: noise floor calc */ 73#define BWI_FRAME_MIN_LEN(hdr) \ 74 ((hdr) + sizeof(struct ieee80211_frame_ack) + IEEE80211_CRC_LEN) 75 76#define CSR_READ_4(sc, reg) \ 77 bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) 78#define CSR_READ_2(sc, reg) \ 79 bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) 80 81#define CSR_WRITE_4(sc, reg, val) \ 82 bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) 83#define CSR_WRITE_2(sc, reg, val) \ 84 bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) 85 86#define CSR_SETBITS_4(sc, reg, bits) \ 87 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits)) 88#define CSR_SETBITS_2(sc, reg, bits) \ 89 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits)) 90 91#define CSR_FILT_SETBITS_4(sc, reg, filt, bits) \ 92 CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & (filt)) | (bits)) 93#define CSR_FILT_SETBITS_2(sc, reg, filt, bits) \ 94 CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits)) 95 96#define CSR_CLRBITS_4(sc, reg, bits) \ 97 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits)) 98#define CSR_CLRBITS_2(sc, reg, bits) \ 99 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits)) 100 101#ifdef BWI_DEBUG 102 103#define DPRINTF(sc, dbg, fmt, ...) \ 104do { \ 105 if ((sc)->sc_debug & (dbg)) \ 106 device_printf((sc)->sc_dev, fmt, __VA_ARGS__); \ 107} while (0) 108 109#define _DPRINTF(sc, dbg, fmt, ...) \ 110do { \ 111 if ((sc)->sc_debug & (dbg)) \ 112 printf(fmt, __VA_ARGS__); \ 113} while (0) 114 115#else /* !BWI_DEBUG */ 116 117#define DPRINTF(sc, dbg, fmt, ...) ((void)0) 118#define _DPRINTF(sc, dbg, fmt, ...) ((void)0) 119 120#endif /* BWI_DEBUG */ 121 122struct bwi_desc32 { 123 /* Little endian */ 124 uint32_t ctrl; 125 uint32_t addr; /* BWI_DESC32_A_ */ 126} __packed; 127 128#define BWI_DESC32_A_FUNC_TXRX 0x1 129#define BWI_DESC32_A_FUNC_MASK __BITS(31, 30) 130#define BWI_DESC32_A_ADDR_MASK __BITS(29, 0) 131 132#define BWI_DESC32_C_BUFLEN_MASK __BITS(12, 0) 133#define BWI_DESC32_C_ADDRHI_MASK __BITS(17, 16) 134#define BWI_DESC32_C_EOR __BIT(28) 135#define BWI_DESC32_C_INTR __BIT(29) 136#define BWI_DESC32_C_FRAME_END __BIT(30) 137#define BWI_DESC32_C_FRAME_START __BIT(31) 138 139struct bwi_desc64 { 140 /* Little endian */ 141 uint32_t ctrl0; 142 uint32_t ctrl1; 143 uint32_t addr_lo; 144 uint32_t addr_hi; 145} __packed; 146 147struct bwi_rxbuf_hdr { 148 /* Little endian */ 149 uint16_t rxh_buflen; /* exclude bwi_rxbuf_hdr */ 150 uint8_t rxh_pad1[2]; 151 uint16_t rxh_flags1; /* BWI_RXH_F1_ */ 152 uint8_t rxh_rssi; 153 uint8_t rxh_sq; 154 uint16_t rxh_phyinfo; /* BWI_RXH_PHYINFO_ */ 155 uint16_t rxh_flags3; /* BWI_RXH_F3_ */ 156 uint16_t rxh_flags2; /* BWI_RXH_F2_ */ 157 uint16_t rxh_tsf; 158 uint8_t rxh_pad3[14]; /* Padded to 30bytes */ 159} __packed; 160 161#define BWI_RXH_F1_BCM2053_RSSI __BIT(14) 162#define BWI_RXH_F1_SHPREAMBLE __BIT(7) 163#define BWI_RXH_F1_OFDM __BIT(0) 164 165#define BWI_RXH_F2_TYPE2FRAME __BIT(2) 166 167#define BWI_RXH_F3_BCM2050_RSSI __BIT(10) 168 169#define BWI_RXH_PHYINFO_LNAGAIN __BITS(15, 14) 170 171struct bwi_txbuf_hdr { 172 /* Little endian */ 173 uint32_t txh_mac_ctrl; /* BWI_TXH_MAC_C_ */ 174 uint8_t txh_fc[2]; 175 uint16_t txh_unknown1; 176 uint16_t txh_phy_ctrl; /* BWI_TXH_PHY_C_ */ 177 uint8_t txh_ivs[16]; 178 uint8_t txh_addr1[IEEE80211_ADDR_LEN]; 179 uint16_t txh_unknown2; 180 uint8_t txh_rts_fb_plcp[4]; 181 uint16_t txh_rts_fb_duration; 182 uint8_t txh_fb_plcp[4]; 183 uint16_t txh_fb_duration; 184 uint8_t txh_pad2[2]; 185 uint16_t txh_id; /* BWI_TXH_ID_ */ 186 uint16_t txh_unknown3; 187 uint8_t txh_rts_plcp[6]; 188 uint8_t txh_rts_fc[2]; 189 uint16_t txh_rts_duration; 190 uint8_t txh_rts_ra[IEEE80211_ADDR_LEN]; 191 uint8_t txh_rts_ta[IEEE80211_ADDR_LEN]; 192 uint8_t txh_pad3[2]; 193 uint8_t txh_plcp[6]; 194} __packed; 195 196#define BWI_TXH_ID_RING_MASK __BITS(15, 13) 197#define BWI_TXH_ID_IDX_MASK __BITS(12, 0) 198 199#define BWI_TXH_PHY_C_OFDM __BIT(0) 200#define BWI_TXH_PHY_C_SHPREAMBLE __BIT(4) 201#define BWI_TXH_PHY_C_ANTMODE_MASK __BITS(9, 8) 202 203#define BWI_TXH_MAC_C_ACK __BIT(0) 204#define BWI_TXH_MAC_C_FIRST_FRAG __BIT(3) 205#define BWI_TXH_MAC_C_HWSEQ __BIT(4) 206#define BWI_TXH_MAC_C_FB_OFDM __BIT(8) 207 208struct bwi_txstats { 209 /* Little endian */ 210 uint8_t txs_pad1[4]; 211 uint16_t txs_id; 212 uint8_t txs_flags; /* BWI_TXS_F_ */ 213 uint8_t txs_txcnt; /* BWI_TXS_TXCNT_ */ 214 uint8_t txs_pad2[2]; 215 uint16_t txs_seq; 216 uint16_t txs_unknown; 217 uint8_t txs_pad3[2]; /* Padded to 16bytes */ 218} __packed; 219 220#define BWI_TXS_TXCNT_DATA __BITS(7, 4) 221 222#define BWI_TXS_F_ACKED __BIT(0) 223#define BWI_TXS_F_PENDING __BIT(5) 224 225struct bwi_ring_data { 226 uint32_t rdata_txrx_ctrl; 227 bus_dmamap_t rdata_dmap; 228 bus_addr_t rdata_paddr; 229 void *rdata_desc; 230}; 231 232struct bwi_txbuf { 233 struct mbuf *tb_mbuf; 234 bus_dmamap_t tb_dmap; 235 236 struct ieee80211_node *tb_ni; 237 int tb_rate[2]; 238}; 239 240struct bwi_txbuf_data { 241 struct bwi_txbuf tbd_buf[BWI_TX_NDESC]; 242 int tbd_used; 243 int tbd_idx; 244}; 245 246struct bwi_rxbuf { 247 struct mbuf *rb_mbuf; 248 bus_addr_t rb_paddr; 249 bus_dmamap_t rb_dmap; 250}; 251 252struct bwi_rxbuf_data { 253 struct bwi_rxbuf rbd_buf[BWI_RX_NDESC]; 254 bus_dmamap_t rbd_tmp_dmap; 255 int rbd_idx; 256}; 257 258struct bwi_txstats_data { 259 bus_dma_tag_t stats_ring_dtag; 260 bus_dmamap_t stats_ring_dmap; 261 bus_addr_t stats_ring_paddr; 262 void *stats_ring; 263 264 bus_dma_tag_t stats_dtag; 265 bus_dmamap_t stats_dmap; 266 bus_addr_t stats_paddr; 267 struct bwi_txstats *stats; 268 269 uint32_t stats_ctrl_base; 270 int stats_idx; 271}; 272 273struct bwi_fwhdr { 274 /* Big endian */ 275 uint8_t fw_type; /* BWI_FW_T_ */ 276 uint8_t fw_gen; /* BWI_FW_GEN */ 277 uint8_t fw_pad[2]; 278 uint32_t fw_size; 279#define fw_iv_cnt fw_size 280} __packed; 281 282#define BWI_FWHDR_SZ sizeof(struct bwi_fwhdr) 283 284#define BWI_FW_T_UCODE 'u' 285#define BWI_FW_T_PCM 'p' 286#define BWI_FW_T_IV 'i' 287 288#define BWI_FW_GEN_1 1 289 290#define BWI_FW_VERSION3 3 291#define BWI_FW_VERSION4 4 292#define BWI_FW_VERSION3_REVMAX 0x128 293 294#define BWI_FW_PATH "bwi_v%d_" 295#define BWI_FW_STUB_PATH BWI_FW_PATH "ucode" 296#define BWI_FW_UCODE_PATH BWI_FW_PATH "ucode%d" 297#define BWI_FW_PCM_PATH BWI_FW_PATH "pcm%d" 298#define BWI_FW_IV_PATH BWI_FW_PATH "b0g0initvals%d" 299#define BWI_FW_IV_EXT_PATH BWI_FW_PATH "b0g0bsinitvals%d" 300 301struct bwi_fw_iv { 302 /* Big endian */ 303 uint16_t iv_ofs; 304 union { 305 uint32_t val32; 306 uint16_t val16; 307 } __packed iv_val; 308} __packed; 309 310#define BWI_FW_IV_OFS_MASK __BITS(14, 0) 311#define BWI_FW_IV_IS_32BIT __BIT(15) 312 313struct bwi_led { 314 uint8_t l_flags; /* BWI_LED_F_ */ 315 uint8_t l_act; /* BWI_LED_ACT_ */ 316 uint8_t l_mask; 317}; 318 319#define BWI_LED_F_ACTLOW 0x1 320#define BWI_LED_F_BLINK 0x2 321#define BWI_LED_F_POLLABLE 0x4 322#define BWI_LED_F_SLOW 0x8 323 324enum bwi_clock_mode { 325 BWI_CLOCK_MODE_SLOW, 326 BWI_CLOCK_MODE_FAST, 327 BWI_CLOCK_MODE_DYN 328}; 329 330struct bwi_regwin { 331 uint32_t rw_flags; /* BWI_REGWIN_F_ */ 332 uint16_t rw_type; /* BWI_REGWIN_T_ */ 333 uint8_t rw_id; 334 uint8_t rw_rev; 335}; 336 337#define BWI_REGWIN_F_EXIST 0x1 338 339#define BWI_CREATE_REGWIN(rw, id, type, rev) \ 340do { \ 341 (rw)->rw_flags = BWI_REGWIN_F_EXIST; \ 342 (rw)->rw_type = (type); \ 343 (rw)->rw_id = (id); \ 344 (rw)->rw_rev = (rev); \ 345} while (0) 346 347#define BWI_REGWIN_EXIST(rw) ((rw)->rw_flags & BWI_REGWIN_F_EXIST) 348#define BWI_GPIO_REGWIN(sc) \ 349 (BWI_REGWIN_EXIST(&(sc)->sc_com_regwin) ? \ 350 &(sc)->sc_com_regwin : &(sc)->sc_bus_regwin) 351 352struct bwi_mac; 353 354struct bwi_phy { 355 enum ieee80211_phymode phy_mode; 356 int phy_rev; 357 int phy_version; 358 359 uint32_t phy_flags; /* BWI_PHY_F_ */ 360 uint16_t phy_tbl_ctrl; 361 uint16_t phy_tbl_data_lo; 362 uint16_t phy_tbl_data_hi; 363 364 void (*phy_init)(struct bwi_mac *); 365}; 366 367#define BWI_PHY_F_CALIBRATED 0x1 368#define BWI_PHY_F_LINKED 0x2 369#define BWI_CLEAR_PHY_FLAGS (BWI_PHY_F_CALIBRATED) 370 371/* TX power control */ 372struct bwi_tpctl { 373 uint16_t bbp_atten; /* BBP attenuation: 4bits */ 374 uint16_t rf_atten; /* RF attenuation */ 375 uint16_t tp_ctrl1; /* ??: 3bits */ 376 uint16_t tp_ctrl2; /* ??: 4bits */ 377}; 378 379#define BWI_RF_ATTEN_FACTOR 4 380#define BWI_RF_ATTEN_MAX0 9 381#define BWI_RF_ATTEN_MAX1 31 382#define BWI_BBP_ATTEN_MAX 11 383#define BWI_TPCTL1_MAX 7 384 385struct bwi_rf_lo { 386 int8_t ctrl_lo; 387 int8_t ctrl_hi; 388}; 389 390struct bwi_rf { 391 uint16_t rf_type; /* BWI_RF_T_ */ 392 uint16_t rf_manu; 393 int rf_rev; 394 395 uint32_t rf_flags; /* BWI_RF_F_ */ 396 397#define BWI_RFLO_MAX 56 398 struct bwi_rf_lo rf_lo[BWI_RFLO_MAX]; 399 uint8_t rf_lo_used[8]; 400 401#define BWI_INVALID_NRSSI -1000 402 int16_t rf_nrssi[2]; /* Narrow RSSI */ 403 int32_t rf_nrssi_slope; 404 405#define BWI_NRSSI_TBLSZ 64 406 int8_t rf_nrssi_table[BWI_NRSSI_TBLSZ]; 407 408 uint16_t rf_lo_gain; /* loopback gain */ 409 uint16_t rf_rx_gain; /* TRSW RX gain */ 410 411 uint16_t rf_calib; /* RF calibration value */ 412 u_int rf_curchan; /* current channel */ 413 414 uint16_t rf_ctrl_rd; 415 int rf_ctrl_adj; 416 void (*rf_off)(struct bwi_mac *); 417 void (*rf_on)(struct bwi_mac *); 418 419 void (*rf_set_nrssi_thr)(struct bwi_mac *); 420 void (*rf_calc_nrssi_slope)(struct bwi_mac *); 421 int (*rf_calc_rssi) 422 (struct bwi_mac *, 423 const struct bwi_rxbuf_hdr *); 424 int (*rf_calc_noise)(struct bwi_mac *); 425 426 void (*rf_lo_update)(struct bwi_mac *); 427 428#define BWI_TSSI_MAX 64 429 int8_t rf_txpower_map0[BWI_TSSI_MAX]; 430 /* Indexed by TSSI */ 431 int rf_idle_tssi0; 432 433 int8_t rf_txpower_map[BWI_TSSI_MAX]; 434 int rf_idle_tssi; 435 436 int rf_base_tssi; 437 438 int rf_txpower_max; /* dBm */ 439 440 int rf_ant_mode; /* BWI_ANT_MODE_ */ 441}; 442 443#define BWI_RF_F_INITED 0x1 444#define BWI_RF_F_ON 0x2 445#define BWI_RF_CLEAR_FLAGS (BWI_RF_F_INITED) 446 447#define BWI_ANT_MODE_0 0 448#define BWI_ANT_MODE_1 1 449#define BWI_ANT_MODE_UNKN 2 450#define BWI_ANT_MODE_AUTO 3 451 452struct bwi_softc; 453struct firmware; 454 455struct bwi_mac { 456 struct bwi_regwin mac_regwin; /* MUST be first field */ 457#define mac_rw_flags mac_regwin.rw_flags 458#define mac_type mac_regwin.rw_type 459#define mac_id mac_regwin.rw_id 460#define mac_rev mac_regwin.rw_rev 461 462 struct bwi_softc *mac_sc; 463 464 struct bwi_phy mac_phy; /* PHY I/F */ 465 struct bwi_rf mac_rf; /* RF I/F */ 466 467 struct bwi_tpctl mac_tpctl; /* TX power control */ 468 uint32_t mac_flags; /* BWI_MAC_F_ */ 469 470 const struct firmware *mac_stub; 471 const struct firmware *mac_ucode; 472 const struct firmware *mac_pcm; 473 const struct firmware *mac_iv; 474 const struct firmware *mac_iv_ext; 475}; 476 477#define BWI_MAC_F_BSWAP 0x1 478#define BWI_MAC_F_TPCTL_INITED 0x2 479#define BWI_MAC_F_HAS_TXSTATS 0x4 480#define BWI_MAC_F_INITED 0x8 481#define BWI_MAC_F_ENABLED 0x10 482#define BWI_MAC_F_LOCKED 0x20 /* for debug */ 483#define BWI_MAC_F_TPCTL_ERROR 0x40 484#define BWI_MAC_F_PHYE_RESET 0x80 485 486#define BWI_CREATE_MAC(mac, sc, id, rev) \ 487do { \ 488 BWI_CREATE_REGWIN(&(mac)->mac_regwin, \ 489 (id), \ 490 BWI_REGWIN_T_MAC, \ 491 (rev)); \ 492 (mac)->mac_sc = (sc); \ 493} while (0) 494 495#define BWI_MAC_MAX 2 496#define BWI_LED_MAX 4 497 498enum bwi_bus_space { 499 BWI_BUS_SPACE_30BIT = 1, 500 BWI_BUS_SPACE_32BIT, 501 BWI_BUS_SPACE_64BIT 502}; 503 504#define BWI_TX_RADIOTAP_PRESENT \ 505 ((1 << IEEE80211_RADIOTAP_FLAGS) | \ 506 (1 << IEEE80211_RADIOTAP_RATE) | \ 507 (1 << IEEE80211_RADIOTAP_CHANNEL)) 508 509struct bwi_tx_radiotap_hdr { 510 struct ieee80211_radiotap_header wt_ihdr; 511 uint8_t wt_flags; 512 uint8_t wt_rate; 513 uint16_t wt_chan_freq; 514 uint16_t wt_chan_flags; 515} __packed; 516 517#define BWI_RX_RADIOTAP_PRESENT \ 518 ((1 << IEEE80211_RADIOTAP_TSFT) | \ 519 (1 << IEEE80211_RADIOTAP_FLAGS) | \ 520 (1 << IEEE80211_RADIOTAP_RATE) | \ 521 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 522 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \ 523 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE)) 524 525struct bwi_rx_radiotap_hdr { 526 struct ieee80211_radiotap_header wr_ihdr; 527 uint64_t wr_tsf; 528 uint8_t wr_flags; 529 uint8_t wr_rate; 530 uint16_t wr_chan_freq; 531 uint16_t wr_chan_flags; 532 int8_t wr_antsignal; 533 int8_t wr_antnoise; 534 /* TODO: sq */ 535} __packed __aligned(8); 536 537struct bwi_vap { 538 struct ieee80211vap bv_vap; 539 int (*bv_newstate)(struct ieee80211vap *, 540 enum ieee80211_state, int); 541}; 542#define BWI_VAP(vap) ((struct bwi_vap *)(vap)) 543 544struct bwi_softc { 545 uint32_t sc_flags; /* BWI_F_ */ 546 device_t sc_dev; 547 struct mtx sc_mtx; 548 struct ieee80211com sc_ic; 549 struct mbufq sc_snd; 550 int sc_invalid; 551 552 uint32_t sc_cap; /* BWI_CAP_ */ 553 uint16_t sc_bbp_id; /* BWI_BBPID_ */ 554 uint8_t sc_bbp_rev; 555 uint8_t sc_bbp_pkg; 556 557 uint8_t sc_pci_revid; 558 uint16_t sc_pci_did; 559 uint16_t sc_pci_subvid; 560 uint16_t sc_pci_subdid; 561 562 uint16_t sc_card_flags; /* BWI_CARD_F_ */ 563 uint16_t sc_pwron_delay; 564 int sc_locale; 565 566 int sc_irq_rid; 567 struct resource *sc_irq_res; 568 void *sc_irq_handle; 569 570 int sc_mem_rid; 571 struct resource *sc_mem_res; 572 bus_space_tag_t sc_mem_bt; 573 bus_space_handle_t sc_mem_bh; 574 575 struct callout sc_calib_ch; 576 struct callout sc_watchdog_timer; 577 578 struct bwi_regwin *sc_cur_regwin; 579 struct bwi_regwin sc_com_regwin; 580 struct bwi_regwin sc_bus_regwin; 581 582 int sc_nmac; 583 struct bwi_mac sc_mac[BWI_MAC_MAX]; 584 585 int sc_rx_rate; 586 int sc_tx_rate; 587 enum bwi_txpwrcb_type sc_txpwrcb_type; 588 589 int sc_led_blinking; 590 int sc_led_ticks; 591 struct bwi_led *sc_blink_led; 592 struct callout sc_led_blink_ch; 593 int sc_led_blink_offdur; 594 struct bwi_led sc_leds[BWI_LED_MAX]; 595 596 enum bwi_bus_space sc_bus_space; 597 bus_dma_tag_t sc_parent_dtag; 598 599 bus_dma_tag_t sc_buf_dtag; 600 struct bwi_txbuf_data sc_tx_bdata[BWI_TX_NRING]; 601 struct bwi_rxbuf_data sc_rx_bdata; 602 603 bus_dma_tag_t sc_txring_dtag; 604 struct bwi_ring_data sc_tx_rdata[BWI_TX_NRING]; 605 bus_dma_tag_t sc_rxring_dtag; 606 struct bwi_ring_data sc_rx_rdata; 607 608 struct bwi_txstats_data *sc_txstats; 609 610 int sc_tx_timer; 611 const struct ieee80211_rate_table *sc_rates; 612 613 struct bwi_tx_radiotap_hdr sc_tx_th; 614 struct bwi_rx_radiotap_hdr sc_rx_th; 615 616 struct taskqueue *sc_tq; 617 struct task sc_restart_task; 618 619 int (*sc_init_tx_ring)(struct bwi_softc *, int); 620 void (*sc_free_tx_ring)(struct bwi_softc *, int); 621 622 int (*sc_init_rx_ring)(struct bwi_softc *); 623 void (*sc_free_rx_ring)(struct bwi_softc *); 624 625 int (*sc_init_txstats)(struct bwi_softc *); 626 void (*sc_free_txstats)(struct bwi_softc *); 627 628 void (*sc_setup_rxdesc) 629 (struct bwi_softc *, int, bus_addr_t, int); 630 int (*sc_rxeof)(struct bwi_softc *); 631 632 void (*sc_setup_txdesc) 633 (struct bwi_softc *, struct bwi_ring_data *, 634 int, bus_addr_t, int); 635 void (*sc_start_tx) 636 (struct bwi_softc *, uint32_t, int); 637 638 void (*sc_txeof_status)(struct bwi_softc *); 639 640 /* Sysctl variables */ 641 int sc_fw_version; /* BWI_FW_VERSION[34] */ 642 int sc_dwell_time; /* milliseconds */ 643 int sc_led_idle; 644 int sc_led_blink; 645 int sc_txpwr_calib; 646 uint32_t sc_debug; /* BWI_DBG_ */ 647}; 648 649#define BWI_F_BUS_INITED 0x1 650#define BWI_F_PROMISC 0x2 651#define BWI_F_STOP 0x4 652#define BWI_F_RUNNING 0x8 653 654#define BWI_DBG_MAC 0x00000001 655#define BWI_DBG_RF 0x00000002 656#define BWI_DBG_PHY 0x00000004 657#define BWI_DBG_MISC 0x00000008 658 659#define BWI_DBG_ATTACH 0x00000010 660#define BWI_DBG_INIT 0x00000020 661#define BWI_DBG_FIRMWARE 0x00000040 662#define BWI_DBG_80211 0x00000080 663#define BWI_DBG_TXPOWER 0x00000100 664#define BWI_DBG_INTR 0x00000200 665#define BWI_DBG_RX 0x00000400 666#define BWI_DBG_TX 0x00000800 667#define BWI_DBG_TXEOF 0x00001000 668#define BWI_DBG_LED 0x00002000 669 670#define BWI_LOCK_INIT(sc) \ 671 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->sc_dev), \ 672 MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE) 673#define BWI_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx) 674#define BWI_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 675#define BWI_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 676#define BWI_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) 677 678int bwi_attach(struct bwi_softc *); 679int bwi_detach(struct bwi_softc *); 680void bwi_suspend(struct bwi_softc *); 681void bwi_resume(struct bwi_softc *); 682int bwi_shutdown(struct bwi_softc *); 683void bwi_intr(void *); 684 685int bwi_bus_init(struct bwi_softc *, struct bwi_mac *mac); 686 687uint16_t bwi_read_sprom(struct bwi_softc *, uint16_t); 688int bwi_regwin_switch(struct bwi_softc *, struct bwi_regwin *, 689 struct bwi_regwin **); 690int bwi_regwin_is_enabled(struct bwi_softc *, struct bwi_regwin *); 691void bwi_regwin_enable(struct bwi_softc *, struct bwi_regwin *, 692 uint32_t); 693void bwi_regwin_disable(struct bwi_softc *, struct bwi_regwin *, 694 uint32_t); 695 696#define abs(a) __builtin_abs(a) 697 698/* XXX does not belong here */ 699struct ieee80211_ds_plcp_hdr { 700 uint8_t i_signal; 701 uint8_t i_service; 702 uint16_t i_length; 703 uint16_t i_crc; 704} __packed; 705 706#endif /* !_IF_BWIVAR_H */ 707